scivar.h revision 1.9
1 /* $NetBSD: scivar.h,v 1.9 1996/04/21 21:12:26 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)scivar.h 7.1 (Berkeley) 5/8/90 39 */ 40 #ifndef _SCIVAR_H_ 41 #define _SCIVAR_H_ 42 43 struct sci_pending { 44 TAILQ_ENTRY(sci_pending) link; 45 struct scsi_xfer *xs; 46 }; 47 48 struct sci_softc; 49 50 struct sci_softc { 51 struct device sc_dev; 52 struct isr sc_isr; 53 struct scsi_link sc_link; /* proto for sub devices */ 54 TAILQ_HEAD(,sci_pending) sc_xslist; 55 struct sci_pending sc_xsstore[8][8]; 56 struct scsi_xfer *sc_xs; /* transfer from high level code */ 57 58 volatile u_char *sci_data; /* r: Current data */ 59 volatile u_char *sci_odata; /* w: Out data */ 60 volatile u_char *sci_icmd; /* rw: Initiator command */ 61 volatile u_char *sci_mode; /* rw: Mode */ 62 volatile u_char *sci_tcmd; /* rw: Target command */ 63 volatile u_char *sci_bus_csr; /* r: Bus Status */ 64 volatile u_char *sci_sel_enb; /* w: Select enable */ 65 volatile u_char *sci_csr; /* r: Status */ 66 volatile u_char *sci_dma_send; /* w: Start dma send data */ 67 volatile u_char *sci_idata; /* r: Input data */ 68 volatile u_char *sci_trecv; /* w: Start dma receive, target */ 69 volatile u_char *sci_iack; /* r: Interrupt Acknowledge */ 70 volatile u_char *sci_irecv; /* w: Start dma receive, initiator */ 71 72 /* psuedo DMA transfer */ 73 int (*dma_xfer_in) (); 74 /* psuedo DMA transfer */ 75 int (*dma_xfer_out) (); 76 u_char sc_flags; 77 u_char sc_lun; 78 /* one for each target */ 79 struct syncpar { 80 u_char state; 81 u_char period, offset; 82 } sc_sync[8]; 83 u_char sc_slave; 84 u_char sc_scsi_addr; 85 u_char sc_stat[2]; 86 u_char sc_msg[8]; 87 }; 88 89 /* sc_flags */ 90 #define SCI_IO 0x80 /* DMA I/O in progress */ 91 #define SCI_ALIVE 0x01 /* controller initialized */ 92 #define SCI_SELECTED 0x04 /* bus is in selected state. Needed for 93 correct abort procedure. */ 94 95 /* sync states */ 96 #define SYNC_START 0 /* no sync handshake started */ 97 #define SYNC_SENT 1 /* we sent sync request, no answer yet */ 98 #define SYNC_DONE 2 /* target accepted our (or inferior) settings, 99 or it rejected the request and we stay async */ 100 101 #define PHASE 0x07 /* mask for psns/pctl phase */ 102 #define DATA_OUT_PHASE 0x00 103 #define DATA_IN_PHASE 0x01 104 #define CMD_PHASE 0x02 105 #define STATUS_PHASE 0x03 106 #define BUS_FREE_PHASE 0x04 107 #define ARB_SEL_PHASE 0x05 /* Fuji chip combines arbitration with sel. */ 108 #define MESG_OUT_PHASE 0x06 109 #define MESG_IN_PHASE 0x07 110 111 #define MSG_CMD_COMPLETE 0x00 112 #define MSG_EXT_MESSAGE 0x01 113 #define MSG_SAVE_DATA_PTR 0x02 114 #define MSG_RESTORE_PTR 0x03 115 #define MSG_DISCONNECT 0x04 116 #define MSG_INIT_DETECT_ERROR 0x05 117 #define MSG_ABORT 0x06 118 #define MSG_REJECT 0x07 119 #define MSG_NOOP 0x08 120 #define MSG_PARITY_ERROR 0x09 121 #define MSG_BUS_DEVICE_RESET 0x0C 122 #define MSG_IDENTIFY 0x80 123 #define MSG_IDENTIFY_DR 0xc0 /* (disconnect/reconnect allowed) */ 124 #define MSG_SYNC_REQ 0x01 125 126 127 #define STS_CHECKCOND 0x02 /* Check Condition (ie., read sense) */ 128 #define STS_CONDMET 0x04 /* Condition Met (ie., search worked) */ 129 #define STS_BUSY 0x08 130 #define STS_INTERMED 0x10 /* Intermediate status sent */ 131 #define STS_EXT 0x80 /* Extended status valid */ 132 133 /* 134 * XXXX 135 */ 136 struct scsi_fmt_cdb { 137 int len; /* cdb length (in bytes) */ 138 u_char cdb[28]; /* cdb to use on next read/write */ 139 }; 140 141 struct buf; 142 struct scsi_xfer; 143 144 void sci_minphys __P((struct buf *)); 145 int sci_scsicmd __P((struct scsi_xfer *)); 146 void scireset __P((struct sci_softc *)); 147 148 #endif /* _SCIVAR_H_ */ 149
Indexes created Wed Sep 24 05:09:52 GMT 2025