siop.c revision 1.13
1 /* 2 * Copyright (c) 1994 Michael L. Hitch 3 * Copyright (c) 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Van Jacobson of Lawrence Berkeley Laboratory. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)siop.c 7.5 (Berkeley) 5/4/91 38 * $Id: siop.c,v 1.13 1994/06/14 01:01:56 chopps Exp $ 39 */ 40 41 /* 42 * AMIGA 53C710 scsi adaptor driver 43 */ 44 45 /* need to know if any tapes have been configured */ 46 #include "st.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 #include <machine/cpu.h> 55 #include <amiga/amiga/custom.h> 56 #include <amiga/dev/siopreg.h> 57 #include <amiga/dev/siopvar.h> 58 59 extern u_int kvtop(); 60 61 /* 62 * SCSI delays 63 * In u-seconds, primarily for state changes on the SPC. 64 */ 65 #define SCSI_CMD_WAIT 500000 /* wait per step of 'immediate' cmds */ 66 #define SCSI_DATA_WAIT 500000 /* wait per data in/out step */ 67 #define SCSI_INIT_WAIT 500000 /* wait per step (both) during init */ 68 69 int siopicmd __P((struct siop_softc *, int, void *, int, void *, int)); 70 int siopgo __P((struct siop_softc *, struct scsi_xfer *)); 71 int siopgetsense __P((struct siop_softc *, struct scsi_xfer *)); 72 void siopabort __P((struct siop_softc *, siop_regmap_p, char *)); 73 void sioperror __P((struct siop_softc *, siop_regmap_p, u_char)); 74 void siopstart __P((struct siop_softc *)); 75 void siopreset __P((struct siop_softc *)); 76 void siopsetdelay __P((int)); 77 void siop_scsidone __P((struct siop_softc *, int)); 78 void siop_donextcmd __P((struct siop_softc *)); 79 int siopintr __P((struct siop_softc *)); 80 81 /* 53C710 script */ 82 unsigned long scripts[] = { 83 0x47000000, 0x00000298, /* 000 - 0 */ 84 0x838b0000, 0x000000d0, /* 008 - 8 */ 85 0x7a1b1000, 0x00000000, /* 010 - 16 */ 86 0x828a0000, 0x00000088, /* 018 - 24 */ 87 0x9e020000, 0x0000ff01, /* 020 - 32 */ 88 0x72350000, 0x00000000, /* 028 - 40 */ 89 0x808c0000, 0x00000048, /* 030 - 48 */ 90 0x58000008, 0x00000000, /* 038 - 56 */ 91 0x1e000024, 0x00000024, /* 040 - 64 */ 92 0x838b0000, 0x00000090, /* 048 - 72 */ 93 0x1f00002c, 0x0000002c, /* 050 - 80 */ 94 0x838b0000, 0x00000080, /* 058 - 88 */ 95 0x868a0000, 0xffffffd0, /* 060 - 96 */ 96 0x838a0000, 0x00000070, /* 068 - 104 */ 97 0x878a0000, 0x00000120, /* 070 - 112 */ 98 0x80880000, 0x00000028, /* 078 - 120 */ 99 0x1e000004, 0x00000004, /* 080 - 128 */ 100 0x838b0000, 0x00000050, /* 088 - 136 */ 101 0x868a0000, 0xffffffe8, /* 090 - 144 */ 102 0x838a0000, 0x00000040, /* 098 - 152 */ 103 0x878a0000, 0x000000f0, /* 0a0 - 160 */ 104 0x9a020000, 0x0000ff02, /* 0a8 - 168 */ 105 0x1a00000c, 0x0000000c, /* 0b0 - 176 */ 106 0x878b0000, 0x00000130, /* 0b8 - 184 */ 107 0x838a0000, 0x00000018, /* 0c0 - 192 */ 108 0x818a0000, 0x000000b0, /* 0c8 - 200 */ 109 0x808a0000, 0x00000080, /* 0d0 - 208 */ 110 0x98080000, 0x0000ff03, /* 0d8 - 216 */ 111 0x1b000014, 0x00000014, /* 0e0 - 224 */ 112 0x72090000, 0x00000000, /* 0e8 - 232 */ 113 0x6a340000, 0x00000000, /* 0f0 - 240 */ 114 0x9f030000, 0x0000ff04, /* 0f8 - 248 */ 115 0x1f00001c, 0x0000001c, /* 100 - 256 */ 116 0x98040000, 0x0000ff26, /* 108 - 264 */ 117 0x60000040, 0x00000000, /* 110 - 272 */ 118 0x48000000, 0x00000000, /* 118 - 280 */ 119 0x7c1bef00, 0x00000000, /* 120 - 288 */ 120 0x72340000, 0x00000000, /* 128 - 296 */ 121 0x980c0002, 0x0000fffc, /* 130 - 304 */ 122 0x980c0008, 0x0000fffb, /* 138 - 312 */ 123 0x980c0018, 0x0000fffd, /* 140 - 320 */ 124 0x98040000, 0x0000fffe, /* 148 - 328 */ 125 0x98080000, 0x0000ff00, /* 150 - 336 */ 126 0x18000034, 0x00000034, /* 158 - 344 */ 127 0x808b0000, 0x000001c0, /* 160 - 352 */ 128 0x838b0000, 0xffffff70, /* 168 - 360 */ 129 0x878a0000, 0x000000d0, /* 170 - 368 */ 130 0x98080000, 0x0000ff05, /* 178 - 376 */ 131 0x19000034, 0x00000034, /* 180 - 384 */ 132 0x818b0000, 0x00000160, /* 188 - 392 */ 133 0x80880000, 0xffffffd0, /* 190 - 400 */ 134 0x1f00001c, 0x0000001c, /* 198 - 408 */ 135 0x808c0001, 0x00000018, /* 1a0 - 416 */ 136 0x980c0002, 0x0000ff08, /* 1a8 - 424 */ 137 0x808c0004, 0x00000020, /* 1b0 - 432 */ 138 0x98080000, 0x0000ff06, /* 1b8 - 440 */ 139 0x60000040, 0x00000000, /* 1c0 - 448 */ 140 0x1f00002c, 0x0000002c, /* 1c8 - 456 */ 141 0x98080000, 0x0000ff07, /* 1d0 - 464 */ 142 0x60000040, 0x00000000, /* 1d8 - 472 */ 143 0x48000000, 0x00000000, /* 1e0 - 480 */ 144 0x98080000, 0x0000ff09, /* 1e8 - 488 */ 145 0x1f00001c, 0x0000001c, /* 1f0 - 496 */ 146 0x808c0001, 0x00000018, /* 1f8 - 504 */ 147 0x980c0002, 0x0000ff10, /* 200 - 512 */ 148 0x808c0004, 0x00000020, /* 208 - 520 */ 149 0x98080000, 0x0000ff11, /* 210 - 528 */ 150 0x60000040, 0x00000000, /* 218 - 536 */ 151 0x1f00002c, 0x0000002c, /* 220 - 544 */ 152 0x98080000, 0x0000ff12, /* 228 - 552 */ 153 0x60000040, 0x00000000, /* 230 - 560 */ 154 0x48000000, 0x00000000, /* 238 - 568 */ 155 0x98080000, 0x0000ff13, /* 240 - 576 */ 156 0x1f00001c, 0x0000001c, /* 248 - 584 */ 157 0x808c0001, 0x00000018, /* 250 - 592 */ 158 0x980c0002, 0x0000ff14, /* 258 - 600 */ 159 0x808c0004, 0x00000020, /* 260 - 608 */ 160 0x98080000, 0x0000ff15, /* 268 - 616 */ 161 0x60000040, 0x00000000, /* 270 - 624 */ 162 0x1f00002c, 0x0000002c, /* 278 - 632 */ 163 0x98080000, 0x0000ff16, /* 280 - 640 */ 164 0x60000040, 0x00000000, /* 288 - 648 */ 165 0x48000000, 0x00000000, /* 290 - 656 */ 166 0x98080000, 0x0000ff17, /* 298 - 664 */ 167 0x54000000, 0x00000040, /* 2a0 - 672 */ 168 0x9f030000, 0x0000ff18, /* 2a8 - 680 */ 169 0x1f00001c, 0x0000001c, /* 2b0 - 688 */ 170 0x990b0000, 0x0000ff19, /* 2b8 - 696 */ 171 0x980a0000, 0x0000ff20, /* 2c0 - 704 */ 172 0x9f0a0000, 0x0000ff21, /* 2c8 - 712 */ 173 0x9b0a0000, 0x0000ff22, /* 2d0 - 720 */ 174 0x9e0a0000, 0x0000ff23, /* 2d8 - 728 */ 175 0x98080000, 0x0000ff24, /* 2e0 - 736 */ 176 0x98080000, 0x0000ff25, /* 2e8 - 744 */ 177 0x76100800, 0x00000000, /* 2f0 - 752 */ 178 0x80840700, 0x00000008, /* 2f8 - 760 */ 179 0x7e110100, 0x00000000, /* 300 - 768 */ 180 0x6a100000, 0x00000000, /* 308 - 776 */ 181 0x19000034, 0x00000034, /* 310 - 784 */ 182 0x818b0000, 0xffffffd0, /* 318 - 792 */ 183 0x98080000, 0x0000ff27, /* 320 - 800 */ 184 0x76100800, 0x00000000, /* 328 - 808 */ 185 0x80840700, 0x00000008, /* 330 - 816 */ 186 0x7e110100, 0x00000000, /* 338 - 824 */ 187 0x6a100000, 0x00000000, /* 340 - 832 */ 188 0x18000034, 0x00000034, /* 348 - 840 */ 189 0x808b0000, 0xffffffd0, /* 350 - 848 */ 190 0x98080000, 0x0000ff27 /* 358 - 856 */ 191 }; 192 193 #define Ent_msgout 0x00000018 194 #define Ent_cmd 0x000000a8 195 #define Ent_status 0x000000e0 196 #define Ent_msgin 0x000000f8 197 #define Ent_dataout 0x00000158 198 #define Ent_datain 0x00000180 199 200 /* default to not inhibit sync negotiation on any drive */ 201 /* XXXX - unit 2 inhibits sync for my WangTek tape drive - mlh */ 202 u_char siop_inhibit_sync[8] = { 0, 0, 1, 0, 0, 0, 0 }; /* initialize, so patchable */ 203 int siop_no_dma = 0; 204 205 int siop_reset_delay = 2000; /* delay after reset, in milleseconds */ 206 int siop_sync_period = 50; /* synchronous transfer period, in nanoseconds */ 207 208 int siop_cmd_wait = SCSI_CMD_WAIT; 209 int siop_data_wait = SCSI_DATA_WAIT; 210 int siop_init_wait = SCSI_INIT_WAIT; 211 212 static struct { 213 unsigned char x; /* period from sync request message */ 214 unsigned char y; /* siop_period << 4 | sbcl */ 215 } xxx[] = { 216 {0x0f, 0x01}, 217 {0x13, 0x11}, 218 {0x17, 0x21}, 219 /* {0x17, 0x02}, */ 220 {0x1b, 0x31}, 221 {0x1d, 0x12}, 222 {0x1e, 0x41}, 223 /* {0x1e, 0x03}, */ 224 {0x22, 0x51}, 225 {0x23, 0x22}, 226 {0x26, 0x61}, 227 /* {0x26, 0x13}, */ 228 {0x29, 0x32}, 229 {0x2a, 0x71}, 230 {0x2d, 0x23}, 231 {0x2e, 0x42}, 232 {0x34, 0x52}, 233 {0x35, 0x33}, 234 {0x3a, 0x62}, 235 {0x3c, 0x43}, 236 {0x40, 0x72}, 237 {0x44, 0x53}, 238 {0x4b, 0x63}, 239 {0x53, 0x73} 240 }; 241 242 #ifdef DEBUG 243 #define QPRINTF(a) if (siop_debug > 1) printf a 244 /* 245 * 0x01 - full debug 246 * 0x02 - DMA chaining 247 * 0x04 - siopintr 248 * 0x08 - phase mismatch 249 * 0x10 - panic on phase mismatch 250 */ 251 int siop_debug = 0; 252 int siopsync_debug = 0; 253 int siopdma_hits = 0; 254 int siopdma_misses = 0; 255 #endif 256 257 258 /* 259 * default minphys routine for siop based controllers 260 */ 261 void 262 siop_minphys(bp) 263 struct buf *bp; 264 { 265 /* 266 * no max transfer at this level 267 */ 268 } 269 270 /* 271 * must be used 272 */ 273 u_int 274 siop_adinfo() 275 { 276 /* 277 * one request at a time please 278 */ 279 return(1); 280 } 281 282 /* 283 * used by specific siop controller 284 * 285 * it appears that the higher level code does nothing with LUN's 286 * so I will too. I could plug it in, however so could they 287 * in scsi_scsi_cmd(). 288 */ 289 int 290 siop_scsicmd(xs) 291 struct scsi_xfer *xs; 292 { 293 struct siop_pending *pendp; 294 struct siop_softc *dev; 295 struct scsi_link *slp; 296 int flags, s; 297 298 slp = xs->sc_link; 299 dev = slp->adapter_softc; 300 flags = xs->flags; 301 302 if (flags & SCSI_DATA_UIO) 303 panic("siop: scsi data uio requested"); 304 305 if (dev->sc_xs && flags & SCSI_NOMASK) 306 panic("siop_scsicmd: busy"); 307 308 s = splbio(); 309 pendp = &dev->sc_xsstore[slp->target][slp->lun]; 310 if (pendp->xs) { 311 splx(s); 312 return(TRY_AGAIN_LATER); 313 } 314 315 if (dev->sc_xs) { 316 pendp->xs = xs; 317 TAILQ_INSERT_TAIL(&dev->sc_xslist, pendp, link); 318 splx(s); 319 return(SUCCESSFULLY_QUEUED); 320 } 321 pendp->xs = NULL; 322 dev->sc_xs = xs; 323 splx(s); 324 325 /* 326 * nothing is pending do it now. 327 */ 328 siop_donextcmd(dev); 329 330 if (flags & SCSI_NOMASK) 331 return(COMPLETE); 332 return(SUCCESSFULLY_QUEUED); 333 } 334 335 /* 336 * entered with dev->sc_xs pointing to the next xfer to perform 337 */ 338 void 339 siop_donextcmd(dev) 340 struct siop_softc *dev; 341 { 342 struct scsi_xfer *xs; 343 struct scsi_link *slp; 344 int flags, phase, stat; 345 346 xs = dev->sc_xs; 347 slp = xs->sc_link; 348 flags = xs->flags; 349 350 #if 0 351 if (flags & SCSI_DATA_IN) 352 phase = DATA_IN_PHASE; 353 else if (flags & SCSI_DATA_OUT) 354 phase = DATA_OUT_PHASE; 355 else 356 phase = STATUS_PHASE; 357 #endif 358 359 if (flags & SCSI_RESET) 360 siopreset(dev); 361 362 dev->sc_stat[0] = -1; 363 #if 0 364 if (phase == STATUS_PHASE || flags & SCSI_NOMASK) 365 #else 366 if (flags & SCSI_NOMASK || siop_no_dma) 367 #endif 368 stat = siopicmd(dev, slp->target, xs->cmd, xs->cmdlen, 369 xs->data, xs->datalen/*, phase*/); 370 else if (siopgo(dev, xs) == 0) 371 return; 372 else 373 stat = dev->sc_stat[0]; 374 375 siop_scsidone(dev, stat); 376 } 377 378 void 379 siop_scsidone(dev, stat) 380 struct siop_softc *dev; 381 int stat; 382 { 383 struct siop_pending *pendp; 384 struct scsi_xfer *xs; 385 int s, donext; 386 387 xs = dev->sc_xs; 388 #ifdef DIAGNOSTIC 389 if (xs == NULL) 390 panic("siop_scsidone"); 391 #endif 392 /* 393 * is this right? 394 */ 395 xs->status = stat; 396 397 if (stat == 0 || xs->flags & SCSI_ERR_OK) 398 xs->resid = 0; 399 else { 400 switch(stat) { 401 case SCSI_CHECK: 402 if (stat = siopgetsense(dev, xs)) 403 goto bad_sense; 404 xs->error = XS_SENSE; 405 break; 406 case SCSI_BUSY: 407 xs->error = XS_BUSY; 408 break; 409 bad_sense: 410 default: 411 xs->error = XS_DRIVER_STUFFUP; 412 QPRINTF(("siop_scsicmd() bad %x\n", stat)); 413 break; 414 } 415 } 416 xs->flags |= ITSDONE; 417 418 /* 419 * grab next command before scsi_done() 420 * this way no single device can hog scsi resources. 421 */ 422 s = splbio(); 423 pendp = dev->sc_xslist.tqh_first; 424 if (pendp == NULL) { 425 donext = 0; 426 dev->sc_xs = NULL; 427 } else { 428 donext = 1; 429 TAILQ_REMOVE(&dev->sc_xslist, pendp, link); 430 dev->sc_xs = pendp->xs; 431 pendp->xs = NULL; 432 } 433 splx(s); 434 scsi_done(xs); 435 436 if (donext) 437 siop_donextcmd(dev); 438 } 439 440 int 441 siopgetsense(dev, xs) 442 struct siop_softc *dev; 443 struct scsi_xfer *xs; 444 { 445 struct scsi_sense rqs; 446 struct scsi_link *slp; 447 int stat; 448 449 slp = xs->sc_link; 450 451 rqs.op_code = REQUEST_SENSE; 452 rqs.byte2 = slp->lun << 5; 453 #ifdef not_yet 454 rqs.length = xs->req_sense_length ? xs->req_sense_length : 455 sizeof(xs->sense); 456 #else 457 rqs.length = sizeof(xs->sense); 458 #endif 459 if (rqs.length > sizeof (xs->sense)) 460 rqs.length = sizeof (xs->sense); 461 rqs.unused[0] = rqs.unused[1] = rqs.control = 0; 462 463 return(siopicmd(dev, slp->target, &rqs, sizeof(rqs), &xs->sense, 464 rqs.length)); 465 } 466 467 void 468 siopabort(dev, regs, where) 469 register struct siop_softc *dev; 470 siop_regmap_p regs; 471 char *where; 472 { 473 474 printf ("%s: abort %s: dstat %02x, sstat0 %02x sbcl %02x\n", 475 dev->sc_dev.dv_xname, 476 where, regs->siop_dstat, regs->siop_sstat0, regs->siop_sbcl); 477 478 if (dev->sc_flags & SIOP_SELECTED) { 479 #ifdef TODO 480 SET_SBIC_cmd (regs, SBIC_CMD_ABORT); 481 WAIT_CIP (regs); 482 483 GET_SBIC_asr (regs, asr); 484 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) 485 { 486 /* ok, get more drastic.. */ 487 488 SET_SBIC_cmd (regs, SBIC_CMD_RESET); 489 delay(25); 490 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 491 GET_SBIC_csr (regs, csr); /* clears interrupt also */ 492 493 dev->sc_flags &= ~SIOP_SELECTED; 494 return; 495 } 496 497 do 498 { 499 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 500 GET_SBIC_csr (regs, csr); 501 } 502 while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 503 && (csr != SBIC_CSR_CMD_INVALID)); 504 #endif 505 506 /* lets just hope it worked.. */ 507 dev->sc_flags &= ~SIOP_SELECTED; 508 } 509 } 510 511 /* 512 * XXX Set/reset long delays. 513 * 514 * if delay == 0, reset default delays 515 * if delay < 0, set both delays to default long initialization values 516 * if delay > 0, set both delays to this value 517 * 518 * Used when a devices is expected to respond slowly (e.g. during 519 * initialization). 520 */ 521 void 522 siop_delay(delay) 523 int delay; 524 { 525 static int saved_cmd_wait, saved_data_wait; 526 527 if (delay) { 528 saved_cmd_wait = siop_cmd_wait; 529 saved_data_wait = siop_data_wait; 530 if (delay > 0) 531 siop_cmd_wait = siop_data_wait = delay; 532 else 533 siop_cmd_wait = siop_data_wait = siop_init_wait; 534 } else { 535 siop_cmd_wait = saved_cmd_wait; 536 siop_data_wait = saved_data_wait; 537 } 538 } 539 540 void 541 siopinitialize(dev) 542 struct siop_softc *dev; 543 { 544 /* 545 * check that scripts is on a long word boundary 546 * and that DS is on a long word boundary 547 */ 548 dev->sc_scriptspa = kvtop(scripts); 549 dev->sc_dspa = kvtop(&dev->sc_ds); 550 dev->sc_lunpa = kvtop(&dev->sc_lun); 551 dev->sc_statuspa = kvtop(&dev->sc_stat[0]); 552 dev->sc_msgpa = kvtop(&dev->sc_msg[0]); 553 siopreset (dev); 554 } 555 556 void 557 siopreset(dev) 558 struct siop_softc *dev; 559 { 560 siop_regmap_p regs; 561 u_int i, s; 562 u_char my_id, csr; 563 564 regs = dev->sc_siopp; 565 566 if (dev->sc_flags & SIOP_ALIVE) 567 siopabort(dev, regs, "reset"); 568 569 printf("\n%s: ", dev->sc_dev.dv_xname); /* XXXX */ 570 571 s = splbio(); 572 my_id = 7; 573 574 /* 575 * Reset the chip 576 * XXX - is this really needed? 577 */ 578 regs->siop_sien &= ~SIOP_SIEN_RST; 579 regs->siop_scntl1 |= SIOP_SCNTL1_RST; 580 for (i = 0; i < 1000; ++i) 581 ; 582 regs->siop_scntl1 &= ~SIOP_SCNTL1_RST; 583 regs->siop_sien |= SIOP_SIEN_RST; 584 585 /* 586 * Set up various chip parameters 587 */ 588 regs->siop_istat = 0x40; 589 for (i = 0; i < 1000; ++i) 590 ; 591 regs->siop_istat = 0x00; 592 regs->siop_scntl0 = SIOP_ARB_FULL | SIOP_SCNTL0_EPC | SIOP_SCNTL0_EPG; 593 regs->siop_dcntl = dev->sc_clock_freq & 0xff; 594 regs->siop_dmode = 0x80; /* burst length = 4 */ 595 regs->siop_sien = 0x00; /* don't enable interrupts yet */ 596 regs->siop_dien = 0x00; /* don't enable interrupts yet */ 597 regs->siop_scid = 1 << my_id; 598 regs->siop_dwt = 0x00; 599 regs->siop_ctest0 |= 0x20; /* Enable Active Negation ?? */ 600 regs->siop_ctest7 |= (dev->sc_clock_freq >> 8) & 0xff; 601 602 /* will need to re-negotiate sync xfers */ 603 bzero(&dev->sc_sync, sizeof (dev->sc_sync)); 604 605 splx (s); 606 607 delay (siop_reset_delay * 1000); 608 printf("siop id %d reset\n", my_id); 609 dev->sc_flags |= SIOP_ALIVE; 610 dev->sc_flags &= ~(SIOP_SELECTED | SIOP_DMA); 611 } 612 613 /* 614 * Setup Data Storage for 53C710 and start SCRIPTS processing 615 */ 616 617 void 618 siop_setup (dev, target, cbuf, clen, buf, len) 619 struct siop_softc *dev; 620 int target; 621 u_char *cbuf; 622 int clen; 623 u_char *buf; 624 int len; 625 { 626 siop_regmap_p regs = dev->sc_siopp; 627 int i; 628 int nchain; 629 int count, tcount; 630 char *addr, *dmaend; 631 632 dev->sc_istat = 0; 633 dev->sc_lun = 0x80; /* XXX */ 634 dev->sc_stat[0] = -1; 635 dev->sc_msg[0] = -1; 636 dev->sc_ds.scsi_addr = (0x10000 << target) | (dev->sc_sync[target].period << 8); 637 dev->sc_ds.idlen = 1; 638 dev->sc_ds.idbuf = (char *) dev->sc_lunpa; 639 dev->sc_ds.cmdlen = clen; 640 dev->sc_ds.cmdbuf = (char *) kvtop(cbuf); 641 dev->sc_ds.stslen = 1; 642 dev->sc_ds.stsbuf = (char *) dev->sc_statuspa; 643 dev->sc_ds.msglen = 1; 644 dev->sc_ds.msgbuf = (char *) dev->sc_msgpa; 645 dev->sc_ds.sdtrolen = 0; 646 dev->sc_ds.sdtrilen = 0; 647 dev->sc_ds.chain[0].datalen = len; 648 dev->sc_ds.chain[0].databuf = (char *) kvtop(buf); 649 650 if (dev->sc_sync[target].state == SYNC_START) { 651 if (siop_inhibit_sync[target]) { 652 dev->sc_sync[target].state = SYNC_DONE; 653 dev->sc_sync[target].offset = 0; 654 dev->sc_sync[target].period = 0; 655 #ifdef DEBUG 656 if (siopsync_debug) 657 printf ("Forcing target %d asynchronous\n", target); 658 #endif 659 } 660 else { 661 dev->sc_msg[1] = MSG_IDENTIFY; 662 dev->sc_msg[2] = MSG_EXT_MESSAGE; 663 dev->sc_msg[3] = 3; 664 dev->sc_msg[4] = MSG_SYNC_REQ; 665 dev->sc_msg[5] = siop_sync_period / 4; 666 dev->sc_msg[6] = SIOP_MAX_OFFSET; 667 dev->sc_ds.sdtrolen = 6; 668 dev->sc_ds.sdtrilen = 6; 669 dev->sc_ds.sdtrobuf = dev->sc_ds.sdtribuf = (char *) kvtop(dev->sc_msg + 1); 670 dev->sc_sync[target].state = SYNC_SENT; 671 #ifdef DEBUG 672 if (siopsync_debug) 673 printf ("Sending sync request to target %d\n", target); 674 #endif 675 } 676 } 677 678 /* 679 * If length is > 1 page, check for consecutive physical pages 680 * Need to set up chaining if not 681 */ 682 nchain = 0; 683 count = len; 684 addr = buf; 685 dmaend = NULL; 686 while (count > 0) { 687 dev->sc_ds.chain[nchain].databuf = (char *) kvtop (addr); 688 if (count < (tcount = NBPG - ((int) addr & PGOFSET))) 689 tcount = count; 690 dev->sc_ds.chain[nchain].datalen = tcount; 691 addr += tcount; 692 count -= tcount; 693 if (dev->sc_ds.chain[nchain].databuf == dmaend) { 694 dmaend += dev->sc_ds.chain[nchain].datalen; 695 dev->sc_ds.chain[--nchain].datalen += tcount; 696 #ifdef DEBUG 697 ++siopdma_hits; 698 #endif 699 } 700 else { 701 dmaend = dev->sc_ds.chain[nchain].databuf + 702 dev->sc_ds.chain[nchain].datalen; 703 dev->sc_ds.chain[nchain].datalen = tcount; 704 #ifdef DEBUG 705 ++siopdma_misses; 706 #endif 707 } 708 ++nchain; 709 } 710 #ifdef DEBUG 711 if (nchain != 1 && len != 0 && siop_debug & 3) { 712 printf ("DMA chaining set: %d\n", nchain); 713 for (i = 0; i < nchain; ++i) { 714 printf (" [%d] %8x %4x\n", i, dev->sc_ds.chain[i].databuf, 715 dev->sc_ds.chain[i].datalen); 716 } 717 } 718 #endif 719 720 regs->siop_sbcl = dev->sc_sync[target].offset; 721 if (dev->sc_ds.sdtrolen) 722 regs->siop_scratch = regs->siop_scratch | 0x100; 723 else 724 regs->siop_scratch = regs->siop_scratch & ~0xff00; 725 regs->siop_dsa = dev->sc_dspa; 726 #if 0 727 DCIS(); /* push data cache */ 728 #else 729 dma_cachectl (dev, sizeof (struct siop_softc)); 730 dma_cachectl (cbuf, clen); 731 if (buf != NULL && len != 0) 732 dma_cachectl (buf, len); 733 #endif 734 regs->siop_dsp = dev->sc_scriptspa; 735 } 736 737 /* 738 * Process a DMA or SCSI interrupt from the 53C710 SIOP 739 */ 740 741 int 742 siop_checkintr(dev, istat, dstat, sstat0, status) 743 struct siop_softc *dev; 744 u_char istat; 745 u_char dstat; 746 u_char sstat0; 747 int *status; 748 { 749 siop_regmap_p regs = dev->sc_siopp; 750 int target; 751 752 regs->siop_ctest8 |= 0x04; 753 while ((regs->siop_ctest1 & SIOP_CTEST1_FMT) == 0) 754 ; 755 regs->siop_ctest8 &= ~0x04; 756 #ifdef DEBUG 757 if (siop_debug & 1) { 758 DCIAS(dev->sc_statuspa); /* XXX */ 759 printf ("siopchkintr: istat %x dstat %x sstat0 %x dsps %x sbcl %x sts %x msg %x\n", 760 istat, dstat, sstat0, regs->siop_dsps, regs->siop_sbcl, dev->sc_stat[0], dev->sc_msg[0]); 761 } 762 #endif 763 if (dstat & SIOP_DSTAT_SIR && (regs->siop_dsps == 0xff00 || 764 regs->siop_dsps == 0xfffc)) { 765 /* Normal completion status, or check condition */ 766 if (regs->siop_dsa != dev->sc_dspa) { 767 printf ("siop: invalid dsa: %x %x\n", regs->siop_dsa, 768 dev->sc_dspa); 769 panic("*** siop DSA invalid ***"); 770 } 771 target = dev->sc_slave; 772 if (dev->sc_sync[target].state == SYNC_SENT) { 773 #ifdef DEBUG 774 if (siopsync_debug) 775 printf ("sync msg in: %02x %02x %02x %02x %02x %02x\n", 776 dev->sc_msg[1], dev->sc_msg[2], dev->sc_msg[3], 777 dev->sc_msg[4], dev->sc_msg[5], dev->sc_msg[6]); 778 #endif 779 dev->sc_sync[target].state = SYNC_DONE; 780 dev->sc_sync[target].period = 0; 781 dev->sc_sync[target].offset = 0; 782 if (dev->sc_msg[1] == MSG_EXT_MESSAGE && 783 dev->sc_msg[2] == 3 && 784 dev->sc_msg[3] == MSG_SYNC_REQ && 785 dev->sc_msg[5] != 0) { 786 if (dev->sc_msg[4] && dev->sc_msg[4] < 100 / 4) { 787 #ifdef DEBUG 788 printf ("%d: target %d wanted %dns period\n", 789 dev->sc_dev.dv_xname, target, 790 dev->sc_msg[4] * 4); 791 #endif 792 /* 793 * Kludge for Maxtor XT8580S 794 * It accepts whatever we request, even 795 * though it won't work. So we ask for 796 * a short period than we can handle. If 797 * the device says it can do it, use 208ns. 798 * If the device says it can do less than 799 * 100ns, then we limit it to 100ns. 800 */ 801 if (dev->sc_msg[4] == siop_sync_period / 4) 802 dev->sc_msg[4] = 208 / 4; 803 else 804 dev->sc_msg[4] = 100 / 4; 805 } 806 printf ("%s: target %d now synchronous, period=%dns, offset=%d\n", 807 dev->sc_dev.dv_xname, target, 808 dev->sc_msg[4] * 4, dev->sc_msg[5]); 809 scsi_period_to_siop (dev, target); 810 } 811 } 812 #if 0 813 DCIAS(kvtop(&dev->sc_stat)); /* XXX */ 814 #else 815 dma_cachectl(&dev->sc_stat[0], 1); 816 #endif 817 *status = dev->sc_stat[0]; 818 return 1; 819 } 820 if (sstat0 & SIOP_SSTAT0_M_A) { /* Phase mismatch */ 821 #ifdef DEBUG 822 if (siop_debug & 9) 823 printf ("Phase mismatch: %x dsp +%x\n", regs->siop_sbcl, 824 regs->siop_dsp - dev->sc_scriptspa); 825 if (siop_debug & 0x10) 826 panic ("53c710 phase mismatch"); 827 #endif 828 if ((regs->siop_sbcl & SIOP_REQ) == 0) 829 printf ("Phase mismatch: REQ not asserted! %02x\n", 830 regs->siop_sbcl); 831 switch (regs->siop_sbcl & 7) { 832 /* 833 * For data out and data in phase, check for DMA chaining 834 */ 835 836 /* 837 * for message in, check for possible reject for sync request 838 */ 839 case 0: 840 regs->siop_dsp = dev->sc_scriptspa + Ent_dataout; 841 break; 842 case 1: 843 regs->siop_dsp = dev->sc_scriptspa + Ent_datain; 844 break; 845 case 2: 846 regs->siop_dsp = dev->sc_scriptspa + Ent_cmd; 847 break; 848 case 3: 849 regs->siop_dsp = dev->sc_scriptspa + Ent_status; 850 break; 851 case 6: 852 regs->siop_dsp = dev->sc_scriptspa + Ent_msgout; 853 break; 854 case 7: 855 regs->siop_dsp = dev->sc_scriptspa + Ent_msgin; 856 break; 857 default: 858 goto bad_phase; 859 } 860 return 0; 861 } 862 if (sstat0 & SIOP_SSTAT0_STO) { /* Select timed out */ 863 *status = -1; 864 return 1; 865 } 866 if (dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff05 && 867 (regs->siop_sbcl & (SIOP_MSG | SIOP_CD)) == 0) { 868 printf ("DMA chaining failed\n"); 869 siopreset (dev); 870 *status = -1; 871 return 1; 872 } 873 if (dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff27) { 874 #ifdef DEBUG 875 if (siop_debug & 3) 876 printf ("DMA chaining completed: dsa %x dnad %x addr %x\n", 877 regs->siop_dsa, regs->siop_dnad, regs->siop_addr); 878 #endif 879 regs->siop_dsa = dev->sc_dspa; 880 regs->siop_dsp = dev->sc_scriptspa + Ent_status; 881 return 0; 882 } 883 target = dev->sc_slave; 884 if (dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff26 && 885 dev->sc_msg[0] == MSG_REJECT && dev->sc_sync[target].state == SYNC_SENT) { 886 dev->sc_sync[target].state = SYNC_DONE; 887 dev->sc_sync[target].period = 0; 888 dev->sc_sync[target].offset = 0; 889 dev->sc_ds.sdtrolen = 0; 890 dev->sc_ds.sdtrilen = 0; 891 #ifdef DEBUG 892 if (siopsync_debug || 1) 893 printf ("target %d rejected sync, going asynchronous\n", target); 894 #endif 895 siop_inhibit_sync[target] = -1; 896 if ((regs->siop_sbcl & 7) == 6) { 897 regs->siop_dsp = dev->sc_scriptspa + Ent_msgout; 898 return (0); 899 } 900 } 901 if ((dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff13) || 902 sstat0 & SIOP_SSTAT0_UDC) { 903 #ifdef DEBUG 904 printf ("%s: target %d disconnected unexpectedly\n", 905 dev->sc_dev.dv_xname, target); 906 #endif 907 #if 0 908 siopabort (dev, regs, "siopchkintr"); 909 #endif 910 *status = STS_BUSY; 911 return 1; 912 } 913 if (dstat & SIOP_DSTAT_SIR &®s->siop_dsps == 0xfffb) { 914 #if 0 915 printf ("%s: target %d busy\n", dev->sc_dev.dv_xname, target); 916 #endif 917 #if 0 918 siopabort (dev, regs, "siopchkintr"); 919 #endif 920 *status = STS_BUSY; 921 return 1; 922 } 923 if (sstat0 == 0 && dstat & SIOP_DSTAT_SIR) { 924 #if 0 925 DCIAS(dev->sc_statuspa); 926 #else 927 dma_cachectl (&dev->sc_stat[0], 1); 928 #endif 929 printf ("SIOP interrupt: %x sts %x msg %x sbcl %x\n", 930 regs->siop_dsps, dev->sc_stat[0], dev->sc_msg[0], 931 regs->siop_sbcl); 932 siopreset (dev); 933 *status = -1; 934 return 1; 935 } 936 bad_phase: 937 /* 938 * temporary panic for unhandled conditions 939 * displays various things about the 53C710 status and registers 940 * then panics 941 */ 942 printf ("siopchkintr: target %x ds %x\n", target, &dev->sc_ds); 943 printf ("scripts %x ds %x regs %x dsp %x dcmd %x\n", dev->sc_scriptspa, 944 dev->sc_dspa, kvtop(regs), regs->siop_dsp, *((long *)®s->siop_dcmd)); 945 printf ("siopchkintr: istat %x dstat %x sstat0 %x dsps %x dsa %x sbcl %x sts %x msg %x\n", 946 istat, dstat, sstat0, regs->siop_dsps, regs->siop_dsa, regs->siop_sbcl, 947 dev->sc_stat[0], dev->sc_msg[0]); 948 panic("siopchkintr: **** temp ****"); 949 } 950 951 /* 952 * SCSI 'immediate' command: issue a command to some SCSI device 953 * and get back an 'immediate' response (i.e., do programmed xfer 954 * to get the response data). 'cbuf' is a buffer containing a scsi 955 * command of length clen bytes. 'buf' is a buffer of length 'len' 956 * bytes for data. The transfer direction is determined by the device 957 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 958 * command must supply no data. 'xferphase' is the bus phase the 959 * caller expects to happen after the command is issued. It should 960 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 961 * 962 * XXX - 53C710 will use DMA, but no interrupts (it's a heck of a 963 * lot easier to do than to use programmed I/O). 964 * 965 */ 966 int 967 siopicmd(dev, target, cbuf, clen, buf, len) 968 struct siop_softc *dev; 969 int target; 970 void *cbuf; 971 int clen; 972 void *buf; 973 int len; 974 { 975 siop_regmap_p regs = dev->sc_siopp; 976 int i; 977 int status; 978 u_char istat; 979 u_char dstat; 980 u_char sstat0; 981 982 if (dev->sc_flags & SIOP_SELECTED) { 983 printf ("siopicmd%d: bus busy\n", target); 984 return -1; 985 } 986 regs->siop_sien = 0x00; /* disable SCSI and DMA interrupts */ 987 regs->siop_dien = 0x00; 988 dev->sc_flags |= SIOP_SELECTED; 989 dev->sc_slave = target; 990 #ifdef DEBUG 991 if (siop_debug & 1) 992 printf ("siopicmd: target %x cmd %02x ds %x\n", target, 993 *((char *)cbuf), &dev->sc_ds); 994 #endif 995 siop_setup (dev, target, cbuf, clen, buf, len); 996 997 for (;;) { 998 /* use cmd_wait values? */ 999 i = siop_cmd_wait << 1; 1000 while (((istat = regs->siop_istat) & 1001 (SIOP_ISTAT_SIP | SIOP_ISTAT_DIP)) == 0) { 1002 if (--i <= 0) { 1003 printf ("waiting: tgt %d cmd %02x sbcl %02x dsp %x (+%x) dcmd %x ds %x\n", 1004 target, *((char *)cbuf), 1005 regs->siop_dsp - dev->sc_scriptspa, 1006 regs->siop_sbcl, regs->siop_dsp, 1007 regs->siop_dsp - kvtop(scripts), 1008 *((long *)®s->siop_dcmd), &dev->sc_ds); 1009 i = siop_cmd_wait << 2; 1010 /* XXXX need an upper limit and reset */ 1011 } 1012 delay(1); 1013 } 1014 dstat = regs->siop_dstat; 1015 sstat0 = regs->siop_sstat0; 1016 #ifdef DEBUG 1017 if (siop_debug & 1) { 1018 DCIAS(dev->sc_statuspa); /* XXX should just invalidate dev->sc_stat */ 1019 printf ("siopicmd: istat %x dstat %x sstat0 %x dsps %x sbcl %x sts %x msg %x\n", 1020 istat, dstat, sstat0, regs->siop_dsps, regs->siop_sbcl, 1021 dev->sc_stat[0], dev->sc_msg[0]); 1022 } 1023 #endif 1024 if (siop_checkintr(dev, istat, dstat, sstat0, &status)) { 1025 dev->sc_flags &= ~SIOP_SELECTED; 1026 return (status); 1027 } 1028 } 1029 } 1030 1031 int 1032 siopgo(dev, xs) 1033 struct siop_softc *dev; 1034 struct scsi_xfer *xs; 1035 { 1036 siop_regmap_p regs; 1037 int i; 1038 int nchain; 1039 int count, tcount; 1040 char *addr, *dmaend; 1041 1042 #ifdef DEBUG 1043 if (siop_debug & 1) 1044 printf ("%s: go ", dev->sc_dev.dv_xname); 1045 #if 0 1046 if ((cdb->cdb[1] & 1) == 0 && 1047 ((cdb->cdb[0] == CMD_WRITE && cdb->cdb[2] == 0 && cdb->cdb[3] == 0) || 1048 (cdb->cdb[0] == CMD_WRITE_EXT && cdb->cdb[2] == 0 && cdb->cdb[3] == 0 1049 && cdb->cdb[4] == 0))) 1050 panic ("siopgo: attempted write to block < 0x100"); 1051 #endif 1052 #endif 1053 #if 0 1054 cdb->cdb[1] |= unit << 5; 1055 #endif 1056 1057 if (dev->sc_flags & SIOP_SELECTED) { 1058 printf ("%s: bus busy\n", dev->sc_dev.dv_xname); 1059 return 1; 1060 } 1061 1062 dev->sc_flags |= SIOP_SELECTED | SIOP_DMA; 1063 dev->sc_slave = xs->sc_link->target; 1064 regs = dev->sc_siopp; 1065 /* enable SCSI and DMA interrupts */ 1066 regs->siop_sien = SIOP_SIEN_M_A | SIOP_SIEN_STO | SIOP_SIEN_SEL | SIOP_SIEN_SGE | 1067 SIOP_SIEN_UDC | SIOP_SIEN_RST | SIOP_SIEN_PAR; 1068 regs->siop_dien = 0x20 | SIOP_DIEN_ABRT | SIOP_DIEN_SIR | SIOP_DIEN_WTD | 1069 SIOP_DIEN_OPC; 1070 #ifdef DEBUG 1071 if (siop_debug & 1) 1072 printf ("siopgo: target %x cmd %02x ds %x\n", dev->sc_slave, xs->cmd->opcode, &dev->sc_ds); 1073 #endif 1074 1075 siop_setup(dev, dev->sc_slave, xs->cmd, xs->cmdlen, xs->data, xs->datalen); 1076 1077 return (0); 1078 } 1079 1080 /* 1081 * Check for 53C710 interrupts 1082 */ 1083 1084 int 1085 siopintr (dev) 1086 register struct siop_softc *dev; 1087 { 1088 siop_regmap_p regs; 1089 register u_char istat, dstat, sstat0; 1090 int unit; 1091 int status; 1092 int found = 0; 1093 1094 regs = dev->sc_siopp; 1095 istat = dev->sc_istat; 1096 if ((istat & (SIOP_ISTAT_SIP | SIOP_ISTAT_DIP)) == 0) 1097 return; 1098 if ((dev->sc_flags & (SIOP_DMA | SIOP_SELECTED)) == SIOP_SELECTED) 1099 return; /* doing non-interrupt I/O */ 1100 /* Got a valid interrupt on this device */ 1101 dstat = dev->sc_dstat; 1102 sstat0 = dev->sc_sstat0; 1103 dev->sc_istat = 0; 1104 #ifdef DEBUG 1105 if (siop_debug & 1) 1106 printf ("%s: intr istat %x dstat %x sstat0 %x\n", 1107 dev->sc_dev.dv_xname, istat, dstat, sstat0); 1108 if ((dev->sc_flags & SIOP_DMA) == 0) { 1109 printf ("%s: spurious interrupt? istat %x dstat %x sstat0 %x\n", 1110 dev->sc_dev.dv_xname, istat, dstat, sstat0); 1111 } 1112 #endif 1113 1114 #ifdef DEBUG 1115 if (siop_debug & 5) { 1116 DCIAS(dev->sc_statuspa); 1117 printf ("siopintr%d: istat %x dstat %x sstat0 %x dsps %x sbcl %x sts %x msg %x\n", 1118 unit, istat, dstat, sstat0, regs->siop_dsps, 1119 regs->siop_sbcl, dev->sc_stat[0], dev->sc_msg[0]); 1120 } 1121 #endif 1122 if (siop_checkintr (dev, istat, dstat, sstat0, &status)) { 1123 #if 1 1124 regs->siop_sien = 0; 1125 regs->siop_dien = 0; 1126 if (status == 0xff) 1127 printf ("siopintr: status == 0xff\n"); 1128 #endif 1129 dev->sc_flags &= ~(SIOP_DMA | SIOP_SELECTED); 1130 siop_scsidone(dev, dev->sc_stat[0]); 1131 } 1132 } 1133 1134 scsi_period_to_siop (dev, target) 1135 struct siop_softc *dev; 1136 { 1137 int period, offset, i, sxfer; 1138 1139 period = dev->sc_msg[4]; 1140 offset = dev->sc_msg[5]; 1141 sxfer = 0; 1142 if (offset <= SIOP_MAX_OFFSET) 1143 sxfer = offset; 1144 for (i = 0; i < sizeof (xxx) / 2; ++i) { 1145 if (period <= xxx[i].x) { 1146 sxfer |= xxx[i].y & 0x70; 1147 offset = xxx[i].y & 0x03; 1148 break; 1149 } 1150 } 1151 dev->sc_sync[target].period = sxfer; 1152 dev->sc_sync[target].offset = offset; 1153 #ifdef DEBUG 1154 printf ("sync: siop_sxfr %02x, siop_sbcl %02x\n", sxfer, offset); 1155 #endif 1156 } 1157
Indexes created Tue Sep 23 01:09:51 GMT 2025