siop.c revision 1.14
1 /* 2 * Copyright (c) 1994 Michael L. Hitch 3 * Copyright (c) 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * Van Jacobson of Lawrence Berkeley Laboratory. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by the University of 20 * California, Berkeley and its contributors. 21 * 4. Neither the name of the University nor the names of its contributors 22 * may be used to endorse or promote products derived from this software 23 * without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 35 * SUCH DAMAGE. 36 * 37 * @(#)siop.c 7.5 (Berkeley) 5/4/91 38 * $Id: siop.c,v 1.14 1994/06/22 16:20:53 chopps Exp $ 39 */ 40 41 /* 42 * AMIGA 53C710 scsi adaptor driver 43 */ 44 45 /* need to know if any tapes have been configured */ 46 #include "st.h" 47 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/device.h> 51 #include <sys/buf.h> 52 #include <scsi/scsi_all.h> 53 #include <scsi/scsiconf.h> 54 #include <machine/cpu.h> 55 #include <amiga/amiga/custom.h> 56 #include <amiga/dev/siopreg.h> 57 #include <amiga/dev/siopvar.h> 58 59 extern u_int kvtop(); 60 61 /* 62 * SCSI delays 63 * In u-seconds, primarily for state changes on the SPC. 64 */ 65 #define SCSI_CMD_WAIT 500000 /* wait per step of 'immediate' cmds */ 66 #define SCSI_DATA_WAIT 500000 /* wait per data in/out step */ 67 #define SCSI_INIT_WAIT 500000 /* wait per step (both) during init */ 68 69 int siopicmd __P((struct siop_softc *, int, void *, int, void *, int)); 70 int siopgo __P((struct siop_softc *, struct scsi_xfer *)); 71 int siopgetsense __P((struct siop_softc *, struct scsi_xfer *)); 72 void siopabort __P((struct siop_softc *, siop_regmap_p, char *)); 73 void sioperror __P((struct siop_softc *, siop_regmap_p, u_char)); 74 void siopstart __P((struct siop_softc *)); 75 void siopreset __P((struct siop_softc *)); 76 void siopsetdelay __P((int)); 77 void siop_scsidone __P((struct siop_softc *, int)); 78 void siop_donextcmd __P((struct siop_softc *)); 79 int siopintr __P((struct siop_softc *)); 80 81 /* 53C710 script */ 82 unsigned long scripts[] = { 83 0x47000000, 0x000002d0, /* 000 - 0 */ 84 0x838b0000, 0x000000d0, /* 008 - 8 */ 85 0x7a1b1000, 0x00000000, /* 010 - 16 */ 86 0x828a0000, 0x00000088, /* 018 - 24 */ 87 0x9e020000, 0x0000ff01, /* 020 - 32 */ 88 0x72350000, 0x00000000, /* 028 - 40 */ 89 0x808c0000, 0x00000048, /* 030 - 48 */ 90 0x58000008, 0x00000000, /* 038 - 56 */ 91 0x1e000024, 0x00000024, /* 040 - 64 */ 92 0x838b0000, 0x00000090, /* 048 - 72 */ 93 0x1f00002c, 0x0000002c, /* 050 - 80 */ 94 0x838b0000, 0x00000080, /* 058 - 88 */ 95 0x868a0000, 0xffffffd0, /* 060 - 96 */ 96 0x838a0000, 0x00000070, /* 068 - 104 */ 97 0x878a0000, 0x00000158, /* 070 - 112 */ 98 0x80880000, 0x00000028, /* 078 - 120 */ 99 0x1e000004, 0x00000004, /* 080 - 128 */ 100 0x838b0000, 0x00000050, /* 088 - 136 */ 101 0x868a0000, 0xffffffe8, /* 090 - 144 */ 102 0x838a0000, 0x00000040, /* 098 - 152 */ 103 0x878a0000, 0x00000128, /* 0a0 - 160 */ 104 0x9a020000, 0x0000ff02, /* 0a8 - 168 */ 105 0x1a00000c, 0x0000000c, /* 0b0 - 176 */ 106 0x878b0000, 0x00000168, /* 0b8 - 184 */ 107 0x838a0000, 0x00000018, /* 0c0 - 192 */ 108 0x818a0000, 0x000000e8, /* 0c8 - 200 */ 109 0x808a0000, 0x000000b8, /* 0d0 - 208 */ 110 0x98080000, 0x0000ff03, /* 0d8 - 216 */ 111 0x1b000014, 0x00000014, /* 0e0 - 224 */ 112 0x72090000, 0x00000000, /* 0e8 - 232 */ 113 0x6a340000, 0x00000000, /* 0f0 - 240 */ 114 0x9f030000, 0x0000ff04, /* 0f8 - 248 */ 115 0x1f00001c, 0x0000001c, /* 100 - 256 */ 116 0x808c0007, 0x00000050, /* 108 - 264 */ 117 0x98040000, 0x0000ff26, /* 110 - 272 */ 118 0x60000040, 0x00000000, /* 118 - 280 */ 119 0x48000000, 0x00000000, /* 120 - 288 */ 120 0x7c1bef00, 0x00000000, /* 128 - 296 */ 121 0x72340000, 0x00000000, /* 130 - 304 */ 122 0x980c0002, 0x0000fffc, /* 138 - 312 */ 123 0x980c0008, 0x0000fffb, /* 140 - 320 */ 124 0x980c0018, 0x0000fffd, /* 148 - 328 */ 125 0x98040000, 0x0000fffe, /* 150 - 336 */ 126 0x98080000, 0x0000ff00, /* 158 - 344 */ 127 0x60000008, 0x00000000, /* 160 - 352 */ 128 0x98080000, 0x0000ff26, /* 168 - 360 */ 129 0x60000040, 0x00000000, /* 170 - 368 */ 130 0x828b0000, 0xffffff28, /* 178 - 376 */ 131 0x838b0000, 0xffffff58, /* 180 - 384 */ 132 0x878b0000, 0xffffff68, /* 188 - 392 */ 133 0x18000034, 0x00000034, /* 190 - 400 */ 134 0x808b0000, 0x000001c0, /* 198 - 408 */ 135 0x838b0000, 0xffffff38, /* 1a0 - 416 */ 136 0x878a0000, 0x000000d0, /* 1a8 - 424 */ 137 0x98080000, 0x0000ff05, /* 1b0 - 432 */ 138 0x19000034, 0x00000034, /* 1b8 - 440 */ 139 0x818b0000, 0x00000160, /* 1c0 - 448 */ 140 0x80880000, 0xffffffd0, /* 1c8 - 456 */ 141 0x1f00001c, 0x0000001c, /* 1d0 - 464 */ 142 0x808c0001, 0x00000018, /* 1d8 - 472 */ 143 0x980c0002, 0x0000ff08, /* 1e0 - 480 */ 144 0x808c0004, 0x00000020, /* 1e8 - 488 */ 145 0x98080000, 0x0000ff06, /* 1f0 - 496 */ 146 0x60000040, 0x00000000, /* 1f8 - 504 */ 147 0x1f00002c, 0x0000002c, /* 200 - 512 */ 148 0x98080000, 0x0000ff07, /* 208 - 520 */ 149 0x60000040, 0x00000000, /* 210 - 528 */ 150 0x48000000, 0x00000000, /* 218 - 536 */ 151 0x98080000, 0x0000ff09, /* 220 - 544 */ 152 0x1f00001c, 0x0000001c, /* 228 - 552 */ 153 0x808c0001, 0x00000018, /* 230 - 560 */ 154 0x980c0002, 0x0000ff10, /* 238 - 568 */ 155 0x808c0004, 0x00000020, /* 240 - 576 */ 156 0x98080000, 0x0000ff11, /* 248 - 584 */ 157 0x60000040, 0x00000000, /* 250 - 592 */ 158 0x1f00002c, 0x0000002c, /* 258 - 600 */ 159 0x98080000, 0x0000ff12, /* 260 - 608 */ 160 0x60000040, 0x00000000, /* 268 - 616 */ 161 0x48000000, 0x00000000, /* 270 - 624 */ 162 0x98080000, 0x0000ff13, /* 278 - 632 */ 163 0x1f00001c, 0x0000001c, /* 280 - 640 */ 164 0x808c0001, 0x00000018, /* 288 - 648 */ 165 0x980c0002, 0x0000ff14, /* 290 - 656 */ 166 0x808c0004, 0x00000020, /* 298 - 664 */ 167 0x98080000, 0x0000ff15, /* 2a0 - 672 */ 168 0x60000040, 0x00000000, /* 2a8 - 680 */ 169 0x1f00002c, 0x0000002c, /* 2b0 - 688 */ 170 0x98080000, 0x0000ff16, /* 2b8 - 696 */ 171 0x60000040, 0x00000000, /* 2c0 - 704 */ 172 0x48000000, 0x00000000, /* 2c8 - 712 */ 173 0x98080000, 0x0000ff17, /* 2d0 - 720 */ 174 0x54000000, 0x00000040, /* 2d8 - 728 */ 175 0x9f030000, 0x0000ff18, /* 2e0 - 736 */ 176 0x1f00001c, 0x0000001c, /* 2e8 - 744 */ 177 0x990b0000, 0x0000ff19, /* 2f0 - 752 */ 178 0x980a0000, 0x0000ff20, /* 2f8 - 760 */ 179 0x9f0a0000, 0x0000ff21, /* 300 - 768 */ 180 0x9b0a0000, 0x0000ff22, /* 308 - 776 */ 181 0x9e0a0000, 0x0000ff23, /* 310 - 784 */ 182 0x98080000, 0x0000ff24, /* 318 - 792 */ 183 0x98080000, 0x0000ff25, /* 320 - 800 */ 184 0x76100800, 0x00000000, /* 328 - 808 */ 185 0x80840700, 0x00000008, /* 330 - 816 */ 186 0x7e110100, 0x00000000, /* 338 - 824 */ 187 0x6a100000, 0x00000000, /* 340 - 832 */ 188 0x19000034, 0x00000034, /* 348 - 840 */ 189 0x818b0000, 0xffffffd0, /* 350 - 848 */ 190 0x98080000, 0x0000ff27, /* 358 - 856 */ 191 0x76100800, 0x00000000, /* 360 - 864 */ 192 0x80840700, 0x00000008, /* 368 - 872 */ 193 0x7e110100, 0x00000000, /* 370 - 880 */ 194 0x6a100000, 0x00000000, /* 378 - 888 */ 195 0x18000034, 0x00000034, /* 380 - 896 */ 196 0x808b0000, 0xffffffd0, /* 388 - 904 */ 197 0x98080000, 0x0000ff27 /* 390 - 912 */ 198 }; 199 200 #define Ent_msgout 0x00000018 201 #define Ent_cmd 0x000000a8 202 #define Ent_status 0x000000e0 203 #define Ent_msgin 0x000000f8 204 #define Ent_dataout 0x00000190 205 #define Ent_datain 0x000001b8 206 207 /* default to not inhibit sync negotiation on any drive */ 208 /* XXXX - unit 2 inhibits sync for my WangTek tape drive - mlh */ 209 u_char siop_inhibit_sync[8] = { 0, 0, 0, 0, 0, 0, 0 }; /* initialize, so patchable */ 210 int siop_no_dma = 0; 211 212 int siop_reset_delay = 2000; /* delay after reset, in milleseconds */ 213 int siop_sync_period = 50; /* synchronous transfer period, in nanoseconds */ 214 215 int siop_cmd_wait = SCSI_CMD_WAIT; 216 int siop_data_wait = SCSI_DATA_WAIT; 217 int siop_init_wait = SCSI_INIT_WAIT; 218 219 static struct { 220 unsigned char x; /* period from sync request message */ 221 unsigned char y; /* siop_period << 4 | sbcl */ 222 } xxx[] = { 223 {0x0f, 0x01}, 224 {0x13, 0x11}, 225 {0x17, 0x21}, 226 /* {0x17, 0x02}, */ 227 {0x1b, 0x31}, 228 {0x1d, 0x12}, 229 {0x1e, 0x41}, 230 /* {0x1e, 0x03}, */ 231 {0x22, 0x51}, 232 {0x23, 0x22}, 233 {0x26, 0x61}, 234 /* {0x26, 0x13}, */ 235 {0x29, 0x32}, 236 {0x2a, 0x71}, 237 {0x2d, 0x23}, 238 {0x2e, 0x42}, 239 {0x34, 0x52}, 240 {0x35, 0x33}, 241 {0x3a, 0x62}, 242 {0x3c, 0x43}, 243 {0x40, 0x72}, 244 {0x44, 0x53}, 245 {0x4b, 0x63}, 246 {0x53, 0x73} 247 }; 248 249 #ifdef DEBUG 250 #define QPRINTF(a) if (siop_debug > 1) printf a 251 /* 252 * 0x01 - full debug 253 * 0x02 - DMA chaining 254 * 0x04 - siopintr 255 * 0x08 - phase mismatch 256 * 0x10 - panic on phase mismatch 257 */ 258 int siop_debug = 0; 259 int siopsync_debug = 0; 260 int siopdma_hits = 0; 261 int siopdma_misses = 0; 262 int siopchain_ints = 0; 263 #endif 264 265 266 /* 267 * default minphys routine for siop based controllers 268 */ 269 void 270 siop_minphys(bp) 271 struct buf *bp; 272 { 273 /* 274 * no max transfer at this level 275 */ 276 } 277 278 /* 279 * must be used 280 */ 281 u_int 282 siop_adinfo() 283 { 284 /* 285 * one request at a time please 286 */ 287 return(1); 288 } 289 290 /* 291 * used by specific siop controller 292 * 293 * it appears that the higher level code does nothing with LUN's 294 * so I will too. I could plug it in, however so could they 295 * in scsi_scsi_cmd(). 296 */ 297 int 298 siop_scsicmd(xs) 299 struct scsi_xfer *xs; 300 { 301 struct siop_pending *pendp; 302 struct siop_softc *dev; 303 struct scsi_link *slp; 304 int flags, s; 305 306 slp = xs->sc_link; 307 dev = slp->adapter_softc; 308 flags = xs->flags; 309 310 if (flags & SCSI_DATA_UIO) 311 panic("siop: scsi data uio requested"); 312 313 if (dev->sc_xs && flags & SCSI_NOMASK) 314 panic("siop_scsicmd: busy"); 315 316 s = splbio(); 317 pendp = &dev->sc_xsstore[slp->target][slp->lun]; 318 if (pendp->xs) { 319 splx(s); 320 return(TRY_AGAIN_LATER); 321 } 322 323 if (dev->sc_xs) { 324 pendp->xs = xs; 325 TAILQ_INSERT_TAIL(&dev->sc_xslist, pendp, link); 326 splx(s); 327 return(SUCCESSFULLY_QUEUED); 328 } 329 pendp->xs = NULL; 330 dev->sc_xs = xs; 331 splx(s); 332 333 /* 334 * nothing is pending do it now. 335 */ 336 siop_donextcmd(dev); 337 338 if (flags & SCSI_NOMASK) 339 return(COMPLETE); 340 return(SUCCESSFULLY_QUEUED); 341 } 342 343 /* 344 * entered with dev->sc_xs pointing to the next xfer to perform 345 */ 346 void 347 siop_donextcmd(dev) 348 struct siop_softc *dev; 349 { 350 struct scsi_xfer *xs; 351 struct scsi_link *slp; 352 int flags, phase, stat; 353 354 xs = dev->sc_xs; 355 slp = xs->sc_link; 356 flags = xs->flags; 357 358 #if 0 359 if (flags & SCSI_DATA_IN) 360 phase = DATA_IN_PHASE; 361 else if (flags & SCSI_DATA_OUT) 362 phase = DATA_OUT_PHASE; 363 else 364 phase = STATUS_PHASE; 365 #endif 366 367 if (flags & SCSI_RESET) 368 siopreset(dev); 369 370 dev->sc_stat[0] = -1; 371 #if 0 372 if (phase == STATUS_PHASE || flags & SCSI_NOMASK) 373 #else 374 if (flags & SCSI_NOMASK || siop_no_dma) 375 #endif 376 stat = siopicmd(dev, slp->target, xs->cmd, xs->cmdlen, 377 xs->data, xs->datalen/*, phase*/); 378 else if (siopgo(dev, xs) == 0) 379 return; 380 else 381 stat = dev->sc_stat[0]; 382 383 siop_scsidone(dev, stat); 384 } 385 386 void 387 siop_scsidone(dev, stat) 388 struct siop_softc *dev; 389 int stat; 390 { 391 struct siop_pending *pendp; 392 struct scsi_xfer *xs; 393 int s, donext; 394 395 xs = dev->sc_xs; 396 #ifdef DIAGNOSTIC 397 if (xs == NULL) 398 panic("siop_scsidone"); 399 #endif 400 /* 401 * is this right? 402 */ 403 xs->status = stat; 404 405 if (stat == 0 || xs->flags & SCSI_ERR_OK) 406 xs->resid = 0; 407 else { 408 switch(stat) { 409 case SCSI_CHECK: 410 if (stat = siopgetsense(dev, xs)) 411 goto bad_sense; 412 xs->error = XS_SENSE; 413 break; 414 case SCSI_BUSY: 415 xs->error = XS_BUSY; 416 break; 417 bad_sense: 418 default: 419 xs->error = XS_DRIVER_STUFFUP; 420 QPRINTF(("siop_scsicmd() bad %x\n", stat)); 421 break; 422 } 423 } 424 xs->flags |= ITSDONE; 425 426 /* 427 * grab next command before scsi_done() 428 * this way no single device can hog scsi resources. 429 */ 430 s = splbio(); 431 pendp = dev->sc_xslist.tqh_first; 432 if (pendp == NULL) { 433 donext = 0; 434 dev->sc_xs = NULL; 435 } else { 436 donext = 1; 437 TAILQ_REMOVE(&dev->sc_xslist, pendp, link); 438 dev->sc_xs = pendp->xs; 439 pendp->xs = NULL; 440 } 441 splx(s); 442 scsi_done(xs); 443 444 if (donext) 445 siop_donextcmd(dev); 446 } 447 448 int 449 siopgetsense(dev, xs) 450 struct siop_softc *dev; 451 struct scsi_xfer *xs; 452 { 453 struct scsi_sense rqs; 454 struct scsi_link *slp; 455 int stat; 456 457 slp = xs->sc_link; 458 459 rqs.op_code = REQUEST_SENSE; 460 rqs.byte2 = slp->lun << 5; 461 #ifdef not_yet 462 rqs.length = xs->req_sense_length ? xs->req_sense_length : 463 sizeof(xs->sense); 464 #else 465 rqs.length = sizeof(xs->sense); 466 #endif 467 if (rqs.length > sizeof (xs->sense)) 468 rqs.length = sizeof (xs->sense); 469 rqs.unused[0] = rqs.unused[1] = rqs.control = 0; 470 471 return(siopicmd(dev, slp->target, &rqs, sizeof(rqs), &xs->sense, 472 rqs.length)); 473 } 474 475 void 476 siopabort(dev, regs, where) 477 register struct siop_softc *dev; 478 siop_regmap_p regs; 479 char *where; 480 { 481 482 printf ("%s: abort %s: dstat %02x, sstat0 %02x sbcl %02x\n", 483 dev->sc_dev.dv_xname, 484 where, regs->siop_dstat, regs->siop_sstat0, regs->siop_sbcl); 485 486 if (dev->sc_flags & SIOP_SELECTED) { 487 #ifdef TODO 488 SET_SBIC_cmd (regs, SBIC_CMD_ABORT); 489 WAIT_CIP (regs); 490 491 GET_SBIC_asr (regs, asr); 492 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) 493 { 494 /* ok, get more drastic.. */ 495 496 SET_SBIC_cmd (regs, SBIC_CMD_RESET); 497 delay(25); 498 SBIC_WAIT(regs, SBIC_ASR_INT, 0); 499 GET_SBIC_csr (regs, csr); /* clears interrupt also */ 500 501 dev->sc_flags &= ~SIOP_SELECTED; 502 return; 503 } 504 505 do 506 { 507 SBIC_WAIT (regs, SBIC_ASR_INT, 0); 508 GET_SBIC_csr (regs, csr); 509 } 510 while ((csr != SBIC_CSR_DISC) && (csr != SBIC_CSR_DISC_1) 511 && (csr != SBIC_CSR_CMD_INVALID)); 512 #endif 513 514 /* lets just hope it worked.. */ 515 dev->sc_flags &= ~SIOP_SELECTED; 516 } 517 } 518 519 /* 520 * XXX Set/reset long delays. 521 * 522 * if delay == 0, reset default delays 523 * if delay < 0, set both delays to default long initialization values 524 * if delay > 0, set both delays to this value 525 * 526 * Used when a devices is expected to respond slowly (e.g. during 527 * initialization). 528 */ 529 void 530 siop_delay(delay) 531 int delay; 532 { 533 static int saved_cmd_wait, saved_data_wait; 534 535 if (delay) { 536 saved_cmd_wait = siop_cmd_wait; 537 saved_data_wait = siop_data_wait; 538 if (delay > 0) 539 siop_cmd_wait = siop_data_wait = delay; 540 else 541 siop_cmd_wait = siop_data_wait = siop_init_wait; 542 } else { 543 siop_cmd_wait = saved_cmd_wait; 544 siop_data_wait = saved_data_wait; 545 } 546 } 547 548 void 549 siopinitialize(dev) 550 struct siop_softc *dev; 551 { 552 /* 553 * Need to check that scripts is on a long word boundary 554 * and that DS is on a long word boundary. 555 * Also need to verify that dev doesn't non-contiguous 556 * physical pages. 557 */ 558 dev->sc_scriptspa = kvtop(scripts); 559 dev->sc_dspa = kvtop(&dev->sc_ds); 560 dev->sc_lunpa = kvtop(&dev->sc_lun); 561 dev->sc_statuspa = kvtop(&dev->sc_stat[0]); 562 dev->sc_msgpa = kvtop(&dev->sc_msg[0]); 563 siopreset (dev); 564 } 565 566 void 567 siopreset(dev) 568 struct siop_softc *dev; 569 { 570 siop_regmap_p regs; 571 u_int i, s; 572 u_char my_id, csr; 573 574 regs = dev->sc_siopp; 575 576 if (dev->sc_flags & SIOP_ALIVE) 577 siopabort(dev, regs, "reset"); 578 579 printf("%s: ", dev->sc_dev.dv_xname); /* XXXX */ 580 581 s = splbio(); 582 my_id = 7; 583 584 /* 585 * Reset the chip 586 * XXX - is this really needed? 587 */ 588 regs->siop_sien &= ~SIOP_SIEN_RST; 589 regs->siop_scntl1 |= SIOP_SCNTL1_RST; 590 for (i = 0; i < 1000; ++i) 591 ; 592 regs->siop_scntl1 &= ~SIOP_SCNTL1_RST; 593 regs->siop_sien |= SIOP_SIEN_RST; 594 595 /* 596 * Set up various chip parameters 597 */ 598 regs->siop_istat = 0x40; 599 for (i = 0; i < 1000; ++i) 600 ; 601 regs->siop_istat = 0x00; 602 regs->siop_scntl0 = SIOP_ARB_FULL | SIOP_SCNTL0_EPC | SIOP_SCNTL0_EPG; 603 regs->siop_dcntl = dev->sc_clock_freq & 0xff; 604 regs->siop_dmode = 0x80; /* burst length = 4 */ 605 regs->siop_sien = 0x00; /* don't enable interrupts yet */ 606 regs->siop_dien = 0x00; /* don't enable interrupts yet */ 607 regs->siop_scid = 1 << my_id; 608 regs->siop_dwt = 0x00; 609 regs->siop_ctest0 |= 0x20; /* Enable Active Negation ?? */ 610 regs->siop_ctest7 |= (dev->sc_clock_freq >> 8) & 0xff; 611 612 /* will need to re-negotiate sync xfers */ 613 bzero(&dev->sc_sync, sizeof (dev->sc_sync)); 614 615 splx (s); 616 617 delay (siop_reset_delay * 1000); 618 printf("siop id %d reset\n", my_id); 619 dev->sc_flags |= SIOP_ALIVE; 620 dev->sc_flags &= ~(SIOP_SELECTED | SIOP_DMA); 621 } 622 623 /* 624 * Setup Data Storage for 53C710 and start SCRIPTS processing 625 */ 626 627 void 628 siop_setup (dev, target, cbuf, clen, buf, len) 629 struct siop_softc *dev; 630 int target; 631 u_char *cbuf; 632 int clen; 633 u_char *buf; 634 int len; 635 { 636 siop_regmap_p regs = dev->sc_siopp; 637 int i; 638 int nchain; 639 int count, tcount; 640 char *addr, *dmaend; 641 642 dev->sc_istat = 0; 643 dev->sc_lun = 0x80; /* XXX */ 644 dev->sc_stat[0] = -1; 645 dev->sc_msg[0] = -1; 646 dev->sc_ds.scsi_addr = (0x10000 << target) | (dev->sc_sync[target].period << 8); 647 dev->sc_ds.idlen = 1; 648 dev->sc_ds.idbuf = (char *) dev->sc_lunpa; 649 dev->sc_ds.cmdlen = clen; 650 dev->sc_ds.cmdbuf = (char *) kvtop(cbuf); 651 dev->sc_ds.stslen = 1; 652 dev->sc_ds.stsbuf = (char *) dev->sc_statuspa; 653 dev->sc_ds.msglen = 1; 654 dev->sc_ds.msgbuf = (char *) dev->sc_msgpa; 655 dev->sc_ds.sdtrolen = 0; 656 dev->sc_ds.sdtrilen = 0; 657 bzero(&dev->sc_ds.chain, sizeof (dev->sc_ds.chain)); 658 659 if (dev->sc_sync[target].state == SYNC_START) { 660 if (siop_inhibit_sync[target]) { 661 dev->sc_sync[target].state = SYNC_DONE; 662 dev->sc_sync[target].offset = 0; 663 dev->sc_sync[target].period = 0; 664 #ifdef DEBUG 665 if (siopsync_debug) 666 printf ("Forcing target %d asynchronous\n", target); 667 #endif 668 } 669 else { 670 dev->sc_msg[1] = MSG_IDENTIFY; 671 dev->sc_msg[2] = MSG_EXT_MESSAGE; 672 dev->sc_msg[3] = 3; 673 dev->sc_msg[4] = MSG_SYNC_REQ; 674 dev->sc_msg[5] = siop_sync_period / 4; 675 dev->sc_msg[6] = SIOP_MAX_OFFSET; 676 dev->sc_ds.sdtrolen = 6; 677 dev->sc_ds.sdtrilen = 6; 678 dev->sc_ds.sdtrobuf = dev->sc_ds.sdtribuf = (char *) (dev->sc_msgpa + 1); 679 dev->sc_sync[target].state = SYNC_SENT; 680 #ifdef DEBUG 681 if (siopsync_debug) 682 printf ("Sending sync request to target %d\n", target); 683 #endif 684 } 685 } 686 687 /* 688 * If length is > 1 page, check for consecutive physical pages 689 * Need to set up chaining if not 690 */ 691 nchain = 0; 692 count = len; 693 addr = buf; 694 dmaend = NULL; 695 while (count > 0) { 696 dev->sc_ds.chain[nchain].databuf = (char *) kvtop (addr); 697 if (count < (tcount = NBPG - ((int) addr & PGOFSET))) 698 tcount = count; 699 dev->sc_ds.chain[nchain].datalen = tcount; 700 addr += tcount; 701 count -= tcount; 702 if (dev->sc_ds.chain[nchain].databuf == dmaend) { 703 dmaend += dev->sc_ds.chain[nchain].datalen; 704 dev->sc_ds.chain[--nchain].datalen += tcount; 705 #ifdef DEBUG 706 ++siopdma_hits; 707 #endif 708 } 709 else { 710 dmaend = dev->sc_ds.chain[nchain].databuf + 711 dev->sc_ds.chain[nchain].datalen; 712 dev->sc_ds.chain[nchain].datalen = tcount; 713 #ifdef DEBUG 714 if (nchain) /* Don't count miss on first one */ 715 ++siopdma_misses; 716 #endif 717 } 718 ++nchain; 719 if (nchain < DMAMAXIO) /* force error if buffer too small */ 720 dev->sc_ds.chain[nchain].datalen = 0; 721 } 722 #ifdef DEBUG 723 if (nchain != 1 && len != 0 && siop_debug & 3) { 724 printf ("DMA chaining set: %d\n", nchain); 725 for (i = 0; i < nchain; ++i) { 726 printf (" [%d] %8x %4x\n", i, dev->sc_ds.chain[i].databuf, 727 dev->sc_ds.chain[i].datalen); 728 } 729 } 730 #endif 731 732 regs->siop_sbcl = dev->sc_sync[target].offset; 733 if (dev->sc_ds.sdtrolen) 734 regs->siop_scratch = regs->siop_scratch | 0x100; 735 else 736 regs->siop_scratch = regs->siop_scratch & ~0xff00; 737 regs->siop_dsa = dev->sc_dspa; 738 /* push data case on things the 53c710 needs to access */ 739 dma_cachectl (dev, sizeof (struct siop_softc)); 740 dma_cachectl (cbuf, clen); 741 if (buf != NULL && len != 0) 742 dma_cachectl (buf, len); 743 regs->siop_dsp = dev->sc_scriptspa; 744 } 745 746 /* 747 * Process a DMA or SCSI interrupt from the 53C710 SIOP 748 */ 749 750 int 751 siop_checkintr(dev, istat, dstat, sstat0, status) 752 struct siop_softc *dev; 753 u_char istat; 754 u_char dstat; 755 u_char sstat0; 756 int *status; 757 { 758 siop_regmap_p regs = dev->sc_siopp; 759 int target; 760 761 regs->siop_ctest8 |= 0x04; 762 while ((regs->siop_ctest1 & SIOP_CTEST1_FMT) == 0) 763 ; 764 regs->siop_ctest8 &= ~0x04; 765 #ifdef DEBUG 766 if (siop_debug & 1) { 767 DCIAS(dev->sc_statuspa); /* XXX */ 768 printf ("siopchkintr: istat %x dstat %x sstat0 %x dsps %x sbcl %x sts %x msg %x\n", 769 istat, dstat, sstat0, regs->siop_dsps, regs->siop_sbcl, dev->sc_stat[0], dev->sc_msg[0]); 770 } 771 #endif 772 if (dstat & SIOP_DSTAT_SIR && (regs->siop_dsps == 0xff00 || 773 regs->siop_dsps == 0xfffc)) { 774 /* Normal completion status, or check condition */ 775 if (regs->siop_dsa != dev->sc_dspa) { 776 printf ("siop: invalid dsa: %x %x\n", regs->siop_dsa, 777 dev->sc_dspa); 778 panic("*** siop DSA invalid ***"); 779 } 780 target = dev->sc_slave; 781 if (dev->sc_sync[target].state == SYNC_SENT) { 782 #ifdef DEBUG 783 if (siopsync_debug) 784 printf ("sync msg in: %02x %02x %02x %02x %02x %02x\n", 785 dev->sc_msg[1], dev->sc_msg[2], dev->sc_msg[3], 786 dev->sc_msg[4], dev->sc_msg[5], dev->sc_msg[6]); 787 #endif 788 if (dev->sc_msg[0] == MSG_REJECT) 789 printf ("target %d sync request was rejected\n", 790 target); 791 dev->sc_sync[target].state = SYNC_DONE; 792 dev->sc_sync[target].period = 0; 793 dev->sc_sync[target].offset = 0; 794 if (dev->sc_msg[1] == MSG_EXT_MESSAGE && 795 dev->sc_msg[2] == 3 && 796 dev->sc_msg[3] == MSG_SYNC_REQ && 797 dev->sc_msg[5] != 0) { 798 if (dev->sc_msg[4] && dev->sc_msg[4] < 100 / 4) { 799 #ifdef DEBUG 800 printf ("%d: target %d wanted %dns period\n", 801 dev->sc_dev.dv_xname, target, 802 dev->sc_msg[4] * 4); 803 #endif 804 /* 805 * Kludge for Maxtor XT8580S 806 * It accepts whatever we request, even 807 * though it won't work. So we ask for 808 * a short period than we can handle. If 809 * the device says it can do it, use 208ns. 810 * If the device says it can do less than 811 * 100ns, then we limit it to 100ns. 812 */ 813 if (dev->sc_msg[4] == siop_sync_period / 4) 814 dev->sc_msg[4] = 208 / 4; 815 else 816 dev->sc_msg[4] = 100 / 4; 817 } 818 printf ("%s: target %d now synchronous, period=%dns, offset=%d\n", 819 dev->sc_dev.dv_xname, target, 820 dev->sc_msg[4] * 4, dev->sc_msg[5]); 821 scsi_period_to_siop (dev, target); 822 } 823 } 824 #if 0 825 DCIAS(dev->sc_statuspa); /* XXX */ 826 #else 827 dma_cachectl(&dev->sc_stat[0], 1); 828 #endif 829 *status = dev->sc_stat[0]; 830 return 1; 831 } 832 if (sstat0 & SIOP_SSTAT0_M_A) { /* Phase mismatch */ 833 #ifdef DEBUG 834 if (siop_debug & 9) 835 printf ("Phase mismatch: %x dsp +%x\n", regs->siop_sbcl, 836 regs->siop_dsp - dev->sc_scriptspa); 837 if (siop_debug & 0x10) 838 panic ("53c710 phase mismatch"); 839 #endif 840 if ((regs->siop_sbcl & SIOP_REQ) == 0) 841 printf ("Phase mismatch: REQ not asserted! %02x\n", 842 regs->siop_sbcl); 843 switch (regs->siop_sbcl & 7) { 844 /* 845 * For data out and data in phase, check for DMA chaining 846 */ 847 848 /* 849 * for message in, check for possible reject for sync request 850 */ 851 case 0: 852 regs->siop_dsp = dev->sc_scriptspa + Ent_dataout; 853 break; 854 case 1: 855 regs->siop_dsp = dev->sc_scriptspa + Ent_datain; 856 break; 857 case 2: 858 regs->siop_dsp = dev->sc_scriptspa + Ent_cmd; 859 break; 860 case 3: 861 regs->siop_dsp = dev->sc_scriptspa + Ent_status; 862 break; 863 case 6: 864 regs->siop_dsp = dev->sc_scriptspa + Ent_msgout; 865 break; 866 case 7: 867 regs->siop_dsp = dev->sc_scriptspa + Ent_msgin; 868 break; 869 default: 870 goto bad_phase; 871 } 872 return 0; 873 } 874 if (sstat0 & SIOP_SSTAT0_STO) { /* Select timed out */ 875 *status = -1; 876 return 1; 877 } 878 if (dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff05 && 879 (regs->siop_sbcl & (SIOP_MSG | SIOP_CD)) == 0) { 880 printf ("DMA chaining failed\n"); 881 siopreset (dev); 882 *status = -1; 883 return 1; 884 } 885 if (dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff27) { 886 #ifdef DEBUG 887 if (siop_debug & 3) 888 printf ("DMA chaining completed: dsa %x dnad %x addr %x\n", 889 regs->siop_dsa, regs->siop_dnad, regs->siop_addr); 890 ++siopchain_ints; 891 #endif 892 regs->siop_dsa = dev->sc_dspa; 893 regs->siop_dsp = dev->sc_scriptspa + Ent_status; 894 return 0; 895 } 896 target = dev->sc_slave; 897 if (dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff26 && 898 dev->sc_msg[0] == MSG_REJECT && dev->sc_sync[target].state == SYNC_SENT) { 899 dev->sc_sync[target].state = SYNC_DONE; 900 dev->sc_sync[target].period = 0; 901 dev->sc_sync[target].offset = 0; 902 dev->sc_ds.sdtrolen = 0; 903 dev->sc_ds.sdtrilen = 0; 904 #ifdef DEBUG 905 if (siopsync_debug || 1) 906 printf ("target %d rejected sync, going asynchronous\n", target); 907 #endif 908 siop_inhibit_sync[target] = -1; 909 if ((regs->siop_sbcl & 7) == 6) { 910 regs->siop_dsp = dev->sc_scriptspa + Ent_msgout; 911 return (0); 912 } 913 regs->siop_dcntl |= SIOP_DCNTL_STD; 914 return (0); 915 } 916 if ((dstat & SIOP_DSTAT_SIR && regs->siop_dsps == 0xff13) || 917 sstat0 & SIOP_SSTAT0_UDC) { 918 #ifdef DEBUG 919 printf ("%s: target %d disconnected unexpectedly\n", 920 dev->sc_dev.dv_xname, target); 921 #endif 922 #if 0 923 siopabort (dev, regs, "siopchkintr"); 924 #endif 925 *status = STS_BUSY; 926 return 1; 927 } 928 if (dstat & SIOP_DSTAT_SIR &®s->siop_dsps == 0xfffb) { 929 #if 0 930 printf ("%s: target %d busy\n", dev->sc_dev.dv_xname, target); 931 #endif 932 #if 0 933 siopabort (dev, regs, "siopchkintr"); 934 #endif 935 *status = STS_BUSY; 936 return 1; 937 } 938 if (sstat0 == 0 && dstat & SIOP_DSTAT_SIR) { 939 #if 0 940 DCIAS(dev->sc_statuspa); 941 #else 942 dma_cachectl (&dev->sc_stat[0], 1); 943 #endif 944 printf ("SIOP interrupt: %x sts %x msg %x sbcl %x\n", 945 regs->siop_dsps, dev->sc_stat[0], dev->sc_msg[0], 946 regs->siop_sbcl); 947 siopreset (dev); 948 *status = -1; 949 return 1; 950 } 951 bad_phase: 952 /* 953 * temporary panic for unhandled conditions 954 * displays various things about the 53C710 status and registers 955 * then panics. 956 * XXXX need to clean this up to print out the info, reset, and continue 957 */ 958 printf ("siopchkintr: target %x ds %x\n", target, &dev->sc_ds); 959 printf ("scripts %x ds %x regs %x dsp %x dcmd %x\n", dev->sc_scriptspa, 960 dev->sc_dspa, kvtop(regs), regs->siop_dsp, *((long *)®s->siop_dcmd)); 961 printf ("siopchkintr: istat %x dstat %x sstat0 %x dsps %x dsa %x sbcl %x sts %x msg %x\n", 962 istat, dstat, sstat0, regs->siop_dsps, regs->siop_dsa, regs->siop_sbcl, 963 dev->sc_stat[0], dev->sc_msg[0]); 964 panic("siopchkintr: **** temp ****"); 965 } 966 967 /* 968 * SCSI 'immediate' command: issue a command to some SCSI device 969 * and get back an 'immediate' response (i.e., do programmed xfer 970 * to get the response data). 'cbuf' is a buffer containing a scsi 971 * command of length clen bytes. 'buf' is a buffer of length 'len' 972 * bytes for data. The transfer direction is determined by the device 973 * (i.e., by the scsi bus data xfer phase). If 'len' is zero, the 974 * command must supply no data. 'xferphase' is the bus phase the 975 * caller expects to happen after the command is issued. It should 976 * be one of DATA_IN_PHASE, DATA_OUT_PHASE or STATUS_PHASE. 977 * 978 * XXX - 53C710 will use DMA, but no interrupts (it's a heck of a 979 * lot easier to do than to use programmed I/O). 980 * 981 */ 982 int 983 siopicmd(dev, target, cbuf, clen, buf, len) 984 struct siop_softc *dev; 985 int target; 986 void *cbuf; 987 int clen; 988 void *buf; 989 int len; 990 { 991 siop_regmap_p regs = dev->sc_siopp; 992 int i; 993 int status; 994 u_char istat; 995 u_char dstat; 996 u_char sstat0; 997 998 if (dev->sc_flags & SIOP_SELECTED) { 999 printf ("siopicmd%d: bus busy\n", target); 1000 return -1; 1001 } 1002 regs->siop_sien = 0x00; /* disable SCSI and DMA interrupts */ 1003 regs->siop_dien = 0x00; 1004 dev->sc_flags |= SIOP_SELECTED; 1005 dev->sc_slave = target; 1006 #ifdef DEBUG 1007 if (siop_debug & 1) 1008 printf ("siopicmd: target %x cmd %02x ds %x\n", target, 1009 *((char *)cbuf), &dev->sc_ds); 1010 #endif 1011 siop_setup (dev, target, cbuf, clen, buf, len); 1012 1013 for (;;) { 1014 /* use cmd_wait values? */ 1015 i = siop_cmd_wait << 1; 1016 while (((istat = regs->siop_istat) & 1017 (SIOP_ISTAT_SIP | SIOP_ISTAT_DIP)) == 0) { 1018 if (--i <= 0) { 1019 printf ("waiting: tgt %d cmd %02x sbcl %02x dsp %x (+%x) dcmd %x ds %x\n", 1020 target, *((char *)cbuf), 1021 regs->siop_sbcl, regs->siop_dsp, 1022 regs->siop_dsp - dev->sc_scriptspa, 1023 *((long *)®s->siop_dcmd), &dev->sc_ds); 1024 i = siop_cmd_wait << 2; 1025 /* XXXX need an upper limit and reset */ 1026 } 1027 delay(1); 1028 } 1029 dstat = regs->siop_dstat; 1030 sstat0 = regs->siop_sstat0; 1031 #ifdef DEBUG 1032 if (siop_debug & 1) { 1033 DCIAS(dev->sc_statuspa); /* XXX should just invalidate dev->sc_stat */ 1034 printf ("siopicmd: istat %x dstat %x sstat0 %x dsps %x sbcl %x sts %x msg %x\n", 1035 istat, dstat, sstat0, regs->siop_dsps, regs->siop_sbcl, 1036 dev->sc_stat[0], dev->sc_msg[0]); 1037 } 1038 #endif 1039 if (siop_checkintr(dev, istat, dstat, sstat0, &status)) { 1040 dev->sc_flags &= ~SIOP_SELECTED; 1041 return (status); 1042 } 1043 } 1044 } 1045 1046 int 1047 siopgo(dev, xs) 1048 struct siop_softc *dev; 1049 struct scsi_xfer *xs; 1050 { 1051 siop_regmap_p regs; 1052 int i; 1053 int nchain; 1054 int count, tcount; 1055 char *addr, *dmaend; 1056 1057 #ifdef DEBUG 1058 if (siop_debug & 1) 1059 printf ("%s: go ", dev->sc_dev.dv_xname); 1060 #if 0 1061 if ((cdb->cdb[1] & 1) == 0 && 1062 ((cdb->cdb[0] == CMD_WRITE && cdb->cdb[2] == 0 && cdb->cdb[3] == 0) || 1063 (cdb->cdb[0] == CMD_WRITE_EXT && cdb->cdb[2] == 0 && cdb->cdb[3] == 0 1064 && cdb->cdb[4] == 0))) 1065 panic ("siopgo: attempted write to block < 0x100"); 1066 #endif 1067 #endif 1068 #if 0 1069 cdb->cdb[1] |= unit << 5; 1070 #endif 1071 1072 if (dev->sc_flags & SIOP_SELECTED) { 1073 printf ("%s: bus busy\n", dev->sc_dev.dv_xname); 1074 return 1; 1075 } 1076 1077 dev->sc_flags |= SIOP_SELECTED | SIOP_DMA; 1078 dev->sc_slave = xs->sc_link->target; 1079 regs = dev->sc_siopp; 1080 /* enable SCSI and DMA interrupts */ 1081 regs->siop_sien = SIOP_SIEN_M_A | SIOP_SIEN_STO | SIOP_SIEN_SEL | SIOP_SIEN_SGE | 1082 SIOP_SIEN_UDC | SIOP_SIEN_RST | SIOP_SIEN_PAR; 1083 regs->siop_dien = 0x20 | SIOP_DIEN_ABRT | SIOP_DIEN_SIR | SIOP_DIEN_WTD | 1084 SIOP_DIEN_OPC; 1085 #ifdef DEBUG 1086 if (siop_debug & 1) 1087 printf ("siopgo: target %x cmd %02x ds %x\n", dev->sc_slave, xs->cmd->opcode, &dev->sc_ds); 1088 #endif 1089 1090 siop_setup(dev, dev->sc_slave, xs->cmd, xs->cmdlen, xs->data, xs->datalen); 1091 1092 return (0); 1093 } 1094 1095 /* 1096 * Check for 53C710 interrupts 1097 */ 1098 1099 int 1100 siopintr (dev) 1101 register struct siop_softc *dev; 1102 { 1103 siop_regmap_p regs; 1104 register u_char istat, dstat, sstat0; 1105 int unit; 1106 int status; 1107 int found = 0; 1108 1109 regs = dev->sc_siopp; 1110 istat = dev->sc_istat; 1111 if ((istat & (SIOP_ISTAT_SIP | SIOP_ISTAT_DIP)) == 0) 1112 return; 1113 if ((dev->sc_flags & (SIOP_DMA | SIOP_SELECTED)) == SIOP_SELECTED) 1114 return; /* doing non-interrupt I/O */ 1115 /* Got a valid interrupt on this device */ 1116 dstat = dev->sc_dstat; 1117 sstat0 = dev->sc_sstat0; 1118 dev->sc_istat = 0; 1119 #ifdef DEBUG 1120 if (siop_debug & 1) 1121 printf ("%s: intr istat %x dstat %x sstat0 %x\n", 1122 dev->sc_dev.dv_xname, istat, dstat, sstat0); 1123 if ((dev->sc_flags & SIOP_DMA) == 0) { 1124 printf ("%s: spurious interrupt? istat %x dstat %x sstat0 %x\n", 1125 dev->sc_dev.dv_xname, istat, dstat, sstat0); 1126 } 1127 #endif 1128 1129 #ifdef DEBUG 1130 if (siop_debug & 5) { 1131 DCIAS(dev->sc_statuspa); 1132 printf ("siopintr%d: istat %x dstat %x sstat0 %x dsps %x sbcl %x sts %x msg %x\n", 1133 unit, istat, dstat, sstat0, regs->siop_dsps, 1134 regs->siop_sbcl, dev->sc_stat[0], dev->sc_msg[0]); 1135 } 1136 #endif 1137 if (siop_checkintr (dev, istat, dstat, sstat0, &status)) { 1138 #if 1 1139 regs->siop_sien = 0; 1140 regs->siop_dien = 0; 1141 if (status == 0xff) 1142 printf ("siopintr: status == 0xff\n"); 1143 #endif 1144 dev->sc_flags &= ~(SIOP_DMA | SIOP_SELECTED); 1145 siop_scsidone(dev, dev->sc_stat[0]); 1146 } 1147 } 1148 1149 scsi_period_to_siop (dev, target) 1150 struct siop_softc *dev; 1151 { 1152 int period, offset, i, sxfer; 1153 1154 period = dev->sc_msg[4]; 1155 offset = dev->sc_msg[5]; 1156 sxfer = 0; 1157 if (offset <= SIOP_MAX_OFFSET) 1158 sxfer = offset; 1159 for (i = 0; i < sizeof (xxx) / 2; ++i) { 1160 if (period <= xxx[i].x) { 1161 sxfer |= xxx[i].y & 0x70; 1162 offset = xxx[i].y & 0x03; 1163 break; 1164 } 1165 } 1166 dev->sc_sync[target].period = sxfer; 1167 dev->sc_sync[target].offset = offset; 1168 #ifdef DEBUG 1169 printf ("sync: siop_sxfr %02x, siop_sbcl %02x\n", sxfer, offset); 1170 #endif 1171 } 1172
Indexes created Mon Sep 22 05:09:51 GMT 2025