1 1.16 andvar /* $NetBSD: siopreg.h,v 1.16 2022/06/27 20:28:31 andvar Exp $ */ 2 1.5 cgd 3 1.1 mw /* 4 1.1 mw * Copyright (c) 1990 The Regents of the University of California. 5 1.1 mw * All rights reserved. 6 1.1 mw * 7 1.1 mw * This code is derived from software contributed to Berkeley by 8 1.1 mw * Van Jacobson of Lawrence Berkeley Laboratory. 9 1.1 mw * 10 1.1 mw * Redistribution and use in source and binary forms, with or without 11 1.1 mw * modification, are permitted provided that the following conditions 12 1.1 mw * are met: 13 1.1 mw * 1. Redistributions of source code must retain the above copyright 14 1.1 mw * notice, this list of conditions and the following disclaimer. 15 1.1 mw * 2. Redistributions in binary form must reproduce the above copyright 16 1.1 mw * notice, this list of conditions and the following disclaimer in the 17 1.1 mw * documentation and/or other materials provided with the distribution. 18 1.12 agc * 3. Neither the name of the University nor the names of its contributors 19 1.1 mw * may be used to endorse or promote products derived from this software 20 1.1 mw * without specific prior written permission. 21 1.1 mw * 22 1.1 mw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 23 1.1 mw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 1.1 mw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 1.1 mw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 26 1.1 mw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 1.1 mw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 28 1.1 mw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 29 1.1 mw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 30 1.1 mw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 31 1.1 mw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 1.1 mw * SUCH DAMAGE. 33 1.1 mw * 34 1.2 chopps * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 35 1.1 mw */ 36 1.1 mw 37 1.1 mw /* 38 1.1 mw * NCR 53C710 SCSI interface hardware description. 39 1.1 mw * 40 1.6 chopps * From the Mach scsi driver for the 53C700 41 1.1 mw */ 42 1.1 mw 43 1.1 mw typedef struct { 44 1.9 is 45 1.9 is #ifndef ARCH_720 46 1.9 is 47 1.7 chopps /*00*/ volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */ 48 1.7 chopps /*01*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 49 1.7 chopps /*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 50 1.7 chopps /*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 51 1.9 is 52 1.7 chopps /*04*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 53 1.7 chopps /*05*/ volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */ 54 1.7 chopps /*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 55 1.7 chopps /*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 56 1.9 is 57 1.7 chopps /*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 58 1.7 chopps /*09*/ volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */ 59 1.7 chopps /*0a*/ volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */ 60 1.7 chopps /*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 61 1.9 is 62 1.7 chopps /*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 63 1.7 chopps /*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 64 1.7 chopps /*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 65 1.7 chopps /*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */ 66 1.9 is 67 1.7 chopps /*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 68 1.9 is 69 1.7 chopps /*14*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 70 1.7 chopps /*15*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 71 1.7 chopps /*16*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 72 1.7 chopps /*17*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 73 1.9 is 74 1.7 chopps /*18*/ volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */ 75 1.7 chopps /*19*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 76 1.7 chopps /*1a*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 77 1.7 chopps /*1b*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 78 1.9 is 79 1.7 chopps /*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 80 1.9 is 81 1.7 chopps /*20*/ volatile unsigned char siop_lcrc; /* rw: LCRC value */ 82 1.7 chopps /*21*/ volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */ 83 1.7 chopps /*22*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 84 1.7 chopps /*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 85 1.9 is 86 1.7 chopps /*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 87 1.7 chopps /*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 88 1.7 chopps /*26*/ volatile unsigned char siop_dbc1; 89 1.7 chopps /*27*/ volatile unsigned char siop_dbc0; 90 1.9 is 91 1.7 chopps /*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 92 1.9 is 93 1.7 chopps /*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 94 1.9 is 95 1.7 chopps /*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 96 1.9 is 97 1.7 chopps /*34*/ volatile unsigned long siop_scratch; /* rw: Scratch Register */ 98 1.9 is 99 1.9 is /*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 100 1.9 is /*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 101 1.9 is /*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 102 1.9 is /*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 103 1.9 is 104 1.9 is /*3c*/ volatile unsigned long siop_adder; 105 1.9 is 106 1.9 is #else 107 1.9 is 108 1.9 is /*00*/ volatile unsigned char siop_scntl3; /* rw: SCSI control reg 3 */ 109 1.9 is /*01*/ volatile unsigned char siop_scntl2; /* rw: SCSI control reg 2 */ 110 1.9 is /*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 111 1.9 is /*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 112 1.9 is 113 1.9 is /*04*/ volatile unsigned char siop_gpreg; /* rw: SCSI */ 114 1.9 is /*05*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 115 1.9 is /*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 116 1.9 is /*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 117 1.9 is 118 1.9 is /*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 119 1.9 is /*09*/ volatile unsigned char siop_ssid; /* ro: SCSI */ 120 1.9 is /*0a*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 121 1.9 is /*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 122 1.9 is 123 1.9 is /*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 124 1.9 is /*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 125 1.9 is /*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 126 1.9 is /*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */ 127 1.9 is 128 1.9 is /*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 129 1.9 is 130 1.9 is /*14*/ volatile unsigned char siop_14_; /* ??: */ 131 1.9 is /*15*/ volatile unsigned char siop_15_; /* ??: */ 132 1.9 is /*16*/ volatile unsigned char siop_16_; /* ??: */ 133 1.9 is /*17*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 134 1.9 is 135 1.9 is /*18*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 136 1.9 is /*19*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 137 1.9 is /*1a*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 138 1.9 is /*1b*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 139 1.9 is 140 1.9 is /*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 141 1.9 is 142 1.9 is /*20*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 143 1.9 is /*21*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 144 1.9 is /*22*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 145 1.9 is /*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 146 1.9 is 147 1.9 is /*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 148 1.9 is /*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 149 1.9 is /*26*/ volatile unsigned char siop_dbc1; 150 1.9 is /*27*/ volatile unsigned char siop_dbc0; 151 1.9 is 152 1.9 is /*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 153 1.9 is 154 1.9 is /*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 155 1.9 is 156 1.9 is /*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 157 1.9 is 158 1.9 is /*34*/ volatile unsigned long siop_scratcha; /* rw: Scratch Register A */ 159 1.9 is 160 1.7 chopps /*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 161 1.7 chopps /*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 162 1.7 chopps /*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 163 1.7 chopps /*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 164 1.9 is 165 1.7 chopps /*3c*/ volatile unsigned long siop_adder; 166 1.1 mw 167 1.9 is /*40*/ volatile unsigned short siop_sist; /* rw: SCSI Interrupt Status */ 168 1.9 is #define SIOP_SIST_STO 0x0400 /* timeout (select) */ 169 1.9 is #define SIOP_SIST_GEN 0x0200 /* timeout (general) */ 170 1.10 mhitch #define SIOP_SIST_HTH 0x0100 /* handshake timer expired */ 171 1.10 mhitch #define SIOP_SIST_MA 0x0080 /* phase mismatch */ 172 1.10 mhitch #define SIOP_SIST_CMP 0x0040 /* function complete */ 173 1.10 mhitch #define SIOP_SIST_SEL 0x0020 /* selected */ 174 1.10 mhitch #define SIOP_SIST_RSL 0x0010 /* reselected */ 175 1.9 is #define SIOP_SIST_SGE 0x0008 /* gross error (over/underflow) */ 176 1.9 is #define SIOP_SIST_UDC 0x0004 /* unexpected disconnect */ 177 1.10 mhitch #define SIOP_SIST_RST 0x0002 /* RST received */ 178 1.9 is #define SIOP_SIST_PAR 0x0001 /* scsi parity error */ 179 1.9 is /*42*/ volatile unsigned short siop_sien; /* rw: SCSI Interrupt Enable */ 180 1.9 is #define SIOP_SIEN_STO 0x0400 /* timeout (select) */ 181 1.9 is #define SIOP_SIEN_GEN 0x0200 /* timeout (general) */ 182 1.10 mhitch #define SIOP_SIEN_HTH 0x0100 /* handshake timer expired */ 183 1.9 is #define SIOP_SIEN_MA 0x0080 /* phase mispatch */ 184 1.10 mhitch #define SIOP_SIEN_CMP 0x0040 /* function complete */ 185 1.10 mhitch #define SIOP_SIEN_SEL 0x0020 /* selected */ 186 1.10 mhitch #define SIOP_SIEN_RSL 0x0010 /* reselected */ 187 1.9 is #define SIOP_SIEN_SGE 0x0008 /* gross error (over/underflow) */ 188 1.9 is #define SIOP_SIEN_UDC 0x0004 /* unexpected disconnect */ 189 1.9 is #define SIOP_SIEN_RST 0x0002 /* scsi bus reset */ 190 1.9 is #define SIOP_SIEN_PAR 0x0001 /* scsi parity error */ 191 1.9 is 192 1.9 is /*44*/ volatile unsigned char siop_gpcntl; /* rw: SCSI */ 193 1.9 is /*45*/ volatile unsigned char siop_macntl; /* rw: SCSI */ 194 1.9 is /*46*/ volatile unsigned char siop_swide; /* rw: SCSI */ 195 1.9 is /*47*/ volatile unsigned char siop_slpar; /* rw: SCSI */ 196 1.9 is 197 1.9 is /*48*/ volatile unsigned short siop_respid; /* rw: SCSI Reselect-IDS */ 198 1.9 is /*4a*/ volatile unsigned char siop_stime1; /* rw: SCSI */ 199 1.9 is /*4b*/ volatile unsigned char siop_stime0; /* rw: SCSI */ 200 1.9 is 201 1.9 is /*4c*/ volatile unsigned char siop_stest3; /* ro: Chip test register 3 */ 202 1.10 mhitch #define SIOP_STEST3_HSC 0x20 /* Halt SCSI Clock */ 203 1.9 is /*4d*/ volatile unsigned char siop_stest2; /* ro: Chip test register 2 */ 204 1.9 is /*4e*/ volatile unsigned char siop_stest1; /* ro: Chip test register 1 */ 205 1.10 mhitch #define SIOP_STEST1_DBLEN 0x08 /* SCLK Double Enable */ 206 1.10 mhitch #define SIOP_STEST1_DBLSEL 0x04 /* SCLK Doubler Select */ 207 1.9 is /*4f*/ volatile unsigned char siop_stest0; /* ro: Chip test register 0 */ 208 1.9 is 209 1.9 is /*50*/ volatile unsigned char siop_50_; /* rw: SCSI */ 210 1.9 is /*51*/ volatile unsigned char siop_stest4; /* rw: SCSI */ 211 1.9 is /*52*/ volatile unsigned short siop_sidl; /* ro: SCSI Input Data Latch */ 212 1.9 is 213 1.9 is /*54*/ volatile unsigned short siop_54_; /* rw: SCSI */ 214 1.9 is /*56*/ volatile unsigned short siop_sodl; /* rw: SCSI Output Data Latch */ 215 1.9 is 216 1.9 is /*58*/ volatile unsigned short siop_58_; /* rw: SCSI */ 217 1.9 is /*5a*/ volatile unsigned short siop_sbdl; /* ro: SCSI Bus Data Lines */ 218 1.9 is 219 1.9 is /*5c*/ volatile unsigned long siop_scratchb; /* rw: Scratch Register B */ 220 1.9 is #endif 221 1.9 is 222 1.1 mw } siop_regmap_t; 223 1.4 chopps typedef volatile siop_regmap_t *siop_regmap_p; 224 1.1 mw 225 1.1 mw /* 226 1.1 mw * Register defines 227 1.1 mw */ 228 1.1 mw 229 1.1 mw /* Scsi control register 0 (scntl0) */ 230 1.1 mw 231 1.1 mw #define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 232 1.1 mw # define SIOP_ARB_SIMPLE 0x00 233 1.1 mw # define SIOP_ARB_FULL 0xc0 234 1.1 mw #define SIOP_SCNTL0_START 0x20 /* Start Sequence */ 235 1.1 mw #define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 236 1.1 mw #define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 237 1.1 mw #define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 238 1.1 mw #define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 239 1.1 mw #define SIOP_SCNTL0_TRG 0x01 /* Target Mode */ 240 1.1 mw 241 1.1 mw /* Scsi control register 1 (scntl1) */ 242 1.1 mw 243 1.1 mw #define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 244 1.1 mw #define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 245 1.10 mhitch #ifndef ARCH_720 246 1.1 mw #define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 247 1.10 mhitch #else 248 1.10 mhitch #define SIOP_SCNTL1_DHP 0x20 /* Disable Halt on Parity or ATN */ 249 1.10 mhitch #endif 250 1.1 mw #define SIOP_SCNTL1_CON 0x10 /* Connected */ 251 1.1 mw #define SIOP_SCNTL1_RST 0x08 /* Assert RST */ 252 1.6 chopps #define SIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ 253 1.10 mhitch #ifndef ARCH_720 254 1.6 chopps #define SIOP_SCNTL1_RES0 0x02 /* Reserved */ 255 1.6 chopps #define SIOP_SCNTL1_RES1 0x01 /* Reserved */ 256 1.10 mhitch #else 257 1.10 mhitch #define SIOP_SCNTL1_IARB 0x02 /* Immediate Arbitration */ 258 1.10 mhitch #define SIOP_SCNTL1_SST 0x01 /* Start SCSI Transfer */ 259 1.10 mhitch #endif 260 1.10 mhitch 261 1.10 mhitch /* Scsi control register 3 (scntl3) */ 262 1.10 mhitch 263 1.10 mhitch #ifdef ARCH_720 264 1.10 mhitch #define SIOP_SCNTL3_ULTRA 0x80 /* Ultra Enable */ 265 1.10 mhitch #define SIOP_SCNTL3_SCF 0x70 /* Synch Clock Conversion Factor */ 266 1.10 mhitch #define SIOP_SCNTL3_EWS 0x08 /* Enable Wide SCSI */ 267 1.10 mhitch #define SIOP_SCNTL3_CCF 0x07 /* Clock Conversion Factor */ 268 1.10 mhitch #endif 269 1.1 mw 270 1.1 mw /* Scsi interrupt enable register (sien) */ 271 1.1 mw 272 1.9 is #ifndef ARCH_720 273 1.1 mw #define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 274 1.6 chopps #define SIOP_SIEN_FCMP 0x40 /* Function Complete */ 275 1.1 mw #define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 276 1.1 mw #define SIOP_SIEN_SEL 0x10 /* (Re)Selected */ 277 1.1 mw #define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 278 1.1 mw #define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 279 1.1 mw #define SIOP_SIEN_RST 0x02 /* RST asserted */ 280 1.1 mw #define SIOP_SIEN_PAR 0x01 /* Parity Error */ 281 1.9 is #endif 282 1.1 mw 283 1.1 mw /* Scsi chip ID (scid) */ 284 1.1 mw 285 1.1 mw #define SIOP_SCID_VALUE(i) (1<<i) 286 1.10 mhitch #ifdef ARCH_720 287 1.10 mhitch #define SIOP_SCID_RRE 0x40 /* Enable Response to Reselection */ 288 1.10 mhitch #define SIOP_SCID_SRE 0x20 /* Enable Response to Selection */ 289 1.10 mhitch #endif 290 1.1 mw 291 1.1 mw /* Scsi transfer register (sxfer) */ 292 1.1 mw 293 1.10 mhitch #ifndef ARCH_720 294 1.1 mw #define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */ 295 1.1 mw #define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 296 1.1 mw /* see specs for formulas: 297 1.1 mw Period = TCP * (4 + XFERP ) 298 1.1 mw TCP = 1 + CLK + 1..2; 299 1.1 mw */ 300 1.1 mw #define SIOP_SXFER_MO 0x0f /* Synch Max Offset */ 301 1.1 mw # define SIOP_MAX_OFFSET 8 302 1.9 is #else 303 1.10 mhitch #define SIOP_SXFER_TP 0xe0 /* Synch Transfer Period */ 304 1.10 mhitch /* see specs for formulas: 305 1.10 mhitch Period = TCP * (4 + XFERP ) 306 1.10 mhitch TCP = 1 + CLK + 1..2; 307 1.10 mhitch */ 308 1.9 is #define SIOP_SXFER_MO 0x1f /* Synch Max Offset */ 309 1.9 is # define SIOP_MAX_OFFSET 16 310 1.9 is #endif 311 1.1 mw 312 1.1 mw /* Scsi output data latch register (sodl) */ 313 1.1 mw 314 1.1 mw /* Scsi output control latch register (socl) */ 315 1.1 mw 316 1.1 mw #define SIOP_REQ 0x80 /* SCSI signal <x> asserted */ 317 1.1 mw #define SIOP_ACK 0x40 318 1.1 mw #define SIOP_BSY 0x20 319 1.1 mw #define SIOP_SEL 0x10 320 1.1 mw #define SIOP_ATN 0x08 321 1.1 mw #define SIOP_MSG 0x04 322 1.1 mw #define SIOP_CD 0x02 323 1.1 mw #define SIOP_IO 0x01 324 1.1 mw 325 1.1 mw #define SIOP_PHASE(socl) SCSI_PHASE(socl) 326 1.1 mw 327 1.1 mw /* Scsi first byte received register (sfbr) */ 328 1.1 mw 329 1.1 mw /* Scsi input data latch register (sidl) */ 330 1.1 mw 331 1.1 mw /* Scsi bus data lines register (sbdl) */ 332 1.1 mw 333 1.1 mw /* Scsi bus control lines register (sbcl). Same as socl */ 334 1.1 mw 335 1.1 mw /* DMA status register (dstat) */ 336 1.1 mw 337 1.1 mw #define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 338 1.10 mhitch #ifndef ARCH_720 339 1.6 chopps #define SIOP_DSTAT_RES 0x40 340 1.10 mhitch #else 341 1.10 mhitch #define SIOP_DSTAT_HPE 0x40 /* Host Parity Error */ 342 1.10 mhitch #endif 343 1.6 chopps #define SIOP_DSTAT_BF 0x20 /* Bus fault */ 344 1.1 mw #define SIOP_DSTAT_ABRT 0x10 /* Aborted */ 345 1.1 mw #define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 346 1.1 mw #define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 347 1.1 mw #define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 348 1.6 chopps #define SIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ 349 1.1 mw 350 1.1 mw /* Scsi status register 0 (sstat0) */ 351 1.1 mw 352 1.10 mhitch #ifndef ARCH_720 353 1.1 mw #define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 354 1.6 chopps #define SIOP_SSTAT0_FCMP 0x40 /* Function Complete */ 355 1.1 mw #define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 356 1.1 mw #define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 357 1.1 mw #define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 358 1.1 mw #define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 359 1.1 mw #define SIOP_SSTAT0_RST 0x02 /* RST asserted */ 360 1.1 mw #define SIOP_SSTAT0_PAR 0x01 /* Parity Error */ 361 1.10 mhitch #else 362 1.10 mhitch #define SIOP_SSTAT0_ILF 0x80 /* SIDL lsb full */ 363 1.10 mhitch #define SIOP_SSTAT0_ORF 0x40 /* SODR lsb full */ 364 1.10 mhitch #define SIOP_SSTAT0_OLF 0x20 /* SODL lsb full */ 365 1.10 mhitch #define SIOP_SSTAT0_AIP 0x10 /* Arbitration in progress */ 366 1.10 mhitch #define SIOP_SSTAT0_LOA 0x08 /* Lost Arbitration */ 367 1.10 mhitch #define SIOP_SSTAT0_WOA 0x04 /* Won Arbitration */ 368 1.10 mhitch #define SIOP_SSTAT0_RST 0x02 /* SCSI RST/ signal */ 369 1.10 mhitch #define SIOP_SSTAT0_SDP0 0x01 /* SCSI SDP0/ parity signal */ 370 1.10 mhitch #endif 371 1.1 mw 372 1.1 mw /* Scsi status register 1 (sstat1) */ 373 1.1 mw 374 1.10 mhitch #ifndef ARCH_720 375 1.1 mw #define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 376 1.1 mw #define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 377 1.1 mw #define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 378 1.1 mw #define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 379 1.1 mw #define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 380 1.1 mw #define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 381 1.1 mw #define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 382 1.1 mw #define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 383 1.10 mhitch #else 384 1.10 mhitch #define SIOP_SSTAT1_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 385 1.10 mhitch #define SIOP_SSTAT1_SDP0 0x08 /* Latched (on REQ) SCSI Parity */ 386 1.10 mhitch #define SIOP_SSTAT1_MSG 0x04 /* Latched SCSI phase */ 387 1.10 mhitch #define SIOP_SSTAT1_CD 0x02 388 1.10 mhitch #define SIOP_SSTAT1_IO 0x01 389 1.10 mhitch #endif 390 1.1 mw 391 1.1 mw /* Scsi status register 2 (sstat2) */ 392 1.1 mw 393 1.10 mhitch #ifndef ARCH_720 394 1.1 mw #define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 395 1.1 mw # define SIOP_SCSI_FIFO_DEEP 8 396 1.1 mw #define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 397 1.1 mw #define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 398 1.1 mw #define SIOP_SSTAT2_CD 0x02 399 1.1 mw #define SIOP_SSTAT2_IO 0x01 400 1.10 mhitch #else 401 1.10 mhitch #define SIOP_SSTAT2_ILF1 0x80 /* SIDL msb full */ 402 1.10 mhitch #define SIOP_SSTAT2_ORF1 0x40 /* SODR msb full */ 403 1.10 mhitch #define SIOP_SSTAT2_OLF1 0x20 /* SODL msb full */ 404 1.10 mhitch #define SIOP_SSTAT2_FF4 0x10 /* FIFO flags bit 4 */ 405 1.10 mhitch #define SIOP_SSTAT2_SPL1 0x08 /* Latched Parity for SD15-8 */ 406 1.10 mhitch #define SIOP_SSTAT2_DIFF 0x04 /* DIFFSENSE Sense */ 407 1.10 mhitch #define SIOP_SSTAT2_LDSC 0x02 /* Last Disconnect */ 408 1.10 mhitch #define SIOP_SSTAT2_SDP1 0x01 /* SCSI SDP1 Parity */ 409 1.10 mhitch #endif 410 1.1 mw 411 1.1 mw /* Chip test register 0 (ctest0) */ 412 1.1 mw 413 1.10 mhitch #ifndef ARCH_720 414 1.6 chopps #define SIOP_CTEST0_RES0 0x80 415 1.6 chopps #define SIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ 416 1.6 chopps #define SIOP_CTEST0_GRP 0x20 /* Generate Receive Parity for Passthrough */ 417 1.6 chopps #define SIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ 418 1.6 chopps #define SIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ 419 1.6 chopps #define SIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ 420 1.6 chopps #define SIOP_CTEST0_RES1 0x02 421 1.1 mw #define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 422 1.10 mhitch #endif 423 1.1 mw 424 1.1 mw /* Chip test register 1 (ctest1) */ 425 1.1 mw 426 1.1 mw #define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */ 427 1.1 mw #define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 428 1.1 mw 429 1.1 mw /* Chip test register 2 (ctest2) */ 430 1.1 mw 431 1.10 mhitch #ifndef ARCH_720 432 1.6 chopps #define SIOP_CTEST2_RES 0x80 433 1.10 mhitch #else 434 1.10 mhitch #define SIOP_CTETS2_DDIR 0x80 /* Data Transfer Direction */ 435 1.10 mhitch #endif 436 1.6 chopps #define SIOP_CTEST2_SIGP 0x40 /* Signal process */ 437 1.10 mhitch #ifndef ARCH_720 438 1.1 mw #define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */ 439 1.1 mw #define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 440 1.10 mhitch #else 441 1.10 mhitch #define SIOP_CTEST2_RES5 0x20 442 1.10 mhitch #define SIOP_CTEST2_RES4 0x10 443 1.10 mhitch #endif 444 1.1 mw #define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 445 1.1 mw #define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 446 1.1 mw #define SIOP_CTEST2_DREQ 0x02 /* DREQ status */ 447 1.1 mw #define SIOP_CTEST2_DACK 0x01 /* DACK status */ 448 1.1 mw 449 1.1 mw /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 450 1.1 mw 451 1.10 mhitch #ifdef ARCH_720 452 1.10 mhitch #define SIOP_CTEST3_V 0xf0 /* Chip revision level */ 453 1.10 mhitch #define SIOP_CTEST3_FLF 0x08 /* Flush DMA FIFO */ 454 1.10 mhitch #define SIOP_CTEST3_CLF 0x04 /* Clear DMA FIFO */ 455 1.10 mhitch #define SIOP_CTEST3_FM 0x02 /* Fetch pin mode */ 456 1.10 mhitch #define SIOP_CTEST3_SM 0x01 /* Snoop pins mode */ 457 1.10 mhitch #endif 458 1.10 mhitch 459 1.1 mw /* Chip test register 4 (ctest4) */ 460 1.1 mw 461 1.6 chopps #define SIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ 462 1.1 mw #define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 463 1.1 mw #define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 464 1.10 mhitch #ifndef ARCH_720 465 1.16 andvar #define SIOP_CTEST4_SLBE 0x10 /* SCSI loopback enable */ 466 1.1 mw #define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 467 1.10 mhitch #else 468 1.10 mhitch #define SIOP_CTEST4_SRTM 0x10 /* Shadow Register Test Mode */ 469 1.11 tsutsui #define SIOP_CTEST4_EHPC 0x08 /* Enable Host Parity Check */ 470 1.10 mhitch #endif 471 1.1 mw #define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6) 472 1.1 mw 4->0, .. 7->3 */ 473 1.1 mw 474 1.1 mw /* Chip test register 5 (ctest5) */ 475 1.1 mw 476 1.1 mw #define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 477 1.1 mw #define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 478 1.10 mhitch #ifndef ARCH_720 479 1.1 mw #define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 480 1.10 mhitch #else 481 1.10 mhitch #define SIOP_CTEST5_RES 0x20 482 1.10 mhitch #endif 483 1.1 mw #define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */ 484 1.1 mw #define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 485 1.10 mhitch #ifndef ARCH_720 486 1.1 mw #define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 487 1.1 mw #define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 488 1.1 mw #define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 489 1.10 mhitch #else 490 1.10 mhitch #define SIOP_CTEST5_RAM 0x06 /* SCRIPTS RAM 1-0 */ 491 1.10 mhitch #define SIOP_CTEST5 RAMEN 0x01 /* RAM Base Address Enable */ 492 1.10 mhitch #endif 493 1.1 mw 494 1.1 mw /* Chip test register 6 (ctest6) DMA FIFO access */ 495 1.1 mw 496 1.1 mw /* Chip test register 7 (ctest7) */ 497 1.1 mw 498 1.10 mhitch #ifndef ARCH_720 499 1.6 chopps #define SIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ 500 1.6 chopps #define SIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ 501 1.15 msaitoh #define SIOP_CTEST7_SC0 0x20 /* Snoop control 0 */ 502 1.6 chopps #define SIOP_CTEST7_STD 0x10 /* Selection timeout disable */ 503 1.1 mw #define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 504 1.1 mw #define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 505 1.6 chopps #define SIOP_CTEST7_TT1 0x02 /* Transfer type bit */ 506 1.1 mw #define SIOP_CTEST7_DIFF 0x01 /* Differential mode */ 507 1.10 mhitch #endif 508 1.1 mw 509 1.1 mw /* DMA FIFO register (dfifo) */ 510 1.1 mw 511 1.6 chopps #define SIOP_DFIFO_RES 0x80 512 1.6 chopps #define SIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ 513 1.1 mw 514 1.1 mw /* Interrupt status register (istat) */ 515 1.1 mw 516 1.1 mw #define SIOP_ISTAT_ABRT 0x80 /* Abort operation */ 517 1.6 chopps #define SIOP_ISTAT_RST 0x40 /* Software reset */ 518 1.6 chopps #define SIOP_ISTAT_SIGP 0x20 /* Signal process */ 519 1.10 mhitch #ifndef ARCH_720 520 1.6 chopps #define SIOP_ISTAT_RES 0x10 521 1.10 mhitch #else 522 1.10 mhitch #define SIOP_ISTAT_SEM 0x10 /* Semaphore */ 523 1.10 mhitch #endif 524 1.1 mw #define SIOP_ISTAT_CON 0x08 /* Connected */ 525 1.10 mhitch #ifndef ARCH_720 526 1.6 chopps #define SIOP_ISTAT_RES1 0x04 527 1.10 mhitch #else 528 1.10 mhitch #define SIOP_ISTAT_INTF 0x04 /* Interrupt on the Fly */ 529 1.10 mhitch #endif 530 1.1 mw #define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 531 1.1 mw #define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 532 1.1 mw 533 1.8 veego /* Chip test register 8 (ctest8) */ 534 1.6 chopps 535 1.6 chopps #define SIOP_CTEST8_V 0xf0 /* Chip revision level */ 536 1.6 chopps #define SIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ 537 1.6 chopps #define SIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ 538 1.6 chopps #define SIOP_CTEST8_FM 0x02 /* Fetch pin mode */ 539 1.6 chopps #define SIOP_CTEST8_SM 0x01 /* Snoop pins mode */ 540 1.1 mw 541 1.1 mw /* DMA Mode register (dmode) */ 542 1.1 mw 543 1.1 mw #define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 544 1.6 chopps #define SIOP_DMODE_FC 0x30 /* Function code */ 545 1.6 chopps #define SIOP_DMODE_PD 0x08 /* Program/data */ 546 1.6 chopps #define SIOP_DMODE_FAM 0x04 /* Fixed address mode */ 547 1.6 chopps #define SIOP_DMODE_U0 0x02 /* User programmable transfer type */ 548 1.6 chopps #define SIOP_DMODE_MAN 0x01 /* Manual start mode */ 549 1.1 mw 550 1.1 mw /* DMA interrupt enable register (dien) */ 551 1.1 mw 552 1.6 chopps #define SIOP_DIEN_RES 0xc0 553 1.10 mhitch #ifdef ARCH_720 554 1.10 mhitch #define SIOP_DIEN_HPED 0x40 /* Host Parity */ 555 1.10 mhitch #endif 556 1.6 chopps #define SIOP_DIEN_BF 0x20 /* On Bus Fault */ 557 1.1 mw #define SIOP_DIEN_ABRT 0x10 /* On Abort */ 558 1.1 mw #define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 559 1.1 mw #define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 560 1.1 mw #define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 561 1.6 chopps #define SIOP_DIEN_IID 0x01 /* On illegal instruction detected */ 562 1.1 mw 563 1.1 mw /* DMA control register (dcntl) */ 564 1.1 mw 565 1.10 mhitch #ifndef ARCH_720 566 1.1 mw #define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: 567 1.14 lukem 0 --> 37.51..50.00 MHz, div=2 568 1.14 lukem 1 --> 25.01..37.50 MHz, div=1.5 569 1.14 lukem 2 --> 16.67..25.00 MHz, div=1 570 1.14 lukem 3 --> 50.01..66.67 MHz, div=3 571 1.1 mw */ 572 1.10 mhitch #else 573 1.10 mhitch #define SIOP_DCNTL_STE 0x80 /* Size Throttle Enable */ 574 1.10 mhitch #define SIOP_DCNTL_BSM 0x40 /* Bus Mode */ 575 1.10 mhitch #endif 576 1.6 chopps #define SIOP_DCNTL_EA 0x20 /* Enable ack */ 577 1.1 mw #define SIOP_DCNTL_SSM 0x10 /* Single step mode */ 578 1.10 mhitch #ifndef ARCH_720 579 1.6 chopps #define SIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ 580 1.10 mhitch #else 581 1.10 mhitch #define SIOP_DCNTL_BW16 0x8 /* Bus Width 16 */ 582 1.10 mhitch #endif 583 1.6 chopps #define SIOP_DCNTL_STD 0x04 /* Start DMA operation */ 584 1.6 chopps #define SIOP_DCNTL_FA 0x02 /* Fast arbitration */ 585 1.6 chopps #define SIOP_DCNTL_COM 0x01 /* 53C700 compatibility */ 586
Indexes created Mon Sep 22 13:09:51 GMT 2025