siopreg.h revision 1.1
1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)scsireg.h 7.3 (Berkeley) 2/5/91 37 */ 38 39 /* 40 * NCR 53C710 SCSI interface hardware description. 41 * 42 */ 43 44 typedef struct { 45 volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */ 46 volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 47 volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 48 volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 49 volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 50 volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */ 51 volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 52 volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 53 volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 54 volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */ 55 volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */ 56 volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 57 volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 58 volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 59 volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 60 volatile unsigned char siop_dstat; /* ro: DMA status */ 61 volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 62 volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 63 volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 64 volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 65 volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 66 volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */ 67 volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 68 volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 69 volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 70 volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 71 volatile unsigned char siop_lcrc; /* rw: LCRC value */ 72 volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */ 73 volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 74 volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 75 volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 76 volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 77 volatile unsigned char siop_dbc1; 78 volatile unsigned char siop_dbc0; 79 volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 80 volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 81 volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 82 volatile unsigned long siop_scratch; /* rw: Scratch Register */ 83 volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 84 volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 85 volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 86 volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 87 volatile unsigned long siop_addr; 88 89 } siop_regmap_t; 90 91 /* 92 * Register defines 93 */ 94 95 /* Scsi control register 0 (scntl0) */ 96 97 #define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 98 # define SIOP_ARB_SIMPLE 0x00 99 # define SIOP_ARB_FULL 0xc0 100 #define SIOP_SCNTL0_START 0x20 /* Start Sequence */ 101 #define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 102 #define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 103 #define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 104 #define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 105 #define SIOP_SCNTL0_TRG 0x01 /* Target Mode */ 106 107 /* Scsi control register 1 (scntl1) */ 108 109 #define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 110 #define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 111 #define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 112 #define SIOP_SCNTL1_CON 0x10 /* Connected */ 113 #define SIOP_SCNTL1_RST 0x08 /* Assert RST */ 114 #define SIOP_SCNTL1_PAR 0x04 /* Force bad Parity */ 115 #define SIOP_SCNTL1_SND 0x02 /* Start Send operation */ 116 #define SIOP_SCNTL1_RCV 0x01 /* Start Receive operation */ 117 118 /* Scsi interrupt enable register (sien) */ 119 120 #define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 121 #define SIOP_SIEN_FC 0x40 /* Function Complete */ 122 #define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 123 #define SIOP_SIEN_SEL 0x10 /* (Re)Selected */ 124 #define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 125 #define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 126 #define SIOP_SIEN_RST 0x02 /* RST asserted */ 127 #define SIOP_SIEN_PAR 0x01 /* Parity Error */ 128 129 /* Scsi chip ID (scid) */ 130 131 #define SIOP_SCID_VALUE(i) (1<<i) 132 133 /* Scsi transfer register (sxfer) */ 134 135 #define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */ 136 #define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 137 /* see specs for formulas: 138 Period = TCP * (4 + XFERP ) 139 TCP = 1 + CLK + 1..2; 140 */ 141 #define SIOP_SXFER_MO 0x0f /* Synch Max Offset */ 142 # define SIOP_MAX_OFFSET 8 143 144 /* Scsi output data latch register (sodl) */ 145 146 /* Scsi output control latch register (socl) */ 147 148 #define SIOP_REQ 0x80 /* SCSI signal <x> asserted */ 149 #define SIOP_ACK 0x40 150 #define SIOP_BSY 0x20 151 #define SIOP_SEL 0x10 152 #define SIOP_ATN 0x08 153 #define SIOP_MSG 0x04 154 #define SIOP_CD 0x02 155 #define SIOP_IO 0x01 156 157 #define SIOP_PHASE(socl) SCSI_PHASE(socl) 158 159 /* Scsi first byte received register (sfbr) */ 160 161 /* Scsi input data latch register (sidl) */ 162 163 /* Scsi bus data lines register (sbdl) */ 164 165 /* Scsi bus control lines register (sbcl). Same as socl */ 166 167 /* DMA status register (dstat) */ 168 169 #define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 170 #define SIOP_DSTAT_RES 0x60 171 #define SIOP_DSTAT_ABRT 0x10 /* Aborted */ 172 #define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 173 #define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 174 #define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 175 #define SIOP_DSTAT_OPC 0x01 /* Invalid SCRIPTS Opcode */ 176 177 /* Scsi status register 0 (sstat0) */ 178 179 #define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 180 #define SIOP_SSTAT0_FC 0x40 /* Function Complete */ 181 #define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 182 #define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 183 #define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 184 #define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 185 #define SIOP_SSTAT0_RST 0x02 /* RST asserted */ 186 #define SIOP_SSTAT0_PAR 0x01 /* Parity Error */ 187 188 /* Scsi status register 1 (sstat1) */ 189 190 #define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 191 #define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 192 #define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 193 #define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 194 #define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 195 #define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 196 #define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 197 #define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 198 199 /* Scsi status register 2 (sstat2) */ 200 201 #define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 202 # define SIOP_SCSI_FIFO_DEEP 8 203 #define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 204 #define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 205 #define SIOP_SSTAT2_CD 0x02 206 #define SIOP_SSTAT2_IO 0x01 207 208 /* Chip test register 0 (ctest0) */ 209 210 #define SIOP_CTEST0_RES 0xfc 211 #define SIOP_CTEST0_RTRG 0x02 /* Real Target mode */ 212 #define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 213 214 /* Chip test register 1 (ctest1) */ 215 216 #define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */ 217 #define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 218 219 /* Chip test register 2 (ctest2) */ 220 221 #define SIOP_CTEST2_RES 0xc0 222 #define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */ 223 #define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 224 #define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 225 #define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 226 #define SIOP_CTEST2_DREQ 0x02 /* DREQ status */ 227 #define SIOP_CTEST2_DACK 0x01 /* DACK status */ 228 229 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 230 231 /* Chip test register 4 (ctest4) */ 232 233 #define SIOP_CTEST4_RES 0x80 234 #define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 235 #define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 236 #define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 237 #define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 238 #define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6) 239 4->0, .. 7->3 */ 240 241 /* Chip test register 5 (ctest5) */ 242 243 #define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 244 #define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 245 #define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 246 #define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */ 247 #define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 248 #define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 249 #define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 250 #define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 251 252 /* Chip test register 6 (ctest6) DMA FIFO access */ 253 254 /* Chip test register 7 (ctest7) */ 255 256 #define SIOP_CTEST7_RES 0xe0 257 #define SIOP_CTEST7_STD 0x10 /* Disable selection timeout */ 258 #define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 259 #define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 260 #define SIOP_CTEST7_DC 0x02 /* Drive DC pin low on SCRIPT fetches */ 261 #define SIOP_CTEST7_DIFF 0x01 /* Differential mode */ 262 263 /* DMA FIFO register (dfifo) */ 264 265 #define SIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ 266 #define SIOP_DFIFO_CLF 0x40 /* Clear DMA and SCSI FIFOs */ 267 #define SIOP_DFIFO_BO 0x3f /* FIFO byte offset counter */ 268 269 /* Interrupt status register (istat) */ 270 271 #define SIOP_ISTAT_ABRT 0x80 /* Abort operation */ 272 #define SIOP_ISTAT_RES 0x70 273 #define SIOP_ISTAT_CON 0x08 /* Connected */ 274 #define SIOP_ISTAT_PRE 0x04 /* Pointer register empty */ 275 #define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 276 #define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 277 278 279 /* DMA Mode register (dmode) */ 280 281 #define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 282 #define SIOP_DMODE_BW16 0x20 /* Bus Width is 16 bits */ 283 #define SIOP_DMODE_286 0x10 /* 286 mode */ 284 #define SIOP_DMODE_IO_M 0x08 /* xfer data to memory or I/O space */ 285 #define SIOP_DMODE_FAM 0x04 /* fixed address mode */ 286 #define SIOP_DMODE_PIPE 0x02 /* SCRIPTS in Pipeline mode */ 287 #define SIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ 288 289 /* DMA interrupt enable register (dien) */ 290 291 #define SIOP_DIEN_RES 0xe0 292 #define SIOP_DIEN_ABRT 0x10 /* On Abort */ 293 #define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 294 #define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 295 #define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 296 #define SIOP_DIEN_OPC 0x01 /* On SCRIPTS illegal opcode */ 297 298 /* DMA control register (dcntl) */ 299 300 #define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: 301 0 --> 37.51..50.00 Mhz, div=2 302 1 --> 25.01..37.50 Mhz, div=1.5 303 2 --> 16.67..25.00 Mhz, div=1 304 3 --> reserved 305 */ 306 #define SIOP_DCNTL_S16 0x20 /* SCRIPTS fetches 16bits at a time */ 307 #define SIOP_DCNTL_SSM 0x10 /* Single step mode */ 308 #define SIOP_DCNTL_LLM 0x08 /* Enable Low-level mode */ 309 #define SIOP_DCNTL_STD 0x04 /* Start SCRIPTS operation */ 310 #define SIOP_DCNTL_RES 0x02 311 #define SIOP_DCNTL_RST 0x01 /* Software reset */ 312 313 /* psns/pctl phase lines as bits */ 314 #define PHASE_MSG 0x04 315 #define PHASE_CD 0x02 /* =1 if 'command' */ 316 #define PHASE_IO 0x01 /* =1 if data inbound */ 317 /* Phase lines as values */ 318 #define PHASE 0x07 /* mask for psns/pctl phase */ 319 #define DATA_OUT_PHASE 0x00 320 #define DATA_IN_PHASE 0x01 321 #define CMD_PHASE 0x02 322 #define STATUS_PHASE 0x03 323 #define BUS_FREE_PHASE 0x04 324 #define ARB_SEL_PHASE 0x05 /* Fuji chip combines arbitration with sel. */ 325 #define MESG_OUT_PHASE 0x06 326 #define MESG_IN_PHASE 0x07 327 328 /* SCSI Messages */ 329 330 #define MSG_CMD_COMPLETE 0x00 331 #define MSG_EXT_MESSAGE 0x01 332 #define MSG_SAVE_DATA_PTR 0x02 333 #define MSG_RESTORE_PTR 0x03 334 #define MSG_DISCONNECT 0x04 335 #define MSG_INIT_DETECT_ERROR 0x05 336 #define MSG_ABORT 0x06 337 #define MSG_REJECT 0x07 338 #define MSG_NOOP 0x08 339 #define MSG_PARITY_ERROR 0x09 340 #define MSG_BUS_DEVICE_RESET 0x0C 341 #define MSG_IDENTIFY 0x80 342 #define MSG_IDENTIFY_DR 0xc0 /* (disconnect/reconnect allowed) */ 343 #define MSG_SYNC_REQ 0x01 344 345 /* SCSI Commands */ 346 347 #define CMD_TEST_UNIT_READY 0x00 348 #define CMD_REQUEST_SENSE 0x03 349 #define CMD_INQUIRY 0x12 350 #define CMD_SEND_DIAGNOSTIC 0x1D 351 352 #define CMD_REWIND 0x01 353 #define CMD_FORMAT_UNIT 0x04 354 #define CMD_READ_BLOCK_LIMITS 0x05 355 #define CMD_REASSIGN_BLOCKS 0x07 356 #define CMD_READ 0x08 357 #define CMD_WRITE 0x0A 358 #define CMD_WRITE_FILEMARK 0x10 359 #define CMD_SPACE 0x11 360 #define CMD_MODE_SELECT 0x15 361 #define CMD_RELEASE_UNIT 0x17 362 #define CMD_ERASE 0x19 363 #define CMD_MODE_SENSE 0x1A 364 #define CMD_LOADUNLOAD 0x1B 365 #define CMD_RECEIVE_DIAG 0x1C 366 #define CMD_SEND_DIAG 0x1D 367 #define CMD_P_A_MEDIA_REMOVAL 0x1E 368 #define CMD_READ_CAPACITY 0x25 369 #define CMD_READ_EXT 0x28 370 #define CMD_WRITE_EXT 0x2A 371 #define CMD_READ_DEFECT_DATA 0x37 372 #define SD_MANUFAC_DEFECTS 0x14000000 373 #define SD_GROWN_DEFECTS 0x0c000000 374 #define CMD_READ_BUFFER 0x3B 375 #define CMD_WRITE_BUFFER 0x3C 376 #define CMD_READ_FULL 0xF0 377 #define CMD_MEDIA_TEST 0xF1 378 #define CMD_ACCESS_LOG 0xF2 379 #define CMD_WRITE_FULL 0xFC 380 #define CMD_MANAGE_PRIMARY 0xFD 381 #define CMD_EXECUTE_DATA 0xFE 382 383 /* SCSI status bits */ 384 385 #define STS_CHECKCOND 0x02 /* Check Condition (ie., read sense) */ 386 #define STS_CONDMET 0x04 /* Condition Met (ie., search worked) */ 387 #define STS_BUSY 0x08 388 #define STS_INTERMED 0x10 /* Intermediate status sent */ 389 #define STS_EXT 0x80 /* Extended status valid */ 390 391 /* command descriptor blocks */ 392 393 struct scsi_cdb6 { 394 u_char cmd; /* command code */ 395 u_char lun: 3, /* logical unit on ctlr */ 396 lbah: 5; /* msb of read/write logical block addr */ 397 u_char lbam; /* middle byte of l.b.a. */ 398 u_char lbal; /* lsb of l.b.a. */ 399 u_char len; /* transfer length */ 400 u_char xtra; 401 }; 402 403 struct scsi_cdb10 { 404 u_char cmd; /* command code */ 405 u_char lun: 3, /* logical unit on ctlr */ 406 : 4, 407 rel: 1; /* l.b.a. is relative addr if =1 */ 408 u_char lbah; /* msb of read/write logical block addr */ 409 u_char lbahm; /* high middle byte of l.b.a. */ 410 u_char lbalm; /* low middle byte of l.b.a. */ 411 u_char lbal; /* lsb of l.b.a. */ 412 u_char reserved; 413 u_char lenh; /* msb transfer length */ 414 u_char lenl; /* lsb transfer length */ 415 u_char xtra; 416 }; 417 418 /* basic sense data */ 419 420 struct scsi_sense { 421 u_char valid: 1, /* l.b.a. is valid */ 422 class: 3, 423 code: 4; 424 u_char vu: 4, /* vendor unique */ 425 lbah: 4; 426 u_char lbam; 427 u_char lbal; 428 }; 429 430 struct scsi_xsense { 431 u_char valid: 1, /* l.b.a. is valid */ 432 class: 3, 433 code: 4; 434 u_char segment; 435 u_char filemark: 1, 436 eom: 1, 437 ili: 1, /* illegal length indicator */ 438 rsvd: 1, 439 key: 4; 440 u_char info1; 441 u_char info2; 442 u_char info3; 443 u_char info4; 444 u_char len; /* additional sense length */ 445 }; 446 447 /* inquiry data */ 448 struct scsi_inquiry { 449 u_char type; 450 u_char qual; 451 u_char version; 452 u_char rsvd; 453 u_char len; 454 char class[3]; 455 char vendor_id[8]; 456 char product_id[16]; 457 char rev[4]; 458 }; 459 460 struct scsi_format_parms { /* physical BFI format */ 461 u_short reserved; 462 u_short list_len; 463 struct defect { 464 unsigned cyl : 24; 465 unsigned head : 8; 466 long bytes_from_index; 467 } defect[127]; 468 } format_parms; 469 470 struct scsi_reassign_parms { 471 u_short reserved; 472 u_short list_len; /* length in bytes of defects only */ 473 struct new_defect { 474 unsigned lba; /* logical block address */ 475 } new_defect[2]; 476 } reassign_parms; 477 478 struct scsi_modesel_hdr { 479 u_char rsvd1; 480 u_char media_type; 481 u_char rsvd2; 482 u_char block_desc_len; 483 u_int density : 8; 484 u_int number_blocks :24; 485 u_int rsvd3 : 8; 486 u_int block_length :24; 487 }; 488 489 struct scsi_modesense_hdr { 490 u_char len; 491 u_char media_type; 492 u_char wp : 1; 493 u_char rsvd1 : 7; 494 u_char block_desc_len; 495 u_int density : 8; 496 u_int number_blocks :24; 497 u_int rsvd2 : 8; 498 u_int block_length :24; 499 }; 500 501 /* 502 * Mode Select / Mode sense "pages" 503 */ 504 505 /* 506 * Page One - Error Recovery Parameters 507 */ 508 struct scsi_err_recovery { 509 u_char page_savable : 1; /* save parameters */ 510 u_char reserved : 1; 511 u_char page_code : 6; /* = 0x01 */ 512 u_char page_length; /* = 6 */ 513 u_char awre : 1; /* auto write realloc enabled */ 514 u_char arre : 1; /* auto read realloc enabled */ 515 u_char tb : 1; /* transfer block */ 516 u_char rc : 1; /* read continuous */ 517 u_char eec : 1; /* enable early correction */ 518 u_char per : 1; /* post error */ 519 u_char dte : 1; /* disable transfer on error */ 520 u_char dcr : 1; /* disable correction */ 521 u_char retry_count; 522 u_char correction_span; 523 u_char head_offset_count; 524 u_char strobe_offset_count; 525 u_char recovery_time_limit; 526 }; 527 528 /* 529 * Page Two - Disconnect / Reconnect Control Parameters 530 */ 531 struct scsi_disco_reco { 532 u_char page_savable : 1; /* save parameters */ 533 u_char rsvd : 1; 534 u_char page_code : 6; /* = 0x02 */ 535 u_char page_length; /* = 10 */ 536 u_char buffer_full_ratio; /* write, how full before reconnect? */ 537 u_char buffer_empty_ratio; /* read, how full before reconnect? */ 538 539 u_short bus_inactivity_limit; /* how much bus time for busy */ 540 u_short disconnect_time_limit; /* min to remain disconnected */ 541 u_short connect_time_limit; /* min to remain connected */ 542 u_short reserved_1; 543 }; 544 545 /* 546 * Page Three - Direct Access Device Format Parameters 547 */ 548 struct scsi_format { 549 u_char page_savable : 1; /* save parameters */ 550 u_char rsvd : 1; 551 u_char page_code : 6; /* = 0x03 */ 552 u_char page_length; /* = 22 */ 553 u_short tracks_per_zone; /* Handling of Defects Fields */ 554 u_short alt_sect_zone; 555 u_short alt_tracks_zone; 556 u_short alt_tracks_vol; 557 u_short sect_track; /* Track Format Field */ 558 u_short data_sect; /* Sector Format Fields */ 559 u_short interleave; 560 u_short track_skew_factor; 561 u_short cyl_skew_factor; 562 u_char ssec : 1; /* Drive Type Field */ 563 u_char hsec : 1; 564 u_char rmb : 1; 565 u_char surf : 1; 566 u_char ins : 1; 567 u_char reserved_1 : 3; 568 u_char reserved_2; 569 u_char reserved_3; 570 u_char reserved_4; 571 }; 572 573 /* 574 * Page Four - Rigid Disk Drive Geometry Parameters 575 */ 576 struct scsi_geometry { 577 u_char page_savable : 1; /* save parameters */ 578 u_char rsvd : 1; 579 u_char page_code : 6; /* = 0x04 */ 580 u_char page_length; /* = 18 */ 581 u_char cyl_ub; /* number of cylinders */ 582 u_char cyl_mb; 583 u_char cyl_lb; 584 u_char heads; /* number of heads */ 585 u_char precomp_cyl_ub; /* cylinder to start precomp */ 586 u_char precomp_cyl_mb; 587 u_char precomp_cyl_lb; 588 u_char current_cyl_ub; /* cyl to start reduced current */ 589 u_char current_cyl_mb; 590 u_char current_cyl_lb; 591 u_short step_rate; /* drive step rate */ 592 u_char landing_cyl_ub; /* landing zone cylinder */ 593 u_char landing_cyl_mb; 594 u_char landing_cyl_lb; 595 u_char reserved_1; 596 u_char reserved_2; 597 u_char reserved_3; 598 }; 599 600 /* 601 * Page 0x38 - Cache Control Parameters 602 */ 603 struct scsi_cache { 604 u_char page_savable : 1; /* save parameters */ 605 u_char rsvd : 1; 606 u_char page_code : 6; /* = 0x38 */ 607 u_char page_length; /* = 14 */ 608 u_char rsvd_1 : 1; 609 u_char wie : 1; /* write index enable */ 610 u_char rsvd_2 : 1; 611 u_char ce : 1; /* cache enable */ 612 u_char table_size : 4; 613 u_char prefetch_threshold; 614 u_char maximum_threshold; 615 u_char maximumprefetch_multiplier; 616 u_char minimum_threshold; 617 u_char minimum_prefetch_multiplier; 618 u_char reserved[8]; 619 }; 620 621 /* 622 * Driver ioctl's for various scsi operations. 623 */ 624 #ifndef _IOCTL_ 625 #include "ioctl.h" 626 #endif 627 628 /* 629 * Control for SCSI "format" mode. 630 * 631 * "Format" mode allows a privileged process to issue direct SCSI 632 * commands to a drive (it is intended primarily to allow on-line 633 * formatting). SDIOCSFORMAT with a non-zero arg will put the drive 634 * into format mode; a zero arg will take it out. When in format 635 * mode, only the process that issued the SDIOCFORMAT can read or 636 * write the drive. 637 * 638 * In format mode, process is expected to 639 * - do SDIOCSCSICOMMAND to supply cdb for next SCSI op 640 * - do read or write as appropriate for cdb 641 * - if i/o error, optionally do SDIOCSENSE to get completion 642 * status and sense data from last scsi operation. 643 */ 644 645 struct scsi_fmt_cdb { 646 int len; /* cdb length (in bytes) */ 647 u_char cdb[28]; /* cdb to use on next read/write */ 648 }; 649 650 struct scsi_fmt_sense { 651 u_int status; /* completion status of last op */ 652 u_char sense[28]; /* sense data (if any) from last op */ 653 }; 654 655 #define SDIOCSFORMAT _IOW('S', 0x1, int) 656 #define SDIOCGFORMAT _IOR('S', 0x2, int) 657 #define SDIOCSCSICOMMAND _IOW('S', 0x3, struct scsi_fmt_cdb) 658 #define SDIOCSENSE _IOR('S', 0x4, struct scsi_fmt_sense) 659 660 extern void siopreset (int unit); 661 extern void siopstart (int unit); 662 extern int siopgo (int ctlr, int slave, int unit, struct buf *bp, struct scsi_fmt_cdb *cdb, int pad); 663 extern void siopdone (int unit); 664 #if 0 665 extern int siopintr2 (int unit); 666 #else 667 extern int siopintr2 (void); 668 #endif 669
Indexes created Sun Sep 28 16:09:52 GMT 2025