siopreg.h revision 1.2
1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 37 */ 38 39 /* 40 * NCR 53C710 SCSI interface hardware description. 41 * 42 * Using parts of the Mach scsi driver for the 53C700 43 */ 44 45 typedef struct { 46 volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */ 47 volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 48 volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 49 volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 50 volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 51 volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */ 52 volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 53 volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 54 volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 55 volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */ 56 volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */ 57 volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 58 volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 59 volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 60 volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 61 volatile unsigned char siop_dstat; /* ro: DMA status */ 62 volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 63 volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 64 volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 65 volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 66 volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 67 volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */ 68 volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 69 volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 70 volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 71 volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 72 volatile unsigned char siop_lcrc; /* rw: LCRC value */ 73 volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */ 74 volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 75 volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 76 volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 77 volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 78 volatile unsigned char siop_dbc1; 79 volatile unsigned char siop_dbc0; 80 volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 81 volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 82 volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 83 volatile unsigned long siop_scratch; /* rw: Scratch Register */ 84 volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 85 volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 86 volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 87 volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 88 volatile unsigned long siop_addr; 89 90 } siop_regmap_t; 91 92 /* 93 * Register defines 94 */ 95 96 /* Scsi control register 0 (scntl0) */ 97 98 #define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 99 # define SIOP_ARB_SIMPLE 0x00 100 # define SIOP_ARB_FULL 0xc0 101 #define SIOP_SCNTL0_START 0x20 /* Start Sequence */ 102 #define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 103 #define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 104 #define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 105 #define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 106 #define SIOP_SCNTL0_TRG 0x01 /* Target Mode */ 107 108 /* Scsi control register 1 (scntl1) */ 109 110 #define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 111 #define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 112 #define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 113 #define SIOP_SCNTL1_CON 0x10 /* Connected */ 114 #define SIOP_SCNTL1_RST 0x08 /* Assert RST */ 115 #define SIOP_SCNTL1_PAR 0x04 /* Force bad Parity */ 116 #define SIOP_SCNTL1_SND 0x02 /* Start Send operation */ 117 #define SIOP_SCNTL1_RCV 0x01 /* Start Receive operation */ 118 119 /* Scsi interrupt enable register (sien) */ 120 121 #define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 122 #define SIOP_SIEN_FC 0x40 /* Function Complete */ 123 #define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 124 #define SIOP_SIEN_SEL 0x10 /* (Re)Selected */ 125 #define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 126 #define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 127 #define SIOP_SIEN_RST 0x02 /* RST asserted */ 128 #define SIOP_SIEN_PAR 0x01 /* Parity Error */ 129 130 /* Scsi chip ID (scid) */ 131 132 #define SIOP_SCID_VALUE(i) (1<<i) 133 134 /* Scsi transfer register (sxfer) */ 135 136 #define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */ 137 #define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 138 /* see specs for formulas: 139 Period = TCP * (4 + XFERP ) 140 TCP = 1 + CLK + 1..2; 141 */ 142 #define SIOP_SXFER_MO 0x0f /* Synch Max Offset */ 143 # define SIOP_MAX_OFFSET 8 144 145 /* Scsi output data latch register (sodl) */ 146 147 /* Scsi output control latch register (socl) */ 148 149 #define SIOP_REQ 0x80 /* SCSI signal <x> asserted */ 150 #define SIOP_ACK 0x40 151 #define SIOP_BSY 0x20 152 #define SIOP_SEL 0x10 153 #define SIOP_ATN 0x08 154 #define SIOP_MSG 0x04 155 #define SIOP_CD 0x02 156 #define SIOP_IO 0x01 157 158 #define SIOP_PHASE(socl) SCSI_PHASE(socl) 159 160 /* Scsi first byte received register (sfbr) */ 161 162 /* Scsi input data latch register (sidl) */ 163 164 /* Scsi bus data lines register (sbdl) */ 165 166 /* Scsi bus control lines register (sbcl). Same as socl */ 167 168 /* DMA status register (dstat) */ 169 170 #define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 171 #define SIOP_DSTAT_RES 0x60 172 #define SIOP_DSTAT_ABRT 0x10 /* Aborted */ 173 #define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 174 #define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 175 #define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 176 #define SIOP_DSTAT_OPC 0x01 /* Invalid SCRIPTS Opcode */ 177 178 /* Scsi status register 0 (sstat0) */ 179 180 #define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 181 #define SIOP_SSTAT0_FC 0x40 /* Function Complete */ 182 #define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 183 #define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 184 #define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 185 #define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 186 #define SIOP_SSTAT0_RST 0x02 /* RST asserted */ 187 #define SIOP_SSTAT0_PAR 0x01 /* Parity Error */ 188 189 /* Scsi status register 1 (sstat1) */ 190 191 #define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 192 #define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 193 #define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 194 #define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 195 #define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 196 #define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 197 #define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 198 #define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 199 200 /* Scsi status register 2 (sstat2) */ 201 202 #define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 203 # define SIOP_SCSI_FIFO_DEEP 8 204 #define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 205 #define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 206 #define SIOP_SSTAT2_CD 0x02 207 #define SIOP_SSTAT2_IO 0x01 208 209 /* Chip test register 0 (ctest0) */ 210 211 #define SIOP_CTEST0_RES 0xfc 212 #define SIOP_CTEST0_RTRG 0x02 /* Real Target mode */ 213 #define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 214 215 /* Chip test register 1 (ctest1) */ 216 217 #define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */ 218 #define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 219 220 /* Chip test register 2 (ctest2) */ 221 222 #define SIOP_CTEST2_RES 0xc0 223 #define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */ 224 #define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 225 #define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 226 #define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 227 #define SIOP_CTEST2_DREQ 0x02 /* DREQ status */ 228 #define SIOP_CTEST2_DACK 0x01 /* DACK status */ 229 230 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 231 232 /* Chip test register 4 (ctest4) */ 233 234 #define SIOP_CTEST4_RES 0x80 235 #define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 236 #define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 237 #define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 238 #define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 239 #define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6) 240 4->0, .. 7->3 */ 241 242 /* Chip test register 5 (ctest5) */ 243 244 #define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 245 #define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 246 #define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 247 #define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */ 248 #define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 249 #define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 250 #define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 251 #define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 252 253 /* Chip test register 6 (ctest6) DMA FIFO access */ 254 255 /* Chip test register 7 (ctest7) */ 256 257 #define SIOP_CTEST7_RES 0xe0 258 #define SIOP_CTEST7_STD 0x10 /* Disable selection timeout */ 259 #define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 260 #define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 261 #define SIOP_CTEST7_DC 0x02 /* Drive DC pin low on SCRIPT fetches */ 262 #define SIOP_CTEST7_DIFF 0x01 /* Differential mode */ 263 264 /* DMA FIFO register (dfifo) */ 265 266 #define SIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ 267 #define SIOP_DFIFO_CLF 0x40 /* Clear DMA and SCSI FIFOs */ 268 #define SIOP_DFIFO_BO 0x3f /* FIFO byte offset counter */ 269 270 /* Interrupt status register (istat) */ 271 272 #define SIOP_ISTAT_ABRT 0x80 /* Abort operation */ 273 #define SIOP_ISTAT_RES 0x70 274 #define SIOP_ISTAT_CON 0x08 /* Connected */ 275 #define SIOP_ISTAT_PRE 0x04 /* Pointer register empty */ 276 #define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 277 #define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 278 279 280 /* DMA Mode register (dmode) */ 281 282 #define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 283 #define SIOP_DMODE_BW16 0x20 /* Bus Width is 16 bits */ 284 #define SIOP_DMODE_286 0x10 /* 286 mode */ 285 #define SIOP_DMODE_IO_M 0x08 /* xfer data to memory or I/O space */ 286 #define SIOP_DMODE_FAM 0x04 /* fixed address mode */ 287 #define SIOP_DMODE_PIPE 0x02 /* SCRIPTS in Pipeline mode */ 288 #define SIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ 289 290 /* DMA interrupt enable register (dien) */ 291 292 #define SIOP_DIEN_RES 0xe0 293 #define SIOP_DIEN_ABRT 0x10 /* On Abort */ 294 #define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 295 #define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 296 #define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 297 #define SIOP_DIEN_OPC 0x01 /* On SCRIPTS illegal opcode */ 298 299 /* DMA control register (dcntl) */ 300 301 #define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: 302 0 --> 37.51..50.00 Mhz, div=2 303 1 --> 25.01..37.50 Mhz, div=1.5 304 2 --> 16.67..25.00 Mhz, div=1 305 3 --> reserved 306 */ 307 #define SIOP_DCNTL_S16 0x20 /* SCRIPTS fetches 16bits at a time */ 308 #define SIOP_DCNTL_SSM 0x10 /* Single step mode */ 309 #define SIOP_DCNTL_LLM 0x08 /* Enable Low-level mode */ 310 #define SIOP_DCNTL_STD 0x04 /* Start SCRIPTS operation */ 311 #define SIOP_DCNTL_RES 0x02 312 #define SIOP_DCNTL_RST 0x01 /* Software reset */ 313
Indexes created Sat Sep 27 22:09:54 GMT 2025