siopreg.h revision 1.4
1 /* 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Van Jacobson of Lawrence Berkeley Laboratory. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 37 * $Id: siopreg.h,v 1.4 1994/05/12 05:57:24 chopps Exp $ 38 */ 39 40 /* 41 * NCR 53C710 SCSI interface hardware description. 42 * 43 * Using parts of the Mach scsi driver for the 53C700 44 */ 45 46 typedef struct { 47 volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */ 48 volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 49 volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 50 volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 51 volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 52 volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */ 53 volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 54 volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 55 volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 56 volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */ 57 volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */ 58 volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 59 volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 60 volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 61 volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 62 volatile unsigned char siop_dstat; /* ro: DMA status */ 63 volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 64 volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 65 volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 66 volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 67 volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 68 volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */ 69 volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 70 volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 71 volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 72 volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 73 volatile unsigned char siop_lcrc; /* rw: LCRC value */ 74 volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */ 75 volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 76 volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 77 volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 78 volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 79 volatile unsigned char siop_dbc1; 80 volatile unsigned char siop_dbc0; 81 volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 82 volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 83 volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 84 volatile unsigned long siop_scratch; /* rw: Scratch Register */ 85 volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 86 volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 87 volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 88 volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 89 volatile unsigned long siop_addr; 90 91 } siop_regmap_t; 92 typedef volatile siop_regmap_t *siop_regmap_p; 93 94 /* 95 * Register defines 96 */ 97 98 /* Scsi control register 0 (scntl0) */ 99 100 #define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 101 # define SIOP_ARB_SIMPLE 0x00 102 # define SIOP_ARB_FULL 0xc0 103 #define SIOP_SCNTL0_START 0x20 /* Start Sequence */ 104 #define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 105 #define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 106 #define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 107 #define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 108 #define SIOP_SCNTL0_TRG 0x01 /* Target Mode */ 109 110 /* Scsi control register 1 (scntl1) */ 111 112 #define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 113 #define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 114 #define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 115 #define SIOP_SCNTL1_CON 0x10 /* Connected */ 116 #define SIOP_SCNTL1_RST 0x08 /* Assert RST */ 117 #define SIOP_SCNTL1_PAR 0x04 /* Force bad Parity */ 118 #define SIOP_SCNTL1_SND 0x02 /* Start Send operation */ 119 #define SIOP_SCNTL1_RCV 0x01 /* Start Receive operation */ 120 121 /* Scsi interrupt enable register (sien) */ 122 123 #define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 124 #define SIOP_SIEN_FC 0x40 /* Function Complete */ 125 #define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 126 #define SIOP_SIEN_SEL 0x10 /* (Re)Selected */ 127 #define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 128 #define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 129 #define SIOP_SIEN_RST 0x02 /* RST asserted */ 130 #define SIOP_SIEN_PAR 0x01 /* Parity Error */ 131 132 /* Scsi chip ID (scid) */ 133 134 #define SIOP_SCID_VALUE(i) (1<<i) 135 136 /* Scsi transfer register (sxfer) */ 137 138 #define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */ 139 #define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 140 /* see specs for formulas: 141 Period = TCP * (4 + XFERP ) 142 TCP = 1 + CLK + 1..2; 143 */ 144 #define SIOP_SXFER_MO 0x0f /* Synch Max Offset */ 145 # define SIOP_MAX_OFFSET 8 146 147 /* Scsi output data latch register (sodl) */ 148 149 /* Scsi output control latch register (socl) */ 150 151 #define SIOP_REQ 0x80 /* SCSI signal <x> asserted */ 152 #define SIOP_ACK 0x40 153 #define SIOP_BSY 0x20 154 #define SIOP_SEL 0x10 155 #define SIOP_ATN 0x08 156 #define SIOP_MSG 0x04 157 #define SIOP_CD 0x02 158 #define SIOP_IO 0x01 159 160 #define SIOP_PHASE(socl) SCSI_PHASE(socl) 161 162 /* Scsi first byte received register (sfbr) */ 163 164 /* Scsi input data latch register (sidl) */ 165 166 /* Scsi bus data lines register (sbdl) */ 167 168 /* Scsi bus control lines register (sbcl). Same as socl */ 169 170 /* DMA status register (dstat) */ 171 172 #define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 173 #define SIOP_DSTAT_RES 0x60 174 #define SIOP_DSTAT_ABRT 0x10 /* Aborted */ 175 #define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 176 #define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 177 #define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 178 #define SIOP_DSTAT_OPC 0x01 /* Invalid SCRIPTS Opcode */ 179 180 /* Scsi status register 0 (sstat0) */ 181 182 #define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 183 #define SIOP_SSTAT0_FC 0x40 /* Function Complete */ 184 #define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 185 #define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 186 #define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 187 #define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 188 #define SIOP_SSTAT0_RST 0x02 /* RST asserted */ 189 #define SIOP_SSTAT0_PAR 0x01 /* Parity Error */ 190 191 /* Scsi status register 1 (sstat1) */ 192 193 #define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 194 #define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 195 #define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 196 #define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 197 #define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 198 #define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 199 #define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 200 #define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 201 202 /* Scsi status register 2 (sstat2) */ 203 204 #define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 205 # define SIOP_SCSI_FIFO_DEEP 8 206 #define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 207 #define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 208 #define SIOP_SSTAT2_CD 0x02 209 #define SIOP_SSTAT2_IO 0x01 210 211 /* Chip test register 0 (ctest0) */ 212 213 #define SIOP_CTEST0_RES 0xfc 214 #define SIOP_CTEST0_RTRG 0x02 /* Real Target mode */ 215 #define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 216 217 /* Chip test register 1 (ctest1) */ 218 219 #define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */ 220 #define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 221 222 /* Chip test register 2 (ctest2) */ 223 224 #define SIOP_CTEST2_RES 0xc0 225 #define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */ 226 #define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 227 #define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 228 #define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 229 #define SIOP_CTEST2_DREQ 0x02 /* DREQ status */ 230 #define SIOP_CTEST2_DACK 0x01 /* DACK status */ 231 232 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 233 234 /* Chip test register 4 (ctest4) */ 235 236 #define SIOP_CTEST4_RES 0x80 237 #define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 238 #define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 239 #define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 240 #define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 241 #define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6) 242 4->0, .. 7->3 */ 243 244 /* Chip test register 5 (ctest5) */ 245 246 #define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 247 #define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 248 #define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 249 #define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */ 250 #define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 251 #define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 252 #define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 253 #define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 254 255 /* Chip test register 6 (ctest6) DMA FIFO access */ 256 257 /* Chip test register 7 (ctest7) */ 258 259 #define SIOP_CTEST7_RES 0xe0 260 #define SIOP_CTEST7_STD 0x10 /* Disable selection timeout */ 261 #define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 262 #define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 263 #define SIOP_CTEST7_DC 0x02 /* Drive DC pin low on SCRIPT fetches */ 264 #define SIOP_CTEST7_DIFF 0x01 /* Differential mode */ 265 266 /* DMA FIFO register (dfifo) */ 267 268 #define SIOP_DFIFO_FLF 0x80 /* Flush (spill) DMA FIFO */ 269 #define SIOP_DFIFO_CLF 0x40 /* Clear DMA and SCSI FIFOs */ 270 #define SIOP_DFIFO_BO 0x3f /* FIFO byte offset counter */ 271 272 /* Interrupt status register (istat) */ 273 274 #define SIOP_ISTAT_ABRT 0x80 /* Abort operation */ 275 #define SIOP_ISTAT_RES 0x70 276 #define SIOP_ISTAT_CON 0x08 /* Connected */ 277 #define SIOP_ISTAT_PRE 0x04 /* Pointer register empty */ 278 #define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 279 #define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 280 281 282 /* DMA Mode register (dmode) */ 283 284 #define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 285 #define SIOP_DMODE_BW16 0x20 /* Bus Width is 16 bits */ 286 #define SIOP_DMODE_286 0x10 /* 286 mode */ 287 #define SIOP_DMODE_IO_M 0x08 /* xfer data to memory or I/O space */ 288 #define SIOP_DMODE_FAM 0x04 /* fixed address mode */ 289 #define SIOP_DMODE_PIPE 0x02 /* SCRIPTS in Pipeline mode */ 290 #define SIOP_DMODE_MAN 0x01 /* SCRIPTS in Manual start mode */ 291 292 /* DMA interrupt enable register (dien) */ 293 294 #define SIOP_DIEN_RES 0xe0 295 #define SIOP_DIEN_ABRT 0x10 /* On Abort */ 296 #define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 297 #define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 298 #define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 299 #define SIOP_DIEN_OPC 0x01 /* On SCRIPTS illegal opcode */ 300 301 /* DMA control register (dcntl) */ 302 303 #define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: 304 0 --> 37.51..50.00 Mhz, div=2 305 1 --> 25.01..37.50 Mhz, div=1.5 306 2 --> 16.67..25.00 Mhz, div=1 307 3 --> 50.01..66.00 Mhz, div=3 308 */ 309 #define SIOP_DCNTL_S16 0x20 /* SCRIPTS fetches 16bits at a time */ 310 #define SIOP_DCNTL_SSM 0x10 /* Single step mode */ 311 #define SIOP_DCNTL_LLM 0x08 /* Enable Low-level mode */ 312 #define SIOP_DCNTL_STD 0x04 /* Start SCRIPTS operation */ 313 #define SIOP_DCNTL_RES 0x02 314 #define SIOP_DCNTL_RST 0x01 /* Software reset */ 315
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