siopreg.h revision 1.8
1 /* $NetBSD: siopreg.h,v 1.8 1996/04/21 21:12:37 veego Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 39 */ 40 41 /* 42 * NCR 53C710 SCSI interface hardware description. 43 * 44 * From the Mach scsi driver for the 53C700 45 */ 46 47 typedef struct { 48 /*00*/ volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */ 49 /*01*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 50 /*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 51 /*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 52 /*04*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 53 /*05*/ volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */ 54 /*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 55 /*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 56 /*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 57 /*09*/ volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */ 58 /*0a*/ volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */ 59 /*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 60 /*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 61 /*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 62 /*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 63 /*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */ 64 /*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 65 /*14*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 66 /*15*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 67 /*16*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 68 /*17*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 69 /*18*/ volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */ 70 /*19*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 71 /*1a*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 72 /*1b*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 73 /*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 74 /*20*/ volatile unsigned char siop_lcrc; /* rw: LCRC value */ 75 /*21*/ volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */ 76 /*22*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 77 /*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 78 /*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 79 /*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 80 /*26*/ volatile unsigned char siop_dbc1; 81 /*27*/ volatile unsigned char siop_dbc0; 82 /*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 83 /*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 84 /*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 85 /*34*/ volatile unsigned long siop_scratch; /* rw: Scratch Register */ 86 /*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 87 /*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 88 /*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 89 /*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 90 /*3c*/ volatile unsigned long siop_adder; 91 92 } siop_regmap_t; 93 typedef volatile siop_regmap_t *siop_regmap_p; 94 95 /* 96 * Register defines 97 */ 98 99 /* Scsi control register 0 (scntl0) */ 100 101 #define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 102 # define SIOP_ARB_SIMPLE 0x00 103 # define SIOP_ARB_FULL 0xc0 104 #define SIOP_SCNTL0_START 0x20 /* Start Sequence */ 105 #define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 106 #define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 107 #define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 108 #define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 109 #define SIOP_SCNTL0_TRG 0x01 /* Target Mode */ 110 111 /* Scsi control register 1 (scntl1) */ 112 113 #define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 114 #define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 115 #define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 116 #define SIOP_SCNTL1_CON 0x10 /* Connected */ 117 #define SIOP_SCNTL1_RST 0x08 /* Assert RST */ 118 #define SIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ 119 #define SIOP_SCNTL1_RES0 0x02 /* Reserved */ 120 #define SIOP_SCNTL1_RES1 0x01 /* Reserved */ 121 122 /* Scsi interrupt enable register (sien) */ 123 124 #define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 125 #define SIOP_SIEN_FCMP 0x40 /* Function Complete */ 126 #define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 127 #define SIOP_SIEN_SEL 0x10 /* (Re)Selected */ 128 #define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 129 #define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 130 #define SIOP_SIEN_RST 0x02 /* RST asserted */ 131 #define SIOP_SIEN_PAR 0x01 /* Parity Error */ 132 133 /* Scsi chip ID (scid) */ 134 135 #define SIOP_SCID_VALUE(i) (1<<i) 136 137 /* Scsi transfer register (sxfer) */ 138 139 #define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */ 140 #define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 141 /* see specs for formulas: 142 Period = TCP * (4 + XFERP ) 143 TCP = 1 + CLK + 1..2; 144 */ 145 #define SIOP_SXFER_MO 0x0f /* Synch Max Offset */ 146 # define SIOP_MAX_OFFSET 8 147 148 /* Scsi output data latch register (sodl) */ 149 150 /* Scsi output control latch register (socl) */ 151 152 #define SIOP_REQ 0x80 /* SCSI signal <x> asserted */ 153 #define SIOP_ACK 0x40 154 #define SIOP_BSY 0x20 155 #define SIOP_SEL 0x10 156 #define SIOP_ATN 0x08 157 #define SIOP_MSG 0x04 158 #define SIOP_CD 0x02 159 #define SIOP_IO 0x01 160 161 #define SIOP_PHASE(socl) SCSI_PHASE(socl) 162 163 /* Scsi first byte received register (sfbr) */ 164 165 /* Scsi input data latch register (sidl) */ 166 167 /* Scsi bus data lines register (sbdl) */ 168 169 /* Scsi bus control lines register (sbcl). Same as socl */ 170 171 /* DMA status register (dstat) */ 172 173 #define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 174 #define SIOP_DSTAT_RES 0x40 175 #define SIOP_DSTAT_BF 0x20 /* Bus fault */ 176 #define SIOP_DSTAT_ABRT 0x10 /* Aborted */ 177 #define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 178 #define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 179 #define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 180 #define SIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ 181 182 /* Scsi status register 0 (sstat0) */ 183 184 #define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 185 #define SIOP_SSTAT0_FCMP 0x40 /* Function Complete */ 186 #define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 187 #define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 188 #define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 189 #define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 190 #define SIOP_SSTAT0_RST 0x02 /* RST asserted */ 191 #define SIOP_SSTAT0_PAR 0x01 /* Parity Error */ 192 193 /* Scsi status register 1 (sstat1) */ 194 195 #define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 196 #define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 197 #define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 198 #define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 199 #define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 200 #define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 201 #define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 202 #define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 203 204 /* Scsi status register 2 (sstat2) */ 205 206 #define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 207 # define SIOP_SCSI_FIFO_DEEP 8 208 #define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 209 #define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 210 #define SIOP_SSTAT2_CD 0x02 211 #define SIOP_SSTAT2_IO 0x01 212 213 /* Chip test register 0 (ctest0) */ 214 215 #define SIOP_CTEST0_RES0 0x80 216 #define SIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ 217 #define SIOP_CTEST0_GRP 0x20 /* Generate Receive Parity for Passthrough */ 218 #define SIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ 219 #define SIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ 220 #define SIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ 221 #define SIOP_CTEST0_RES1 0x02 222 #define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 223 224 /* Chip test register 1 (ctest1) */ 225 226 #define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */ 227 #define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 228 229 /* Chip test register 2 (ctest2) */ 230 231 #define SIOP_CTEST2_RES 0x80 232 #define SIOP_CTEST2_SIGP 0x40 /* Signal process */ 233 #define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */ 234 #define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 235 #define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 236 #define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 237 #define SIOP_CTEST2_DREQ 0x02 /* DREQ status */ 238 #define SIOP_CTEST2_DACK 0x01 /* DACK status */ 239 240 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 241 242 /* Chip test register 4 (ctest4) */ 243 244 #define SIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ 245 #define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 246 #define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 247 #define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 248 #define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 249 #define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6) 250 4->0, .. 7->3 */ 251 252 /* Chip test register 5 (ctest5) */ 253 254 #define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 255 #define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 256 #define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 257 #define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */ 258 #define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 259 #define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 260 #define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 261 #define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 262 263 /* Chip test register 6 (ctest6) DMA FIFO access */ 264 265 /* Chip test register 7 (ctest7) */ 266 267 #define SIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ 268 #define SIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ 269 #define SIOP_CTEST7_SC0 0x20 /* Snoop contorl 0 */ 270 #define SIOP_CTEST7_STD 0x10 /* Selection timeout disable */ 271 #define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 272 #define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 273 #define SIOP_CTEST7_TT1 0x02 /* Transfer type bit */ 274 #define SIOP_CTEST7_DIFF 0x01 /* Differential mode */ 275 276 /* DMA FIFO register (dfifo) */ 277 278 #define SIOP_DFIFO_RES 0x80 279 #define SIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ 280 281 /* Interrupt status register (istat) */ 282 283 #define SIOP_ISTAT_ABRT 0x80 /* Abort operation */ 284 #define SIOP_ISTAT_RST 0x40 /* Software reset */ 285 #define SIOP_ISTAT_SIGP 0x20 /* Signal process */ 286 #define SIOP_ISTAT_RES 0x10 287 #define SIOP_ISTAT_CON 0x08 /* Connected */ 288 #define SIOP_ISTAT_RES1 0x04 289 #define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 290 #define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 291 292 /* Chip test register 8 (ctest8) */ 293 294 #define SIOP_CTEST8_V 0xf0 /* Chip revision level */ 295 #define SIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ 296 #define SIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ 297 #define SIOP_CTEST8_FM 0x02 /* Fetch pin mode */ 298 #define SIOP_CTEST8_SM 0x01 /* Snoop pins mode */ 299 300 /* DMA Mode register (dmode) */ 301 302 #define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 303 #define SIOP_DMODE_FC 0x30 /* Function code */ 304 #define SIOP_DMODE_PD 0x08 /* Program/data */ 305 #define SIOP_DMODE_FAM 0x04 /* Fixed address mode */ 306 #define SIOP_DMODE_U0 0x02 /* User programmable transfer type */ 307 #define SIOP_DMODE_MAN 0x01 /* Manual start mode */ 308 309 /* DMA interrupt enable register (dien) */ 310 311 #define SIOP_DIEN_RES 0xc0 312 #define SIOP_DIEN_BF 0x20 /* On Bus Fault */ 313 #define SIOP_DIEN_ABRT 0x10 /* On Abort */ 314 #define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 315 #define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 316 #define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 317 #define SIOP_DIEN_IID 0x01 /* On illegal instruction detected */ 318 319 /* DMA control register (dcntl) */ 320 321 #define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: 322 0 --> 37.51..50.00 Mhz, div=2 323 1 --> 25.01..37.50 Mhz, div=1.5 324 2 --> 16.67..25.00 Mhz, div=1 325 3 --> 50.01..66.67 Mhz, div=3 326 */ 327 #define SIOP_DCNTL_EA 0x20 /* Enable ack */ 328 #define SIOP_DCNTL_SSM 0x10 /* Single step mode */ 329 #define SIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ 330 #define SIOP_DCNTL_STD 0x04 /* Start DMA operation */ 331 #define SIOP_DCNTL_FA 0x02 /* Fast arbitration */ 332 #define SIOP_DCNTL_COM 0x01 /* 53C700 compatibility */ 333
Indexes created Sun Sep 28 16:09:52 GMT 2025