siopreg.h revision 1.9
1 /* $NetBSD: siopreg.h,v 1.9 1999/03/09 20:31:34 is Exp $ */ 2 3 /* 4 * Copyright (c) 1990 The Regents of the University of California. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Van Jacobson of Lawrence Berkeley Laboratory. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * @(#)siopreg.h 7.3 (Berkeley) 2/5/91 39 */ 40 41 /* 42 * NCR 53C710 SCSI interface hardware description. 43 * 44 * From the Mach scsi driver for the 53C700 45 */ 46 47 typedef struct { 48 49 #ifndef ARCH_720 50 51 /*00*/ volatile unsigned char siop_sien; /* rw: SCSI Interrupt Enable */ 52 /*01*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 53 /*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 54 /*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 55 56 /*04*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 57 /*05*/ volatile unsigned char siop_sodl; /* rw: SCSI Output Data Latch */ 58 /*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 59 /*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 60 61 /*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 62 /*09*/ volatile unsigned char siop_sbdl; /* ro: SCSI Bus Data Lines */ 63 /*0a*/ volatile unsigned char siop_sidl; /* ro: SCSI Input Data Latch */ 64 /*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 65 66 /*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 67 /*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 68 /*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 69 /*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */ 70 71 /*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 72 73 /*14*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 74 /*15*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 75 /*16*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 76 /*17*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 77 78 /*18*/ volatile unsigned char siop_ctest7; /* rw: Chip test register 7 */ 79 /*19*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 80 /*1a*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 81 /*1b*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 82 83 /*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 84 85 /*20*/ volatile unsigned char siop_lcrc; /* rw: LCRC value */ 86 /*21*/ volatile unsigned char siop_ctest8; /* rw: Chip test register 8 */ 87 /*22*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 88 /*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 89 90 /*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 91 /*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 92 /*26*/ volatile unsigned char siop_dbc1; 93 /*27*/ volatile unsigned char siop_dbc0; 94 95 /*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 96 97 /*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 98 99 /*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 100 101 /*34*/ volatile unsigned long siop_scratch; /* rw: Scratch Register */ 102 103 /*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 104 /*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 105 /*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 106 /*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 107 108 /*3c*/ volatile unsigned long siop_adder; 109 110 #else 111 112 /*00*/ volatile unsigned char siop_scntl3; /* rw: SCSI control reg 3 */ 113 /*01*/ volatile unsigned char siop_scntl2; /* rw: SCSI control reg 2 */ 114 /*02*/ volatile unsigned char siop_scntl1; /* rw: SCSI control reg 1 */ 115 /*03*/ volatile unsigned char siop_scntl0; /* rw: SCSI control reg 0 */ 116 117 /*04*/ volatile unsigned char siop_gpreg; /* rw: SCSI */ 118 /*05*/ volatile unsigned char siop_sdid; /* rw: SCSI Destination ID */ 119 /*06*/ volatile unsigned char siop_sxfer; /* rw: SCSI Transfer reg */ 120 /*07*/ volatile unsigned char siop_scid; /* rw: SCSI Chip ID reg */ 121 122 /*08*/ volatile unsigned char siop_sbcl; /* ro: SCSI Bus Control Lines */ 123 /*09*/ volatile unsigned char siop_ssid; /* ro: SCSI */ 124 /*0a*/ volatile unsigned char siop_socl; /* rw: SCSI Output Control Latch */ 125 /*0b*/ volatile unsigned char siop_sfbr; /* ro: SCSI First Byte Received */ 126 127 /*0c*/ volatile unsigned char siop_sstat2; /* ro: SCSI status reg 2 */ 128 /*0d*/ volatile unsigned char siop_sstat1; /* ro: SCSI status reg 1 */ 129 /*0e*/ volatile unsigned char siop_sstat0; /* ro: SCSI status reg 0 */ 130 /*0f*/ volatile unsigned char siop_dstat; /* ro: DMA status */ 131 132 /*10*/ volatile unsigned long siop_dsa; /* rw: Data Structure Address */ 133 134 /*14*/ volatile unsigned char siop_14_; /* ??: */ 135 /*15*/ volatile unsigned char siop_15_; /* ??: */ 136 /*16*/ volatile unsigned char siop_16_; /* ??: */ 137 /*17*/ volatile unsigned char siop_istat; /* rw: Interrupt Status reg */ 138 139 /*18*/ volatile unsigned char siop_ctest3; /* ro: Chip test register 3 */ 140 /*19*/ volatile unsigned char siop_ctest2; /* ro: Chip test register 2 */ 141 /*1a*/ volatile unsigned char siop_ctest1; /* ro: Chip test register 1 */ 142 /*1b*/ volatile unsigned char siop_ctest0; /* ro: Chip test register 0 */ 143 144 /*1c*/ volatile unsigned long siop_temp; /* rw: Temporary Stack reg */ 145 146 /*20*/ volatile unsigned char siop_ctest6; /* rw: Chip test register 6 */ 147 /*21*/ volatile unsigned char siop_ctest5; /* rw: Chip test register 5 */ 148 /*22*/ volatile unsigned char siop_ctest4; /* rw: Chip test register 4 */ 149 /*23*/ volatile unsigned char siop_dfifo; /* rw: DMA FIFO */ 150 151 /*24*/ volatile unsigned char siop_dcmd; /* rw: DMA Command Register */ 152 /*25*/ volatile unsigned char siop_dbc2; /* rw: DMA Byte Counter reg */ 153 /*26*/ volatile unsigned char siop_dbc1; 154 /*27*/ volatile unsigned char siop_dbc0; 155 156 /*28*/ volatile unsigned long siop_dnad; /* rw: DMA Next Address */ 157 158 /*2c*/ volatile unsigned long siop_dsp; /* rw: DMA SCRIPTS Pointer reg */ 159 160 /*30*/ volatile unsigned long siop_dsps; /* rw: DMA SCRIPTS Pointer Save reg */ 161 162 /*34*/ volatile unsigned long siop_scratcha; /* rw: Scratch Register A */ 163 164 /*38*/ volatile unsigned char siop_dcntl; /* rw: DMA Control reg */ 165 /*39*/ volatile unsigned char siop_dwt; /* rw: DMA Watchdog Timer */ 166 /*3a*/ volatile unsigned char siop_dien; /* rw: DMA Interrupt Enable */ 167 /*3b*/ volatile unsigned char siop_dmode; /* rw: DMA Mode reg */ 168 169 /*3c*/ volatile unsigned long siop_adder; 170 171 /*40*/ volatile unsigned short siop_sist; /* rw: SCSI Interrupt Status */ 172 #define SIOP_SIST_STO 0x0400 /* timeout (select) */ 173 #define SIOP_SIST_GEN 0x0200 /* timeout (general) */ 174 #define SIOP_SIST_MA 0x0080 /* phase mispatch */ 175 #define SIOP_SIST_SGE 0x0008 /* gross error (over/underflow) */ 176 #define SIOP_SIST_UDC 0x0004 /* unexpected disconnect */ 177 #define SIOP_SIST_PAR 0x0001 /* scsi parity error */ 178 /*42*/ volatile unsigned short siop_sien; /* rw: SCSI Interrupt Enable */ 179 #define SIOP_SIEN_STO 0x0400 /* timeout (select) */ 180 #define SIOP_SIEN_GEN 0x0200 /* timeout (general) */ 181 #define SIOP_SIEN_MA 0x0080 /* phase mispatch */ 182 #define SIOP_SIEN_SGE 0x0008 /* gross error (over/underflow) */ 183 #define SIOP_SIEN_UDC 0x0004 /* unexpected disconnect */ 184 #define SIOP_SIEN_RST 0x0002 /* scsi bus reset */ 185 #define SIOP_SIEN_PAR 0x0001 /* scsi parity error */ 186 187 /*44*/ volatile unsigned char siop_gpcntl; /* rw: SCSI */ 188 /*45*/ volatile unsigned char siop_macntl; /* rw: SCSI */ 189 /*46*/ volatile unsigned char siop_swide; /* rw: SCSI */ 190 /*47*/ volatile unsigned char siop_slpar; /* rw: SCSI */ 191 192 /*48*/ volatile unsigned short siop_respid; /* rw: SCSI Reselect-IDS */ 193 /*4a*/ volatile unsigned char siop_stime1; /* rw: SCSI */ 194 /*4b*/ volatile unsigned char siop_stime0; /* rw: SCSI */ 195 196 /*4c*/ volatile unsigned char siop_stest3; /* ro: Chip test register 3 */ 197 /*4d*/ volatile unsigned char siop_stest2; /* ro: Chip test register 2 */ 198 /*4e*/ volatile unsigned char siop_stest1; /* ro: Chip test register 1 */ 199 /*4f*/ volatile unsigned char siop_stest0; /* ro: Chip test register 0 */ 200 201 /*50*/ volatile unsigned char siop_50_; /* rw: SCSI */ 202 /*51*/ volatile unsigned char siop_stest4; /* rw: SCSI */ 203 /*52*/ volatile unsigned short siop_sidl; /* ro: SCSI Input Data Latch */ 204 205 /*54*/ volatile unsigned short siop_54_; /* rw: SCSI */ 206 /*56*/ volatile unsigned short siop_sodl; /* rw: SCSI Output Data Latch */ 207 208 /*58*/ volatile unsigned short siop_58_; /* rw: SCSI */ 209 /*5a*/ volatile unsigned short siop_sbdl; /* ro: SCSI Bus Data Lines */ 210 211 /*5c*/ volatile unsigned long siop_scratchb; /* rw: Scratch Register B */ 212 #endif 213 214 } siop_regmap_t; 215 typedef volatile siop_regmap_t *siop_regmap_p; 216 217 /* 218 * Register defines 219 */ 220 221 /* Scsi control register 0 (scntl0) */ 222 223 #define SIOP_SCNTL0_ARB 0xc0 /* Arbitration mode */ 224 # define SIOP_ARB_SIMPLE 0x00 225 # define SIOP_ARB_FULL 0xc0 226 #define SIOP_SCNTL0_START 0x20 /* Start Sequence */ 227 #define SIOP_SCNTL0_WATN 0x10 /* (Select) With ATN */ 228 #define SIOP_SCNTL0_EPC 0x08 /* Enable Parity Checking */ 229 #define SIOP_SCNTL0_EPG 0x04 /* Enable Parity Generation */ 230 #define SIOP_SCNTL0_AAP 0x02 /* Assert ATN on Parity Error */ 231 #define SIOP_SCNTL0_TRG 0x01 /* Target Mode */ 232 233 /* Scsi control register 1 (scntl1) */ 234 235 #define SIOP_SCNTL1_EXC 0x80 /* Extra Clock Cycle of data setup */ 236 #define SIOP_SCNTL1_ADB 0x40 /* Assert Data Bus */ 237 #define SIOP_SCNTL1_ESR 0x20 /* Enable Selection/Reselection */ 238 #define SIOP_SCNTL1_CON 0x10 /* Connected */ 239 #define SIOP_SCNTL1_RST 0x08 /* Assert RST */ 240 #define SIOP_SCNTL1_AESP 0x04 /* Assert even SCSI parity */ 241 #define SIOP_SCNTL1_RES0 0x02 /* Reserved */ 242 #define SIOP_SCNTL1_RES1 0x01 /* Reserved */ 243 244 /* Scsi interrupt enable register (sien) */ 245 246 #ifndef ARCH_720 247 #define SIOP_SIEN_M_A 0x80 /* Phase Mismatch or ATN active */ 248 #define SIOP_SIEN_FCMP 0x40 /* Function Complete */ 249 #define SIOP_SIEN_STO 0x20 /* (Re)Selection timeout */ 250 #define SIOP_SIEN_SEL 0x10 /* (Re)Selected */ 251 #define SIOP_SIEN_SGE 0x08 /* SCSI Gross Error */ 252 #define SIOP_SIEN_UDC 0x04 /* Unexpected Disconnect */ 253 #define SIOP_SIEN_RST 0x02 /* RST asserted */ 254 #define SIOP_SIEN_PAR 0x01 /* Parity Error */ 255 #endif 256 257 /* Scsi chip ID (scid) */ 258 259 #define SIOP_SCID_VALUE(i) (1<<i) 260 261 /* Scsi transfer register (sxfer) */ 262 263 #define SIOP_SXFER_DHP 0x80 /* Disable Halt on Parity error/ ATN asserted */ 264 #define SIOP_SXFER_TP 0x70 /* Synch Transfer Period */ 265 /* see specs for formulas: 266 Period = TCP * (4 + XFERP ) 267 TCP = 1 + CLK + 1..2; 268 */ 269 #ifndef ARCH_720 270 #define SIOP_SXFER_MO 0x0f /* Synch Max Offset */ 271 # define SIOP_MAX_OFFSET 8 272 #else 273 #define SIOP_SXFER_MO 0x1f /* Synch Max Offset */ 274 # define SIOP_MAX_OFFSET 16 275 #endif 276 277 /* Scsi output data latch register (sodl) */ 278 279 /* Scsi output control latch register (socl) */ 280 281 #define SIOP_REQ 0x80 /* SCSI signal <x> asserted */ 282 #define SIOP_ACK 0x40 283 #define SIOP_BSY 0x20 284 #define SIOP_SEL 0x10 285 #define SIOP_ATN 0x08 286 #define SIOP_MSG 0x04 287 #define SIOP_CD 0x02 288 #define SIOP_IO 0x01 289 290 #define SIOP_PHASE(socl) SCSI_PHASE(socl) 291 292 /* Scsi first byte received register (sfbr) */ 293 294 /* Scsi input data latch register (sidl) */ 295 296 /* Scsi bus data lines register (sbdl) */ 297 298 /* Scsi bus control lines register (sbcl). Same as socl */ 299 300 /* DMA status register (dstat) */ 301 302 #define SIOP_DSTAT_DFE 0x80 /* DMA FIFO empty */ 303 #define SIOP_DSTAT_RES 0x40 304 #define SIOP_DSTAT_BF 0x20 /* Bus fault */ 305 #define SIOP_DSTAT_ABRT 0x10 /* Aborted */ 306 #define SIOP_DSTAT_SSI 0x08 /* SCRIPT Single Step */ 307 #define SIOP_DSTAT_SIR 0x04 /* SCRIPT Interrupt Instruction */ 308 #define SIOP_DSTAT_WTD 0x02 /* Watchdog Timeout Detected */ 309 #define SIOP_DSTAT_IID 0x01 /* Invalid Instruction Detected */ 310 311 /* Scsi status register 0 (sstat0) */ 312 313 #define SIOP_SSTAT0_M_A 0x80 /* Phase Mismatch or ATN active */ 314 #define SIOP_SSTAT0_FCMP 0x40 /* Function Complete */ 315 #define SIOP_SSTAT0_STO 0x20 /* (Re)Selection timeout */ 316 #define SIOP_SSTAT0_SEL 0x10 /* (Re)Selected */ 317 #define SIOP_SSTAT0_SGE 0x08 /* SCSI Gross Error */ 318 #define SIOP_SSTAT0_UDC 0x04 /* Unexpected Disconnect */ 319 #define SIOP_SSTAT0_RST 0x02 /* RST asserted */ 320 #define SIOP_SSTAT0_PAR 0x01 /* Parity Error */ 321 322 /* Scsi status register 1 (sstat1) */ 323 324 #define SIOP_SSTAT1_ILF 0x80 /* Input latch (sidl) full */ 325 #define SIOP_SSTAT1_ORF 0x40 /* output reg (sodr) full */ 326 #define SIOP_SSTAT1_OLF 0x20 /* output latch (sodl) full */ 327 #define SIOP_SSTAT1_AIP 0x10 /* Arbitration in progress */ 328 #define SIOP_SSTAT1_LOA 0x08 /* Lost arbitration */ 329 #define SIOP_SSTAT1_WOA 0x04 /* Won arbitration */ 330 #define SIOP_SSTAT1_RST 0x02 /* SCSI RST current value */ 331 #define SIOP_SSTAT1_SDP 0x01 /* SCSI SDP current value */ 332 333 /* Scsi status register 2 (sstat2) */ 334 335 #define SIOP_SSTAT2_FF 0xf0 /* SCSI FIFO flags (bytecount) */ 336 # define SIOP_SCSI_FIFO_DEEP 8 337 #define SIOP_SSTAT2_SDP 0x08 /* Latched (on REQ) SCSI SDP */ 338 #define SIOP_SSTAT2_MSG 0x04 /* Latched SCSI phase */ 339 #define SIOP_SSTAT2_CD 0x02 340 #define SIOP_SSTAT2_IO 0x01 341 342 /* Chip test register 0 (ctest0) */ 343 344 #define SIOP_CTEST0_RES0 0x80 345 #define SIOP_CTEST0_BTD 0x40 /* Byte-to-byte Timer Disable */ 346 #define SIOP_CTEST0_GRP 0x20 /* Generate Receive Parity for Passthrough */ 347 #define SIOP_CTEST0_EAN 0x10 /* Enable Active Negation */ 348 #define SIOP_CTEST0_HSC 0x08 /* Halt SCSI clock */ 349 #define SIOP_CTEST0_ERF 0x04 /* Extend REQ/ACK Filtering */ 350 #define SIOP_CTEST0_RES1 0x02 351 #define SIOP_CTEST0_DDIR 0x01 /* Xfer direction (1-> from SCSI bus) */ 352 353 /* Chip test register 1 (ctest1) */ 354 355 #define SIOP_CTEST1_FMT 0xf0 /* Byte empty in DMA FIFO bottom (high->byte3) */ 356 #define SIOP_CTEST1_FFL 0x0f /* Byte full in DMA FIFO top, same */ 357 358 /* Chip test register 2 (ctest2) */ 359 360 #define SIOP_CTEST2_RES 0x80 361 #define SIOP_CTEST2_SIGP 0x40 /* Signal process */ 362 #define SIOP_CTEST2_SOFF 0x20 /* Synch Offset compare (1-> zero Init, max Tgt */ 363 #define SIOP_CTEST2_SFP 0x10 /* SCSI FIFO Parity */ 364 #define SIOP_CTEST2_DFP 0x08 /* DMA FIFO Parity */ 365 #define SIOP_CTEST2_TEOP 0x04 /* True EOP (a-la 5380) */ 366 #define SIOP_CTEST2_DREQ 0x02 /* DREQ status */ 367 #define SIOP_CTEST2_DACK 0x01 /* DACK status */ 368 369 /* Chip test register 3 (ctest3) read-only, top of SCSI FIFO */ 370 371 /* Chip test register 4 (ctest4) */ 372 373 #define SIOP_CTEST4_MUX 0x80 /* Host bus multiplex mode */ 374 #define SIOP_CTEST4_ZMOD 0x40 /* High-impedance outputs */ 375 #define SIOP_CTEST4_SZM 0x20 /* ditto, SCSI "outputs" */ 376 #define SIOP_CTEST4_SLBE 0x10 /* SCSI loobpack enable */ 377 #define SIOP_CTEST4_SFWR 0x08 /* SCSI FIFO write enable (from sodl) */ 378 #define SIOP_CTEST4_FBL 0x07 /* DMA FIFO Byte Lane select (from ctest6) 379 4->0, .. 7->3 */ 380 381 /* Chip test register 5 (ctest5) */ 382 383 #define SIOP_CTEST5_ADCK 0x80 /* Clock Address Incrementor */ 384 #define SIOP_CTEST5_BBCK 0x40 /* Clock Byte counter */ 385 #define SIOP_CTEST5_ROFF 0x20 /* Reset SCSI offset */ 386 #define SIOP_CTEST5_MASR 0x10 /* Master set/reset pulses (of bits 3-0) */ 387 #define SIOP_CTEST5_DDIR 0x08 /* (re)set internal DMA direction */ 388 #define SIOP_CTEST5_EOP 0x04 /* (re)set internal EOP */ 389 #define SIOP_CTEST5_DREQ 0x02 /* (re)set internal REQ */ 390 #define SIOP_CTEST5_DACK 0x01 /* (re)set internal ACK */ 391 392 /* Chip test register 6 (ctest6) DMA FIFO access */ 393 394 /* Chip test register 7 (ctest7) */ 395 396 #define SIOP_CTEST7_CDIS 0x80 /* Cache burst disable */ 397 #define SIOP_CTEST7_SC1 0x40 /* Snoop control 1 */ 398 #define SIOP_CTEST7_SC0 0x20 /* Snoop contorl 0 */ 399 #define SIOP_CTEST7_STD 0x10 /* Selection timeout disable */ 400 #define SIOP_CTEST7_DFP 0x08 /* DMA FIFO parity bit */ 401 #define SIOP_CTEST7_EVP 0x04 /* Even parity (to host bus) */ 402 #define SIOP_CTEST7_TT1 0x02 /* Transfer type bit */ 403 #define SIOP_CTEST7_DIFF 0x01 /* Differential mode */ 404 405 /* DMA FIFO register (dfifo) */ 406 407 #define SIOP_DFIFO_RES 0x80 408 #define SIOP_DFIFO_BO 0x7f /* FIFO byte offset counter */ 409 410 /* Interrupt status register (istat) */ 411 412 #define SIOP_ISTAT_ABRT 0x80 /* Abort operation */ 413 #define SIOP_ISTAT_RST 0x40 /* Software reset */ 414 #define SIOP_ISTAT_SIGP 0x20 /* Signal process */ 415 #define SIOP_ISTAT_RES 0x10 416 #define SIOP_ISTAT_CON 0x08 /* Connected */ 417 #define SIOP_ISTAT_RES1 0x04 418 #define SIOP_ISTAT_SIP 0x02 /* SCSI Interrupt pending */ 419 #define SIOP_ISTAT_DIP 0x01 /* DMA Interrupt pending */ 420 421 /* Chip test register 8 (ctest8) */ 422 423 #define SIOP_CTEST8_V 0xf0 /* Chip revision level */ 424 #define SIOP_CTEST8_FLF 0x08 /* Flush DMA FIFO */ 425 #define SIOP_CTEST8_CLF 0x04 /* Clear DMA and SCSI FIFOs */ 426 #define SIOP_CTEST8_FM 0x02 /* Fetch pin mode */ 427 #define SIOP_CTEST8_SM 0x01 /* Snoop pins mode */ 428 429 /* DMA Mode register (dmode) */ 430 431 #define SIOP_DMODE_BL_MASK 0xc0 /* 0->1 1->2 2->4 3->8 */ 432 #define SIOP_DMODE_FC 0x30 /* Function code */ 433 #define SIOP_DMODE_PD 0x08 /* Program/data */ 434 #define SIOP_DMODE_FAM 0x04 /* Fixed address mode */ 435 #define SIOP_DMODE_U0 0x02 /* User programmable transfer type */ 436 #define SIOP_DMODE_MAN 0x01 /* Manual start mode */ 437 438 /* DMA interrupt enable register (dien) */ 439 440 #define SIOP_DIEN_RES 0xc0 441 #define SIOP_DIEN_BF 0x20 /* On Bus Fault */ 442 #define SIOP_DIEN_ABRT 0x10 /* On Abort */ 443 #define SIOP_DIEN_SSI 0x08 /* On SCRIPTS sstep */ 444 #define SIOP_DIEN_SIR 0x04 /* On SCRIPTS intr instruction */ 445 #define SIOP_DIEN_WTD 0x02 /* On watchdog timeout */ 446 #define SIOP_DIEN_IID 0x01 /* On illegal instruction detected */ 447 448 /* DMA control register (dcntl) */ 449 450 #define SIOP_DCNTL_CF_MASK 0xc0 /* Clock frequency dividers: 451 0 --> 37.51..50.00 Mhz, div=2 452 1 --> 25.01..37.50 Mhz, div=1.5 453 2 --> 16.67..25.00 Mhz, div=1 454 3 --> 50.01..66.67 Mhz, div=3 455 */ 456 #define SIOP_DCNTL_EA 0x20 /* Enable ack */ 457 #define SIOP_DCNTL_SSM 0x10 /* Single step mode */ 458 #define SIOP_DCNTL_LLM 0x08 /* Enable SCSI Low-level mode */ 459 #define SIOP_DCNTL_STD 0x04 /* Start DMA operation */ 460 #define SIOP_DCNTL_FA 0x02 /* Fast arbitration */ 461 #define SIOP_DCNTL_COM 0x01 /* 53C700 compatibility */ 462
Indexes created Mon Sep 29 21:09:56 GMT 2025