cpu.h revision 1.1.1.1 1 1.1 mw /*
2 1.1 mw * Copyright (c) 1988 University of Utah.
3 1.1 mw * Copyright (c) 1982, 1990 The Regents of the University of California.
4 1.1 mw * All rights reserved.
5 1.1 mw *
6 1.1 mw * This code is derived from software contributed to Berkeley by
7 1.1 mw * the Systems Programming Group of the University of Utah Computer
8 1.1 mw * Science Department.
9 1.1 mw *
10 1.1 mw * Redistribution and use in source and binary forms, with or without
11 1.1 mw * modification, are permitted provided that the following conditions
12 1.1 mw * are met:
13 1.1 mw * 1. Redistributions of source code must retain the above copyright
14 1.1 mw * notice, this list of conditions and the following disclaimer.
15 1.1 mw * 2. Redistributions in binary form must reproduce the above copyright
16 1.1 mw * notice, this list of conditions and the following disclaimer in the
17 1.1 mw * documentation and/or other materials provided with the distribution.
18 1.1 mw * 3. All advertising materials mentioning features or use of this software
19 1.1 mw * must display the following acknowledgement:
20 1.1 mw * This product includes software developed by the University of
21 1.1 mw * California, Berkeley and its contributors.
22 1.1 mw * 4. Neither the name of the University nor the names of its contributors
23 1.1 mw * may be used to endorse or promote products derived from this software
24 1.1 mw * without specific prior written permission.
25 1.1 mw *
26 1.1 mw * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 1.1 mw * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 1.1 mw * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 1.1 mw * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 1.1 mw * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 1.1 mw * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 1.1 mw * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 1.1 mw * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 1.1 mw * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 1.1 mw * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 1.1 mw * SUCH DAMAGE.
37 1.1 mw *
38 1.1 mw * from: Utah $Hdr: cpu.h 1.16 91/03/25$
39 1.1 mw *
40 1.1 mw * @(#)cpu.h 7.7 (Berkeley) 6/27/91
41 1.1 mw */
42 1.1 mw
43 1.1 mw /*
44 1.1 mw * Exported definitions unique to amiga/68k cpu support.
45 1.1 mw */
46 1.1 mw
47 1.1 mw /*
48 1.1 mw * definitions of cpu-dependent requirements
49 1.1 mw * referenced in generic code
50 1.1 mw */
51 1.1 mw #define COPY_SIGCODE /* copy sigcode above user stack in exec */
52 1.1 mw
53 1.1 mw /*
54 1.1 mw * function vs. inline configuration;
55 1.1 mw * these are defined to get generic functions
56 1.1 mw * rather than inline or machine-dependent implementations
57 1.1 mw */
58 1.1 mw #define NEED_MINMAX /* need {,i,l,ul}{min,max} functions */
59 1.1 mw #undef NEED_FFS /* don't need ffs function */
60 1.1 mw #undef NEED_BCMP /* don't need bcmp function */
61 1.1 mw #undef NEED_STRLEN /* don't need strlen function */
62 1.1 mw
63 1.1 mw #define cpu_exec(p) /* nothing */
64 1.1 mw #define cpu_wait(p) /* nothing */
65 1.1 mw
66 1.1 mw /*
67 1.1 mw * Arguments to hardclock, softclock and gatherstats
68 1.1 mw * encapsulate the previous machine state in an opaque
69 1.1 mw * clockframe; for hp300, use just what the hardware
70 1.1 mw * leaves on the stack.
71 1.1 mw */
72 1.1 mw typedef struct intrframe {
73 1.1 mw int pc;
74 1.1 mw int ps;
75 1.1 mw } clockframe;
76 1.1 mw
77 1.1 mw #define CLKF_USERMODE(framep) (((framep)->ps & PSL_S) == 0)
78 1.1 mw #define CLKF_BASEPRI(framep) (((framep)->ps & PSL_IPL7) == 0)
79 1.1 mw #define CLKF_PC(framep) ((framep)->pc)
80 1.1 mw
81 1.1 mw
82 1.1 mw /*
83 1.1 mw * Preempt the current process if in interrupt from user mode,
84 1.1 mw * or after the current trap/syscall if in system mode.
85 1.1 mw */
86 1.1 mw #define need_resched() { want_resched++; aston(); }
87 1.1 mw
88 1.1 mw /*
89 1.1 mw * Give a profiling tick to the current process from the softclock
90 1.1 mw * interrupt. On hp300, request an ast to send us through trap(),
91 1.1 mw * marking the proc as needing a profiling tick.
92 1.1 mw */
93 1.1 mw #define profile_tick(p, framep) { (p)->p_flag |= SOWEUPC; aston(); }
94 1.1 mw
95 1.1 mw /*
96 1.1 mw * Notify the current process (p) that it has a signal pending,
97 1.1 mw * process as soon as possible.
98 1.1 mw */
99 1.1 mw #define signotify(p) aston()
100 1.1 mw
101 1.1 mw #define aston() (astpending++)
102 1.1 mw
103 1.1 mw int astpending; /* need to trap before returning to user mode */
104 1.1 mw int want_resched; /* resched() was called */
105 1.1 mw
106 1.1 mw
107 1.1 mw /*
108 1.1 mw * simulated software interrupt register
109 1.1 mw */
110 1.1 mw extern unsigned char ssir;
111 1.1 mw
112 1.1 mw #define SIR_NET 0x1
113 1.1 mw #define SIR_CLOCK 0x2
114 1.1 mw
115 1.1 mw #define siroff(x) ssir &= ~(x)
116 1.1 mw #define setsoftnet() ssir |= SIR_NET
117 1.1 mw #define setsoftclock() ssir |= SIR_CLOCK
118 1.1 mw
119 1.1 mw
120 1.1 mw /*
121 1.1 mw * The rest of this should probably be moved to ../amiga/amigacpu.h,
122 1.1 mw * although some of it could probably be put into generic 68k headers.
123 1.1 mw */
124 1.1 mw
125 1.1 mw /* values for machineid (happen to be AFF_* settings of AttnFlags)
126 1.1 mw * NOTE: '40 support does NOT YET exist! */
127 1.1 mw #define AMIGA_68020 (1L<<1)
128 1.1 mw #define AMIGA_68030 (1L<<2)
129 1.1 mw #define AMIGA_68040 (1L<<3)
130 1.1 mw #define AMIGA_68881 (1L<<4)
131 1.1 mw #define AMIGA_68882 (1L<<5)
132 1.1 mw #define AMIGA_FPU40 (1L<<6)
133 1.1 mw
134 1.1 mw
135 1.1 mw /* values for mmutype (assigned for quick testing) */
136 1.1 mw #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */
137 1.1 mw #define MMU_68851 1 /* Motorola 68851 */
138 1.1 mw
139 1.1 mw /* values for cpuspeed (not really related to clock speed due to caches) */
140 1.1 mw #define MHZ_8 1
141 1.1 mw #define MHZ_16 2
142 1.1 mw #define MHZ_25 3
143 1.1 mw #define MHZ_33 4
144 1.1 mw #define MHZ_50 6
145 1.1 mw
146 1.1 mw #ifdef KERNEL
147 1.1 mw extern int machineid, mmutype;
148 1.1 mw extern char *chipmembase, *chipmemlimit;
149 1.1 mw extern char *customchipbase, *customchiplimit;
150 1.1 mw
151 1.1 mw /* what is this supposed to do? i.e. how is it different than startrtclock?
152 1.1 mw #define enablertclock()
153 1.1 mw
154 1.1 mw Answer (MW): startrtclock is supposed to start the clock chip (to get an
155 1.1 mw accurate uptime, enablertclock is called later (after *vital* stuff
156 1.1 mw has been setup) to enable clock interrupts. Enabling clock interrupts
157 1.1 mw at startrtclock-time can get you into big troubles... */
158 1.1 mw
159 1.1 mw #endif
160 1.1 mw
161 1.1 mw /* physical memory sections */
162 1.1 mw #define CHIPMEMBASE (0x00000000)
163 1.1 mw /* maximum for mapping, not the whole range is needed in physical equivalence */
164 1.1 mw #define CHIPMEMTOP (0x00200000)
165 1.1 mw #define CHIPMEMSIZE btoc(CHIPMEMTOP-CHIPMEMBASE)
166 1.1 mw /* CIA-A and CIA-B */
167 1.1 mw #define CIABASE (0x00BFC000)
168 1.1 mw #define CIATOP (0x00C00000)
169 1.1 mw #define CIASIZE btoc(CIATOP-CIABASE)
170 1.1 mw #define CUSTOMBASE (0x00DFE000)
171 1.1 mw #define CUSTOMTOP (0x00E00000)
172 1.1 mw #define CUSTOMSIZE btoc(CUSTOMTOP-CUSTOMBASE)
173 1.1 mw #ifdef A3000
174 1.1 mw #define SCSIBASE (0x00DD0000)
175 1.1 mw #define SCSITOP (0x00DD0000+AMIGA_PAGE_SIZE)
176 1.1 mw #define SCSISIZE btoc(SCSITOP-SCSIBASE)
177 1.1 mw #endif
178 1.1 mw
179 1.1 mw /* XXX only correct for A3000 memory map!
180 1.1 mw * corresponds to address of last physical memory page, for A3000
181 1.1 mw * this is always 0x08000000 - pagesize (== NBPS)
182 1.1 mw */
183 1.1 mw #define MAXADDR (0x08000000 - UPAGES)
184 1.1 mw
185 1.1 mw
186 1.1 mw /* Amiga specific mappings:
187 1.1 mw *
188 1.1 mw * phys-start map-start phys-end map-end name
189 1.1 mw *
190 1.1 mw * 0x00000000 chipmembase - 0x00200000 chipmemlimit CHIP MEM
191 1.1 mw * 0x00be0000 ciabase - 0x00c00000 cialimit CIA-B/CIA-A
192 1.1 mw * 0x00d80000 customchipbase - 0x00f00000 customchiplimit CUSTOM/ZORRO2
193 1.1 mw */
194 1.1 mw #define ISCHIPMEM(va) \
195 1.1 mw ((char *)(va) >= chipmembase && (char *)(va) < chipmemlimit)
196 1.1 mw #define CHIPMEMV(pa) ((int)(pa)-CHIPMEMBASE+(int)chipmembase)
197 1.1 mw #define CHIPMEMP(va) ((int)(va)-(int)chipmembase+CHIPMEMBASE)
198 1.1 mw #define CHIPMEMPOFF(pa) ((int)(pa)-CHIPMEMBASE)
199 1.1 mw #define CHIPMEMMAPSIZE btoc(CHIPMEMTOP-CHIPMEMBASE) /* 2mb */
200 1.1 mw
201 1.1 mw #define ISCIA(va) \
202 1.1 mw ((char *)(va) >= ciabase && (char *)(va) < cialimit)
203 1.1 mw #define CIAV(pa) ((int)(pa)-CIABASE+(int)ciabase)
204 1.1 mw #define CIAP(va) ((int)(va)-(int)ciabase+CIABASE)
205 1.1 mw #define CIAPOFF(pa) ((int)(pa)-CIABASE)
206 1.1 mw #define CIAMAPSIZE btoc(CIATOP-CIABASE) /* 8k */
207 1.1 mw
208 1.1 mw #define ISCUSTOMCHIP(va) \
209 1.1 mw ((char *)(va) >= customchipbase && (char *)(va) < customchiplimit)
210 1.1 mw #define CUSTOMCHIPV(pa) ((int)(pa)-CUSTOMCHIPBASE+(int)customchipbase)
211 1.1 mw #define CUSTOMCHIPP(va) ((int)(va)-(int)customchipbase+CUSTOMCHIPBASE)
212 1.1 mw #define CUSTOMCHIPPOFF(pa) ((int)(pa)-CUSTOMCHIPBASE)
213 1.1 mw #define CUSTOMCHIPMAPSIZE btoc(CUSTOMCHIPTOP-CUSTOMCHIPBASE) /* 1.5mb */
214 1.1 mw
215 1.1 mw
216 1.1 mw /*
217 1.1 mw * 68851 and 68030 MMU
218 1.1 mw */
219 1.1 mw #define PMMU_LVLMASK 0x0007
220 1.1 mw #define PMMU_INV 0x0400
221 1.1 mw #define PMMU_WP 0x0800
222 1.1 mw #define PMMU_ALV 0x1000
223 1.1 mw #define PMMU_SO 0x2000
224 1.1 mw #define PMMU_LV 0x4000
225 1.1 mw #define PMMU_BE 0x8000
226 1.1 mw #define PMMU_FAULT (PMMU_WP|PMMU_INV)
227 1.1 mw
228 1.1 mw /* 680X0 function codes */
229 1.1 mw #define FC_USERD 1 /* user data space */
230 1.1 mw #define FC_USERP 2 /* user program space */
231 1.1 mw #define FC_SUPERD 5 /* supervisor data space */
232 1.1 mw #define FC_SUPERP 6 /* supervisor program space */
233 1.1 mw #define FC_CPU 7 /* CPU space */
234 1.1 mw
235 1.1 mw /* fields in the 68020 cache control register */
236 1.1 mw #define IC_ENABLE 0x0001 /* enable instruction cache */
237 1.1 mw #define IC_FREEZE 0x0002 /* freeze instruction cache */
238 1.1 mw #define IC_CE 0x0004 /* clear instruction cache entry */
239 1.1 mw #define IC_CLR 0x0008 /* clear entire instruction cache */
240 1.1 mw
241 1.1 mw /* additional fields in the 68030 cache control register */
242 1.1 mw #define IC_BE 0x0010 /* instruction burst enable */
243 1.1 mw #define DC_ENABLE 0x0100 /* data cache enable */
244 1.1 mw #define DC_FREEZE 0x0200 /* data cache freeze */
245 1.1 mw #define DC_CE 0x0400 /* clear data cache entry */
246 1.1 mw #define DC_CLR 0x0800 /* clear entire data cache */
247 1.1 mw #define DC_BE 0x1000 /* data burst enable */
248 1.1 mw #define DC_WA 0x2000 /* write allocate */
249 1.1 mw
250 1.1 mw #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
251 1.1 mw #define CACHE_OFF (DC_CLR|IC_CLR)
252 1.1 mw #define CACHE_CLR (CACHE_ON)
253 1.1 mw #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
254 1.1 mw #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
255