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cpu.h revision 1.11 
      1 /*
      2  * Copyright (c) 1988 University of Utah.
      3  * Copyright (c) 1982, 1990 The Regents of the University of California.
      4  * All rights reserved.
      5  *
      6  * This code is derived from software contributed to Berkeley by
      7  * the Systems Programming Group of the University of Utah Computer
      8  * Science Department.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the University of
     21  *	California, Berkeley and its contributors.
     22  * 4. Neither the name of the University nor the names of its contributors
     23  *    may be used to endorse or promote products derived from this software
     24  *    without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36  * SUCH DAMAGE.
     37  *
     38  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     39  *
     40  *	@(#)cpu.h	7.7 (Berkeley) 6/27/91
     41  *	$Id: cpu.h,v 1.11 1994/05/08 05:53:56 chopps Exp $
     42  */
     43 #ifndef _MACHINE_CPU_H_
     44 #define _MACHINE_CPU_H_
     45 
     46 /*
     47  * Exported definitions unique to amiga/68k cpu support.
     48  */
     49 
     50 /*
     51  * definitions of cpu-dependent requirements
     52  * referenced in generic code
     53  */
     54 #define	COPY_SIGCODE		/* copy sigcode above user stack in exec */
     55 
     56 /*
     57  * function vs. inline configuration;
     58  * these are defined to get generic functions
     59  * rather than inline or machine-dependent implementations
     60  */
     61 #define	NEED_MINMAX		/* need {,i,l,ul}{min,max} functions */
     62 #undef	NEED_FFS		/* don't need ffs function */
     63 #undef	NEED_BCMP		/* don't need bcmp function */
     64 #undef	NEED_STRLEN		/* don't need strlen function */
     65 
     66 #define	cpu_exec(p)	/* nothing */
     67 #define	cpu_wait(p)	/* nothing */
     68 
     69 /*
     70  * Arguments to hardclock, softclock and gatherstats
     71  * encapsulate the previous machine state in an opaque
     72  * clockframe; for hp300, use just what the hardware
     73  * leaves on the stack.
     74  *
     75  * which is now in this format.  note if m68k/frame.h
     76  * changes this may need too also.
     77  */
     78 struct clockframe {
     79 	int     ps;
     80 	int     pc;
     81 };
     82 
     83 
     84 #define	CLKF_USERMODE(framep)	(((framep)->ps & PSL_S) == 0)
     85 #define	CLKF_BASEPRI(framep)	(((framep)->ps & PSL_IPL7) == 0)
     86 #define	CLKF_PC(framep)		((framep)->pc)
     87 #define CLKF_INTR(framep)	(0)	/* XXXX*/
     88 
     89 /*
     90  * Preempt the current process if in interrupt from user mode,
     91  * or after the current trap/syscall if in system mode.
     92  */
     93 #define	need_resched()	{want_resched = 1; setsoftast();}
     94 
     95 /*
     96  * Give a profiling tick to the current process from the softclock
     97  * interrupt.  On hp300, request an ast to send us through trap(),
     98  * marking the proc as needing a profiling tick.
     99  */
    100 #define	profile_tick(p, framep)	((p)->p_flag |= P_OWEUPC, setsoftast())
    101 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, setsoftast())
    102 
    103 /*
    104  * Notify the current process (p) that it has a signal pending,
    105  * process as soon as possible.
    106  */
    107 #define	signotify(p)	setsoftast()
    108 
    109 #define setsoftast()	(astpending = 1)
    110 
    111 int	astpending;		/* need trap before returning to user mode */
    112 int	want_resched;		/* resched() was called */
    113 
    114 /*
    115  * simulated software interrupt register
    116  */
    117 extern unsigned char ssir;
    118 
    119 #define SIR_NET		0x1
    120 #define SIR_CLOCK	0x2
    121 
    122 #define siroff(x)	ssir &= ~(x)
    123 #define setsoftnet()	ssir |= SIR_NET
    124 #define setsoftclock()	ssir |= SIR_CLOCK
    125 
    126 
    127 /*
    128  * The rest of this should probably be moved to ../amiga/amigacpu.h,
    129  * although some of it could probably be put into generic 68k headers.
    130  */
    131 
    132 /* values for machineid (happen to be AFF_* settings of AttnFlags)
    133  * NOTE: '40 support does exist! */
    134 #define AMIGA_68020	(1L<<1)
    135 #define AMIGA_68030	(1L<<2)
    136 #define AMIGA_68040	(1L<<3)
    137 #define AMIGA_68881	(1L<<4)
    138 #define AMIGA_68882	(1L<<5)
    139 #define	AMIGA_FPU40	(1L<<6)
    140 
    141 
    142 /* values for mmutype (assigned for quick testing) */
    143 #define	MMU_68030	-1	/* 68030 on-chip subset of 68851 */
    144 #define	MMU_68851	1	/* Motorola 68851 */
    145 #define MMU_68040	0	/* 68040 on-chip subsubset */
    146 
    147 /* values for cpuspeed (not really related to clock speed due to caches) */
    148 #define	MHZ_8		1
    149 #define	MHZ_16		2
    150 #define	MHZ_25		3
    151 #define	MHZ_33		4
    152 #define	MHZ_50		6
    153 
    154 #ifdef KERNEL
    155 extern	int machineid, mmutype, cpu040;
    156 
    157 /* what is this supposed to do? i.e. how is it different than startrtclock?
    158    #define	enablertclock()
    159 
    160    Answer (MW): startrtclock is supposed to start the clock chip (to get an
    161    accurate uptime, enablertclock is called later (after *vital* stuff
    162    has been setup) to enable clock interrupts. Enabling clock interrupts
    163    at startrtclock-time can get you into big troubles...  */
    164 
    165 #endif
    166 
    167 /* physical memory sections */
    168 #define CHIPMEMBASE	(0x00000000)
    169 /* maximum for mapping, not the whole range is needed in physical equivalence */
    170 #define CHIPMEMTOP	(0x00200000)
    171 #define CHIPMEMSIZE	btoc(CHIPMEMTOP-CHIPMEMBASE)
    172 /* CIA-A and CIA-B */
    173 #define CIABASE		(0x00BFC000)
    174 #define CIATOP		(0x00C00000)
    175 #define CIASIZE		btoc(CIATOP-CIABASE)
    176 #if 0
    177 #define CUSTOMBASE	(0x00DFE000)
    178 #define CUSTOMTOP	(0x00E00000)
    179 #define CUSTOMSIZE	btoc(CUSTOMTOP-CUSTOMBASE)
    180 #ifdef A3000
    181 #define SCSIBASE	(0x00DD0000)
    182 #define SCSITOP		(0x00DD0000+AMIGA_PAGE_SIZE)
    183 #define SCSISIZE	btoc(SCSITOP-SCSIBASE)
    184 #endif
    185 #else
    186 /* zorro2 really starts at 0x00E00000, but starting mapping at D8 also
    187    includes the clock and scsi space on the A3000, as well as the
    188    normal custom chip area on any amiga. That's nice :-)) */
    189 #define CUSTOMBASE	(0x00DFF000)	/* now just offset rel to zorro2 */
    190 #endif
    191 
    192 /* XXX only correct for A3000 memory map!
    193  * corresponds to address of last physical memory page, for A3000
    194  * this is always 0x08000000 - pagesize (== NBPS)
    195  */
    196 #define MAXADDR		(0x08000000 - UPAGES)
    197 
    198 
    199 #if 0
    200 /* these are not used, verbatim from hp300, but not used :-)) */
    201 
    202 /* Amiga specific mappings:
    203  *
    204  * phys-start	map-start	  phys-end	map-end		name
    205  *
    206  * 0x00000000	chipmembase	- 0x00200000	chipmemlimit	CHIP MEM
    207  * 0x00be0000	ciabase		- 0x00c00000	cialimit	CIA-B/CIA-A
    208  * 0x00d80000	customchipbase	- 0x00f00000	customchiplimit	CUSTOM/ZTWO
    209  */
    210 #define ISCHIPMEM(va) \
    211 	((char *)(va) >= chipmembase && (char *)(va) < chipmemlimit)
    212 #define	CHIPMEMV(pa)	((int)(pa)-CHIPMEMBASE+(int)chipmembase)
    213 #define	CHIPMEMP(va)	((int)(va)-(int)chipmembase+CHIPMEMBASE)
    214 #define	CHIPMEMPOFF(pa)	((int)(pa)-CHIPMEMBASE)
    215 #define	CHIPMEMMAPSIZE	btoc(CHIPMEMTOP-CHIPMEMBASE)	/* 2mb */
    216 
    217 #define ISCIA(va) \
    218 	((char *)(va) >= ciabase && (char *)(va) < cialimit)
    219 #define	CIAV(pa)	((int)(pa)-CIABASE+(int)ciabase)
    220 #define	CIAP(va)	((int)(va)-(int)ciabase+CIABASE)
    221 #define	CIAPOFF(pa)	((int)(pa)-CIABASE)
    222 #define	CIAMAPSIZE	btoc(CIATOP-CIABASE)	/* 8k */
    223 
    224 #define ISCUSTOMCHIP(va) \
    225 	((char *)(va) >= customchipbase && (char *)(va) < customchiplimit)
    226 #define	CUSTOMCHIPV(pa)	((int)(pa)-CUSTOMCHIPBASE+(int)customchipbase)
    227 #define	CUSTOMCHIPP(va)	((int)(va)-(int)customchipbase+CUSTOMCHIPBASE)
    228 #define	CUSTOMCHIPPOFF(pa)	((int)(pa)-CUSTOMCHIPBASE)
    229 #define	CUSTOMCHIPMAPSIZE	btoc(CUSTOMCHIPTOP-CUSTOMCHIPBASE)	/* 1.5mb */
    230 #endif
    231 
    232 
    233 /*
    234  * 68851 and 68030 MMU
    235  */
    236 #define	PMMU_LVLMASK	0x0007
    237 #define	PMMU_INV	0x0400
    238 #define	PMMU_WP		0x0800
    239 #define	PMMU_ALV	0x1000
    240 #define	PMMU_SO		0x2000
    241 #define	PMMU_LV		0x4000
    242 #define	PMMU_BE		0x8000
    243 #define	PMMU_FAULT	(PMMU_WP|PMMU_INV)
    244 
    245 /* 680X0 function codes */
    246 #define	FC_USERD	1	/* user data space */
    247 #define	FC_USERP	2	/* user program space */
    248 #define	FC_SUPERD	5	/* supervisor data space */
    249 #define	FC_SUPERP	6	/* supervisor program space */
    250 #define	FC_CPU		7	/* CPU space */
    251 
    252 /* fields in the 68020 cache control register */
    253 #define	IC_ENABLE	0x0001	/* enable instruction cache */
    254 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
    255 #define	IC_CE		0x0004	/* clear instruction cache entry */
    256 #define	IC_CLR		0x0008	/* clear entire instruction cache */
    257 
    258 /* additional fields in the 68030 cache control register */
    259 #define	IC_BE		0x0010	/* instruction burst enable */
    260 #define	DC_ENABLE	0x0100	/* data cache enable */
    261 #define	DC_FREEZE	0x0200	/* data cache freeze */
    262 #define	DC_CE		0x0400	/* clear data cache entry */
    263 #define	DC_CLR		0x0800	/* clear entire data cache */
    264 #define	DC_BE		0x1000	/* data burst enable */
    265 #define	DC_WA		0x2000	/* write allocate */
    266 
    267 /* fields in the 68040 cache control register */
    268 #define	IC40_ENABLE	0x00008000	/* enable instruction cache */
    269 #define DC40_ENABLE	0x80000000	/* enable data cache */
    270 
    271 #define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    272 #define	CACHE_OFF	(DC_CLR|IC_CLR)
    273 #define	CACHE_CLR	(CACHE_ON)
    274 #define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    275 #define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
    276 
    277 /* 68040 cache control */
    278 #define	CACHE40_ON	(IC40_ENABLE|DC40_ENABLE)
    279 #define	CACHE40_OFF	0x00000000
    280 
    281 #endif /* !_MACHINE_CPU_H_ */
    282