cpu.h revision 1.14
1 /* 2 * Copyright (c) 1988 University of Utah. 3 * Copyright (c) 1982, 1990 The Regents of the University of California. 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * the Systems Programming Group of the University of Utah Computer 8 * Science Department. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 39 * 40 * @(#)cpu.h 7.7 (Berkeley) 6/27/91 41 * $Id: cpu.h,v 1.14 1994/06/04 11:59:25 chopps Exp $ 42 */ 43 #ifndef _MACHINE_CPU_H_ 44 #define _MACHINE_CPU_H_ 45 46 /* 47 * Exported definitions unique to amiga/68k cpu support. 48 */ 49 50 /* 51 * definitions of cpu-dependent requirements 52 * referenced in generic code 53 */ 54 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 55 56 #define cpu_exec(p) /* nothing */ 57 #define cpu_swapin(p) /* nothing */ 58 #define cpu_wait(p) /* nothing */ 59 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 60 #define cpu_set_init_frame(p, fp) (p)->p_md.md_regs = fp 61 62 /* 63 * Arguments to hardclock and gatherstats encapsulate the previous 64 * machine state in an opaque clockframe. One the hp300, we use 65 * what the hardware pushes on an interrupt (frame format 0). 66 */ 67 struct clockframe { 68 u_short sr; /* sr at time of interrupt */ 69 u_long pc; /* pc at time of interrupt */ 70 u_short vo; /* vector offset (4-word frame) */ 71 }; 72 73 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 74 #define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0) 75 #define CLKF_PC(framep) ((framep)->pc) 76 #if 0 77 /* We would like to do it this way... */ 78 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 79 #else 80 /* but until we start using PSL_M, we have to do this instead */ 81 #define CLKF_INTR(framep) (0) /* XXX */ 82 #endif 83 84 85 /* 86 * Preempt the current process if in interrupt from user mode, 87 * or after the current trap/syscall if in system mode. 88 */ 89 #define need_resched() {want_resched = 1; setsoftast();} 90 91 /* 92 * Give a profiling tick to the current process from the softclock 93 * interrupt. On hp300, request an ast to send us through trap(), 94 * marking the proc as needing a profiling tick. 95 */ 96 #define profile_tick(p, framep) ((p)->p_flag |= P_OWEUPC, setsoftast()) 97 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, setsoftast()) 98 99 /* 100 * Notify the current process (p) that it has a signal pending, 101 * process as soon as possible. 102 */ 103 #define signotify(p) setsoftast() 104 105 #define setsoftast() (astpending = 1) 106 107 int astpending; /* need trap before returning to user mode */ 108 int want_resched; /* resched() was called */ 109 110 /* 111 * simulated software interrupt register 112 */ 113 extern unsigned char ssir; 114 115 #define SIR_NET 0x1 116 #define SIR_CLOCK 0x2 117 118 #define siroff(x) ssir &= ~(x) 119 #define setsoftnet() ssir |= SIR_NET 120 #define setsoftclock() ssir |= SIR_CLOCK 121 122 123 /* 124 * The rest of this should probably be moved to ../amiga/amigacpu.h, 125 * although some of it could probably be put into generic 68k headers. 126 */ 127 128 /* values for machineid (happen to be AFF_* settings of AttnFlags) 129 * NOTE: '40 support does exist! */ 130 #define AMIGA_68020 (1L<<1) 131 #define AMIGA_68030 (1L<<2) 132 #define AMIGA_68040 (1L<<3) 133 #define AMIGA_68881 (1L<<4) 134 #define AMIGA_68882 (1L<<5) 135 #define AMIGA_FPU40 (1L<<6) 136 137 138 /* values for mmutype (assigned for quick testing) */ 139 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 140 #define MMU_68851 1 /* Motorola 68851 */ 141 #define MMU_68040 -2 /* 68040 on-chip subsubset */ 142 143 /* values for cpuspeed (not really related to clock speed due to caches) */ 144 #define MHZ_8 1 145 #define MHZ_16 2 146 #define MHZ_25 3 147 #define MHZ_33 4 148 #define MHZ_50 6 149 150 #ifdef KERNEL 151 int machineid, mmutype, cpu040; 152 #endif 153 154 /* 155 * 68851 and 68030 MMU 156 */ 157 #define PMMU_LVLMASK 0x0007 158 #define PMMU_INV 0x0400 159 #define PMMU_WP 0x0800 160 #define PMMU_ALV 0x1000 161 #define PMMU_SO 0x2000 162 #define PMMU_LV 0x4000 163 #define PMMU_BE 0x8000 164 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 165 166 /* 680X0 function codes */ 167 #define FC_USERD 1 /* user data space */ 168 #define FC_USERP 2 /* user program space */ 169 #define FC_SUPERD 5 /* supervisor data space */ 170 #define FC_SUPERP 6 /* supervisor program space */ 171 #define FC_CPU 7 /* CPU space */ 172 173 /* fields in the 68020 cache control register */ 174 #define IC_ENABLE 0x0001 /* enable instruction cache */ 175 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 176 #define IC_CE 0x0004 /* clear instruction cache entry */ 177 #define IC_CLR 0x0008 /* clear entire instruction cache */ 178 179 /* additional fields in the 68030 cache control register */ 180 #define IC_BE 0x0010 /* instruction burst enable */ 181 #define DC_ENABLE 0x0100 /* data cache enable */ 182 #define DC_FREEZE 0x0200 /* data cache freeze */ 183 #define DC_CE 0x0400 /* clear data cache entry */ 184 #define DC_CLR 0x0800 /* clear entire data cache */ 185 #define DC_BE 0x1000 /* data burst enable */ 186 #define DC_WA 0x2000 /* write allocate */ 187 188 /* fields in the 68040 cache control register */ 189 #define IC40_ENABLE 0x00008000 /* enable instruction cache */ 190 #define DC40_ENABLE 0x80000000 /* enable data cache */ 191 192 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 193 #define CACHE_OFF (DC_CLR|IC_CLR) 194 #define CACHE_CLR (CACHE_ON) 195 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 196 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 197 198 /* 68040 cache control */ 199 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 200 #define CACHE40_OFF 0x00000000 201 202 /* 203 * CTL_MACHDEP definitions. 204 */ 205 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 206 #define CPU_MAXID 2 /* number of valid machdep ids */ 207 208 #define CTL_MACHDEP_NAMES { \ 209 { 0, 0 }, \ 210 { "console_device", CTLTYPE_STRUCT }, \ 211 } 212 213 #endif /* !_MACHINE_CPU_H_ */ 214
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