cpu.h revision 1.23
1 /* $NetBSD: cpu.h,v 1.23 1995/06/28 02:55:31 cgd Exp $ */ 2 3 /* 4 * Copyright (c) 1988 University of Utah. 5 * Copyright (c) 1982, 1990 The Regents of the University of California. 6 * All rights reserved. 7 * 8 * This code is derived from software contributed to Berkeley by 9 * the Systems Programming Group of the University of Utah Computer 10 * Science Department. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the University of 23 * California, Berkeley and its contributors. 24 * 4. Neither the name of the University nor the names of its contributors 25 * may be used to endorse or promote products derived from this software 26 * without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 * 40 * from: Utah $Hdr: cpu.h 1.16 91/03/25$ 41 * 42 * @(#)cpu.h 7.7 (Berkeley) 6/27/91 43 */ 44 #ifndef _MACHINE_CPU_H_ 45 #define _MACHINE_CPU_H_ 46 47 /* 48 * Exported definitions unique to amiga/68k cpu support. 49 */ 50 51 /* 52 * definitions of cpu-dependent requirements 53 * referenced in generic code 54 */ 55 #define cpu_swapin(p) /* nothing */ 56 #define cpu_wait(p) /* nothing */ 57 #define cpu_setstack(p, ap) (p)->p_md.md_regs[SP] = ap 58 #define cpu_swapout(p) /* nothing */ 59 60 /* 61 * Arguments to hardclock and gatherstats encapsulate the previous 62 * machine state in an opaque clockframe. One the hp300, we use 63 * what the hardware pushes on an interrupt (frame format 0). 64 */ 65 struct clockframe { 66 u_short sr; /* sr at time of interrupt */ 67 u_long pc; /* pc at time of interrupt */ 68 u_short vo; /* vector offset (4-word frame) */ 69 }; 70 71 #define CLKF_USERMODE(framep) (((framep)->sr & PSL_S) == 0) 72 /*#define CLKF_BASEPRI(framep) (((framep)->sr & PSL_IPL) == 0)*/ 73 #define CLKF_BASEPRI(framep) (0) 74 #define CLKF_PC(framep) ((framep)->pc) 75 #if 0 76 /* We would like to do it this way... */ 77 #define CLKF_INTR(framep) (((framep)->sr & PSL_M) == 0) 78 #else 79 /* but until we start using PSL_M, we have to do this instead */ 80 #define CLKF_INTR(framep) (0) /* XXX */ 81 #endif 82 83 84 /* 85 * Preempt the current process if in interrupt from user mode, 86 * or after the current trap/syscall if in system mode. 87 */ 88 #define need_resched() {want_resched = 1; setsoftast();} 89 90 /* 91 * Give a profiling tick to the current process from the softclock 92 * interrupt. On hp300, request an ast to send us through trap(), 93 * marking the proc as needing a profiling tick. 94 */ 95 #define profile_tick(p, framep) ((p)->p_flag |= P_OWEUPC, setsoftast()) 96 #define need_proftick(p) ((p)->p_flag |= P_OWEUPC, setsoftast()) 97 98 /* 99 * Notify the current process (p) that it has a signal pending, 100 * process as soon as possible. 101 */ 102 #define signotify(p) setsoftast() 103 104 #define setsoftast() (astpending = 1) 105 106 int astpending; /* need trap before returning to user mode */ 107 int want_resched; /* resched() was called */ 108 109 /* include support for software interrupts */ 110 #include <machine/mtpr.h> 111 112 /* 113 * The rest of this should probably be moved to ../amiga/amigacpu.h, 114 * although some of it could probably be put into generic 68k headers. 115 */ 116 117 /* values for machineid (happen to be AFF_* settings of AttnFlags) */ 118 #define AMIGA_68020 (1L<<1) 119 #define AMIGA_68030 (1L<<2) 120 #define AMIGA_68040 (1L<<3) 121 #define AMIGA_68881 (1L<<4) 122 #define AMIGA_68882 (1L<<5) 123 #define AMIGA_FPU40 (1L<<6) 124 125 /* values for fputype */ 126 #define FPU_NONE 0 127 #define FPU_68881 1 128 #define FPU_68882 2 129 #define FPU_68040 3 130 131 /* values for mmutype (assigned for quick testing) */ 132 #define MMU_68030 -1 /* 68030 on-chip subset of 68851 */ 133 #define MMU_68851 1 /* Motorola 68851 */ 134 #define MMU_68040 -2 /* 68040 on-chip subsubset */ 135 136 #ifdef _KERNEL 137 int machineid, mmutype, cpu040, fputype; 138 #endif 139 140 /* 141 * 68851 and 68030 MMU 142 */ 143 #define PMMU_LVLMASK 0x0007 144 #define PMMU_INV 0x0400 145 #define PMMU_WP 0x0800 146 #define PMMU_ALV 0x1000 147 #define PMMU_SO 0x2000 148 #define PMMU_LV 0x4000 149 #define PMMU_BE 0x8000 150 #define PMMU_FAULT (PMMU_WP|PMMU_INV) 151 152 /* 680X0 function codes */ 153 #define FC_USERD 1 /* user data space */ 154 #define FC_USERP 2 /* user program space */ 155 #define FC_SUPERD 5 /* supervisor data space */ 156 #define FC_SUPERP 6 /* supervisor program space */ 157 #define FC_CPU 7 /* CPU space */ 158 159 /* fields in the 68020 cache control register */ 160 #define IC_ENABLE 0x0001 /* enable instruction cache */ 161 #define IC_FREEZE 0x0002 /* freeze instruction cache */ 162 #define IC_CE 0x0004 /* clear instruction cache entry */ 163 #define IC_CLR 0x0008 /* clear entire instruction cache */ 164 165 /* additional fields in the 68030 cache control register */ 166 #define IC_BE 0x0010 /* instruction burst enable */ 167 #define DC_ENABLE 0x0100 /* data cache enable */ 168 #define DC_FREEZE 0x0200 /* data cache freeze */ 169 #define DC_CE 0x0400 /* clear data cache entry */ 170 #define DC_CLR 0x0800 /* clear entire data cache */ 171 #define DC_BE 0x1000 /* data burst enable */ 172 #define DC_WA 0x2000 /* write allocate */ 173 174 /* fields in the 68040 cache control register */ 175 #define IC40_ENABLE 0x00008000 /* enable instruction cache */ 176 #define DC40_ENABLE 0x80000000 /* enable data cache */ 177 178 #define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 179 #define CACHE_OFF (DC_CLR|IC_CLR) 180 #define CACHE_CLR (CACHE_ON) 181 #define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE) 182 #define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE) 183 184 /* 68040 cache control */ 185 #define CACHE40_ON (IC40_ENABLE|DC40_ENABLE) 186 #define CACHE40_OFF 0x00000000 187 188 /* 189 * CTL_MACHDEP definitions. 190 */ 191 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 192 #define CPU_MAXID 2 /* number of valid machdep ids */ 193 194 #define CTL_MACHDEP_NAMES { \ 195 { 0, 0 }, \ 196 { "console_device", CTLTYPE_STRUCT }, \ 197 } 198 199 #endif /* !_MACHINE_CPU_H_ */ 200
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