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cpu.h revision 1.30 
      1 /*	$NetBSD: cpu.h,v 1.30 1996/04/23 22:54:49 veego Exp $	*/
      2 
      3 /*
      4  * Copyright (c) 1988 University of Utah.
      5  * Copyright (c) 1982, 1990 The Regents of the University of California.
      6  * All rights reserved.
      7  *
      8  * This code is derived from software contributed to Berkeley by
      9  * the Systems Programming Group of the University of Utah Computer
     10  * Science Department.
     11  *
     12  * Redistribution and use in source and binary forms, with or without
     13  * modification, are permitted provided that the following conditions
     14  * are met:
     15  * 1. Redistributions of source code must retain the above copyright
     16  *    notice, this list of conditions and the following disclaimer.
     17  * 2. Redistributions in binary form must reproduce the above copyright
     18  *    notice, this list of conditions and the following disclaimer in the
     19  *    documentation and/or other materials provided with the distribution.
     20  * 3. All advertising materials mentioning features or use of this software
     21  *    must display the following acknowledgement:
     22  *	This product includes software developed by the University of
     23  *	California, Berkeley and its contributors.
     24  * 4. Neither the name of the University nor the names of its contributors
     25  *    may be used to endorse or promote products derived from this software
     26  *    without specific prior written permission.
     27  *
     28  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     29  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     30  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     31  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     32  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     33  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     34  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     36  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     37  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     38  * SUCH DAMAGE.
     39  *
     40  * from: Utah $Hdr: cpu.h 1.16 91/03/25$
     41  *
     42  *	@(#)cpu.h	7.7 (Berkeley) 6/27/91
     43  */
     44 #ifndef _MACHINE_CPU_H_
     45 #define _MACHINE_CPU_H_
     46 
     47 /*
     48  * Exported definitions unique to amiga/68k cpu support.
     49  */
     50 
     51 /*
     52  * definitions of cpu-dependent requirements
     53  * referenced in generic code
     54  */
     55 #define	cpu_swapin(p)			/* nothing */
     56 #define	cpu_wait(p)			/* nothing */
     57 #define	cpu_swapout(p)			/* nothing */
     58 
     59 /*
     60  * Arguments to hardclock and gatherstats encapsulate the previous
     61  * machine state in an opaque clockframe.  One the hp300, we use
     62  * what the hardware pushes on an interrupt (frame format 0).
     63  */
     64 struct clockframe {
     65 	u_short	sr;		/* sr at time of interrupt */
     66 	u_long	pc;		/* pc at time of interrupt */
     67 	u_short	vo;		/* vector offset (4-word frame) */
     68 };
     69 
     70 #define	CLKF_USERMODE(framep)	(((framep)->sr & PSL_S) == 0)
     71 /*#define	CLKF_BASEPRI(framep)	(((framep)->sr & PSL_IPL) == 0)*/
     72 #define	CLKF_BASEPRI(framep)	(0)
     73 #define	CLKF_PC(framep)		((framep)->pc)
     74 #if 0
     75 /* We would like to do it this way... */
     76 #define	CLKF_INTR(framep)	(((framep)->sr & PSL_M) == 0)
     77 #else
     78 /* but until we start using PSL_M, we have to do this instead */
     79 #define	CLKF_INTR(framep)	(0)	/* XXX */
     80 #endif
     81 
     82 
     83 /*
     84  * Preempt the current process if in interrupt from user mode,
     85  * or after the current trap/syscall if in system mode.
     86  */
     87 #define	need_resched()	{want_resched = 1; setsoftast();}
     88 
     89 /*
     90  * Give a profiling tick to the current process from the softclock
     91  * interrupt.  On hp300, request an ast to send us through trap(),
     92  * marking the proc as needing a profiling tick.
     93  */
     94 #define	profile_tick(p, framep)	((p)->p_flag |= P_OWEUPC, setsoftast())
     95 #define	need_proftick(p)	((p)->p_flag |= P_OWEUPC, setsoftast())
     96 
     97 /*
     98  * Notify the current process (p) that it has a signal pending,
     99  * process as soon as possible.
    100  */
    101 #define	signotify(p)	setsoftast()
    102 
    103 #define setsoftast()	(astpending = 1)
    104 
    105 int	astpending;		/* need trap before returning to user mode */
    106 int	want_resched;		/* resched() was called */
    107 
    108 /* include support for software interrupts */
    109 #include <machine/mtpr.h>
    110 
    111 /*
    112  * The rest of this should probably be moved to ../amiga/amigacpu.h,
    113  * although some of it could probably be put into generic 68k headers.
    114  */
    115 
    116 /* values for machineid (happen to be AFF_* settings of AttnFlags) */
    117 #define AMIGA_68020	(1L<<1)
    118 #define AMIGA_68030	(1L<<2)
    119 #define AMIGA_68040	(1L<<3)
    120 #define AMIGA_68881	(1L<<4)
    121 #define AMIGA_68882	(1L<<5)
    122 #define	AMIGA_FPU40	(1L<<6)
    123 #define AMIGA_68060	(1L<<7)
    124 
    125 /* values for fputype */
    126 #define FPU_NONE	0
    127 #define FPU_68881	1
    128 #define FPU_68882	2
    129 #define FPU_68040	3
    130 
    131 /* values for mmutype (assigned for quick testing) */
    132 #define	MMU_68030	-1	/* 68030 on-chip subset of 68851 */
    133 #define	MMU_68851	1	/* Motorola 68851 */
    134 #define MMU_68040	-2	/* 68040 on-chip subsubset */
    135 
    136 #ifdef _KERNEL
    137 int machineid, mmutype, fputype;
    138 #endif
    139 
    140 /*
    141  * 68851 and 68030 MMU
    142  */
    143 #define	PMMU_LVLMASK	0x0007
    144 #define	PMMU_INV	0x0400
    145 #define	PMMU_WP		0x0800
    146 #define	PMMU_ALV	0x1000
    147 #define	PMMU_SO		0x2000
    148 #define	PMMU_LV		0x4000
    149 #define	PMMU_BE		0x8000
    150 #define	PMMU_FAULT	(PMMU_WP|PMMU_INV)
    151 
    152 /* 680X0 function codes */
    153 #define	FC_USERD	1	/* user data space */
    154 #define	FC_USERP	2	/* user program space */
    155 #define	FC_SUPERD	5	/* supervisor data space */
    156 #define	FC_SUPERP	6	/* supervisor program space */
    157 #define	FC_CPU		7	/* CPU space */
    158 
    159 /* fields in the 68020 cache control register */
    160 #define	IC_ENABLE	0x0001	/* enable instruction cache */
    161 #define	IC_FREEZE	0x0002	/* freeze instruction cache */
    162 #define	IC_CE		0x0004	/* clear instruction cache entry */
    163 #define	IC_CLR		0x0008	/* clear entire instruction cache */
    164 
    165 /* additional fields in the 68030 cache control register */
    166 #define	IC_BE		0x0010	/* instruction burst enable */
    167 #define	DC_ENABLE	0x0100	/* data cache enable */
    168 #define	DC_FREEZE	0x0200	/* data cache freeze */
    169 #define	DC_CE		0x0400	/* clear data cache entry */
    170 #define	DC_CLR		0x0800	/* clear entire data cache */
    171 #define	DC_BE		0x1000	/* data burst enable */
    172 #define	DC_WA		0x2000	/* write allocate */
    173 
    174 /* fields in the 68040 cache control register */
    175 #define	IC40_ENABLE	0x00008000	/* enable instruction cache */
    176 #define DC40_ENABLE	0x80000000	/* enable data cache */
    177 
    178 /* additional fields in the 68060 cache control register */
    179 
    180 #define DC60_NAD	0x40000000	/* no allocate mode, data cache */
    181 #define DC60_ESB	0x20000000	/* enable store buffer */
    182 #define DC60_DPI	0x10000000	/* disable CPUSH invalidation */
    183 #define DC60_FOC	0x08000000	/* four kB data cache mode (else 8) */
    184 
    185 #define IC60_EBC	0x00800000	/* enable branch cache */
    186 #define IC60_CABC	0x00400000	/* clear all branch cache entries */
    187 #define IC60_CUBC	0x00200000	/* clear user branch cache entries */
    188 
    189 #define IC60_NAI	0x00004000	/* no allocate mode, instr. cache */
    190 #define IC60_FIC	0x00002000	/* four kB instr. cache (else 8) */
    191 
    192 
    193 #define	CACHE_ON	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    194 #define	CACHE_OFF	(DC_CLR|IC_CLR)
    195 #define	CACHE_CLR	(CACHE_ON)
    196 #define	IC_CLEAR	(DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
    197 #define	DC_CLEAR	(DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
    198 
    199 /* 68040 cache control */
    200 #define	CACHE40_ON	(IC40_ENABLE|DC40_ENABLE)
    201 #define	CACHE40_OFF	0x00000000
    202 
    203 #define CACHE60_ON	(CACHE40_ON |IC60_CABC|IC60_EBC|DC60_ESB)
    204 #define CACHE60_OFF	(CACHE40_OFF|IC60_CABC)
    205 
    206 /*
    207  * CTL_MACHDEP definitions.
    208  */
    209 #define CPU_CONSDEV	1	/* dev_t: console terminal device */
    210 #define CPU_MAXID	2	/* number of valid machdep ids */
    211 
    212 #define CTL_MACHDEP_NAMES { \
    213 	{ 0, 0 }, \
    214 	{ "console_device", CTLTYPE_STRUCT }, \
    215 }
    216 
    217 #ifdef _KERNEL
    218 /*
    219  * Prototypes from amiga_init.c
    220  */
    221 void	*alloc_z2mem __P((long));
    222 
    223 /*
    224  * Prototypes from autoconf.c
    225  */
    226 void	configure __P((void));
    227 int	is_a1200 __P((void));
    228 int	is_a3000 __P((void));
    229 int	is_a4000 __P((void));
    230 
    231 /*
    232  * Prototypes from clock.c
    233  */
    234 u_long	clkread __P((void));
    235 
    236 /*
    237  * Prototypes from locore.s
    238  */
    239 struct fpframe;
    240 struct user;
    241 struct pcb;
    242 
    243 void	clearseg __P((vm_offset_t));
    244 void	doboot __P((void));
    245 u_long	getdfc __P((void));
    246 u_long	getsfc __P((void));
    247 void	loadustp __P((int));
    248 #ifdef FPCOPROC
    249 void	m68881_save __P((struct fpframe *));
    250 void	m68881_restore __P((struct fpframe *));
    251 #endif
    252 void	physcopyseg __P((vm_offset_t, vm_offset_t));
    253 u_int	probeva __P((u_int, u_int));
    254 void	proc_trampoline __P((void));
    255 void	savectx __P((struct pcb *));
    256 void	switch_exit __P((struct proc *));
    257 void	DCIAS __P((vm_offset_t));
    258 void	DCIS __P((void));
    259 void	DCIU __P((void));
    260 void	ICIA __P((void));
    261 void	ICPA __P((void));
    262 void	PCIA __P((void));
    263 void	TBIA __P((void));
    264 void	TBIS __P((vm_offset_t));
    265 void	TBIAS __P((void));
    266 void	TBIAU __P((void));
    267 #ifdef M68040
    268 void	DCFA __P((void));
    269 void	DCFP __P((vm_offset_t));
    270 void	DCFL __P((vm_offset_t));
    271 void	DCPL __P((vm_offset_t));
    272 void	DCPP __P((vm_offset_t));
    273 void	ICPL __P((vm_offset_t));
    274 void	ICPP __P((vm_offset_t));
    275 #endif
    276 
    277 /*
    278  * Prototypes from machdep.c
    279  */
    280 int	badaddr __P((caddr_t));
    281 int	badbaddr __P((caddr_t));
    282 void	bootsync __P((void));
    283 void	dumpconf __P((void));
    284 struct frame;
    285 void	regdump __P((struct frame *, int));
    286 
    287 /*
    288  * Prototypes from sys_machdep.c:
    289  */
    290 int	cachectl __P((int, caddr_t, int));
    291 int	dma_cachectl __P((caddr_t, int));
    292 
    293 /*
    294  * Prototypes from vm_machdep.c
    295  */
    296 int	kvtop __P((caddr_t));
    297 void	physaccess __P((caddr_t,  caddr_t, int, int));
    298 void	physunaccess __P((caddr_t, int));
    299 void	setredzone __P((u_int *, caddr_t));
    300 
    301 /*
    302  * Prototypes from swapgeneric.c:
    303  */
    304 void	setconf __P((void));
    305 
    306 /*
    307  * Prototypes from pmap.c:
    308  */
    309 void	pmap_bootstrap __P((vm_offset_t, vm_offset_t));
    310 
    311 #endif /* _KERNEL */
    312 
    313 #endif /* !_MACHINE_CPU_H_ */
    314