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pte.h revision 1.7
      1  1.1      mw /*
      2  1.1      mw  * Copyright (c) 1988 University of Utah.
      3  1.1      mw  * Copyright (c) 1982, 1986, 1990 The Regents of the University of California.
      4  1.1      mw  * All rights reserved.
      5  1.1      mw  *
      6  1.1      mw  * This code is derived from software contributed to Berkeley by
      7  1.1      mw  * the Systems Programming Group of the University of Utah Computer
      8  1.1      mw  * Science Department.
      9  1.1      mw  *
     10  1.1      mw  * Redistribution and use in source and binary forms, with or without
     11  1.1      mw  * modification, are permitted provided that the following conditions
     12  1.1      mw  * are met:
     13  1.1      mw  * 1. Redistributions of source code must retain the above copyright
     14  1.1      mw  *    notice, this list of conditions and the following disclaimer.
     15  1.1      mw  * 2. Redistributions in binary form must reproduce the above copyright
     16  1.1      mw  *    notice, this list of conditions and the following disclaimer in the
     17  1.1      mw  *    documentation and/or other materials provided with the distribution.
     18  1.1      mw  * 3. All advertising materials mentioning features or use of this software
     19  1.1      mw  *    must display the following acknowledgement:
     20  1.1      mw  *	This product includes software developed by the University of
     21  1.1      mw  *	California, Berkeley and its contributors.
     22  1.1      mw  * 4. Neither the name of the University nor the names of its contributors
     23  1.1      mw  *    may be used to endorse or promote products derived from this software
     24  1.1      mw  *    without specific prior written permission.
     25  1.1      mw  *
     26  1.1      mw  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     27  1.1      mw  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     28  1.1      mw  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     29  1.1      mw  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     30  1.1      mw  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     31  1.1      mw  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     32  1.1      mw  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     33  1.1      mw  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     34  1.1      mw  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     35  1.1      mw  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     36  1.1      mw  * SUCH DAMAGE.
     37  1.1      mw  *
     38  1.1      mw  * from: Utah $Hdr: pte.h 1.11 89/09/03$
     39  1.1      mw  *
     40  1.1      mw  *	@(#)pte.h	7.3 (Berkeley) 5/8/91
     41  1.7  chopps  *	$Id: pte.h,v 1.7 1994/06/04 05:25:03 chopps Exp $
     42  1.1      mw  */
     43  1.4  chopps #ifndef _MACHINE_PTE_H_
     44  1.4  chopps #define _MACHINE_PTE_H_
     45  1.1      mw 
     46  1.1      mw /*
     47  1.1      mw  * AMIGA hardware segment/page table entries
     48  1.1      mw  */
     49  1.1      mw 
     50  1.1      mw struct ste {
     51  1.1      mw 	unsigned int	sg_pfnum:20;	/* page table frame number */
     52  1.1      mw 	unsigned int	:8;		/* reserved at 0 */
     53  1.1      mw 	unsigned int	:1;		/* reserved at 1 */
     54  1.1      mw 	unsigned int	sg_prot:1;	/* write protect bit */
     55  1.1      mw 	unsigned int	sg_v:2;		/* valid bits */
     56  1.1      mw };
     57  1.1      mw 
     58  1.1      mw struct pte {
     59  1.1      mw 	unsigned int	pg_pfnum:20;	/* page frame number or 0 */
     60  1.1      mw 	unsigned int	:3;
     61  1.1      mw 	unsigned int	pg_w:1;		/* is wired */
     62  1.1      mw 	unsigned int	:1;		/* reserved at zero */
     63  1.1      mw 	unsigned int	pg_ci:1;	/* cache inhibit bit */
     64  1.1      mw 	unsigned int	pg_cm1:1;	/* cache mode, lsb (68040) */
     65  1.1      mw 	unsigned int	pg_m:1;		/* hardware modified (dirty) bit */
     66  1.1      mw 	unsigned int	pg_u:1;		/* hardware used (reference) bit */
     67  1.1      mw 	unsigned int	pg_prot:1;	/* write protect bit */
     68  1.1      mw 	unsigned int	pg_v:2;		/* valid bit */
     69  1.1      mw };
     70  1.1      mw 
     71  1.1      mw typedef struct ste	st_entry_t;	/* segment table entry */
     72  1.1      mw typedef struct pte	pt_entry_t;	/* Mach page table entry */
     73  1.1      mw 
     74  1.1      mw #define	PT_ENTRY_NULL	((pt_entry_t *) 0)
     75  1.1      mw #define	ST_ENTRY_NULL	((st_entry_t *) 0)
     76  1.1      mw 
     77  1.1      mw #define	SG_V		0x00000002	/* segment is valid */
     78  1.1      mw #define	SG_NV		0x00000000
     79  1.1      mw #define	SG_PROT		0x00000004	/* access protection mask */
     80  1.1      mw #define	SG_RO		0x00000004
     81  1.1      mw #define	SG_RW		0x00000000
     82  1.1      mw #define	SG_FRAME	0xffffe000
     83  1.1      mw #define SG_IMASK1	0xfe000000
     84  1.1      mw #define SG_IMASK2	0x01fc0000
     85  1.1      mw #define SG_040IMASK	0xfffc0000
     86  1.1      mw #define SG_040PMASK	0x0003e000
     87  1.1      mw #define SG_ISHIFT1	25
     88  1.1      mw #define SG_040ISHIFT	18
     89  1.1      mw #define SG_IMASK	0xff000000
     90  1.1      mw #define SG_PMASK	0x00ffe000
     91  1.1      mw #define SG_ISHIFT	24
     92  1.1      mw #define SG_PSHIFT	13
     93  1.1      mw 
     94  1.1      mw 
     95  1.1      mw #define	PG_V		0x00000001
     96  1.1      mw #define	PG_NV		0x00000000
     97  1.1      mw #define	PG_PROT		0x00000004
     98  1.1      mw #define	PG_U		0x00000008
     99  1.1      mw #define	PG_M		0x00000010
    100  1.1      mw #define	PG_W		0x00000100
    101  1.1      mw #define	PG_RO		0x00000004
    102  1.1      mw #define	PG_RW		0x00000000
    103  1.1      mw #define	PG_CI		0x00000040
    104  1.1      mw #define PG_CC		0x00000020	/* Cachable, copyback */
    105  1.1      mw #define PG_CIN		0x00000060	/* Cache inhibited, nonserialized */
    106  1.6  chopps #define PG_CMASK	0x00000060	/* Cache mask for 040 */
    107  1.1      mw #define PG_FRAME	0xffffe000
    108  1.1      mw #define PG_SHIFT	13
    109  1.1      mw #define	PG_PFNUM(x)	(((x) & PG_FRAME) >> PG_SHIFT)
    110  1.1      mw 
    111  1.7  chopps #define AMIGA_040RTSIZE		512	/* root (level 1) table size */
    112  1.7  chopps #define AMIGA_040STSIZE		512	/* segment (level 2) table size */
    113  1.7  chopps #define	AMIGA_040PTSIZE		128	/* page (level 3) table size */
    114  1.7  chopps #define AMIGA_STSIZE		1024	/* segment table size */
    115  1.7  chopps /*
    116  1.7  chopps  * AMIGA_MAX_COREUPT	maximum number of incore user page tables
    117  1.7  chopps  * AMIGA_USER_PTSIZE	the number of bytes for user pagetables
    118  1.7  chopps  * AMIGA_PTBASE		the VA start of the map from which upt's are allocated
    119  1.7  chopps  * AMIGA_PTSIZE		the size of the map from which upt's are allocated
    120  1.7  chopps  * AMIGA_KPTSIZE	size of kernel page table
    121  1.7  chopps  * AMIGA_MAX_KPTSIZE	the most number of bytes for kpt pages
    122  1.7  chopps  * AMIGA_MAX_PTSIZE	the number of bytes to map everything
    123  1.7  chopps  */
    124  1.7  chopps #define AMIGA_MAX_COREUPT	1024
    125  1.7  chopps #define AMIGA_UPTSIZE		roundup(VM_MAXUSER_ADDRESS / NPTEPG, NBPG)
    126  1.7  chopps #define AMIGA_UPTBASE		0x10000000
    127  1.7  chopps #define AMIGA_UPTMAXSIZE \
    128  1.7  chopps     roundup((AMIGA_MAX_COREUPT * AMIGA_UPTSIZE), NBPG)
    129  1.7  chopps #define AMIGA_MAX_KPTSIZE \
    130  1.7  chopps     (AMIGA_MAX_COREUPT * AMIGA_UPTSIZE / NPTEPG)
    131  1.7  chopps #define AMIGA_KPTSIZE \
    132  1.7  chopps     roundup((VM_MAX_KERNEL_ADDRESS - VM_MIN_KERNEL_ADDRESS) / NPTEPG, NBPG)
    133  1.7  chopps #define AMIGA_MAX_PTSIZE	roundup(0xffffffff / NPTEPG, NBPG)
    134  1.1      mw 
    135  1.1      mw /*
    136  1.1      mw  * Kernel virtual address to page table entry and to physical address.
    137  1.1      mw  */
    138  1.1      mw #define	kvtopte(va) \
    139  1.1      mw 	(&Sysmap[((unsigned)(va) - VM_MIN_KERNEL_ADDRESS) >> PGSHIFT])
    140  1.1      mw #define	ptetokv(pt) \
    141  1.1      mw 	((((pt_entry_t *)(pt) - Sysmap) << PGSHIFT) + VM_MIN_KERNEL_ADDRESS)
    142  1.1      mw #define	kvtophys(va) \
    143  1.1      mw 	((kvtopte(va)->pg_pfnum << PGSHIFT) | ((int)(va) & PGOFSET))
    144  1.1      mw 
    145  1.1      mw 
    146  1.4  chopps #endif /* !_MACHINE_PTE_H_ */
    147