cv3dpb.c revision 1.2
1 /* $NetBSD: cv3dpb.c,v 1.2 2012/10/27 17:17:32 chs Exp $ */ 2 3 /*- 4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/extent.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 46 #include <amiga/dev/zbusvar.h> 47 #include <amiga/pci/cv3dpbreg.h> 48 #include <amiga/pci/cv3dpbvar.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 #include <dev/pci/pciconf.h> 54 55 /* Zorro IDs */ 56 #define ZORRO_MANID_P5 8512 57 #define ZORRO_PRODID_CV643D_Z3 67 /* CV64/3D on Z3 bus */ 58 59 static int cv3dpb_match(device_t, cfdata_t, void *); 60 static void cv3dpb_attach(device_t, device_t, void *); 61 pcireg_t cv3dpb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 62 void cv3dpb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 63 int cv3dpb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno); 64 int cv3dpb_pci_intr_map(const struct pci_attach_args *pa, 65 pci_intr_handle_t *ihp); 66 static bool cv3dpb_bus_map(struct cv3dpb_softc *sc); 67 68 CFATTACH_DECL_NEW(cv3dpb, sizeof(struct cv3dpb_softc), 69 cv3dpb_match, cv3dpb_attach, NULL, NULL); 70 71 static int 72 cv3dpb_match(device_t parent, cfdata_t cf, void *aux) 73 { 74 struct zbus_args *zap; 75 76 zap = aux; 77 78 if (zap->manid != ZORRO_MANID_P5) 79 return 0; 80 81 if (zap->prodid != ZORRO_PRODID_CV643D_Z3) 82 return 0; 83 84 #ifdef P5PB_DEBUG 85 aprint_normal("cv3dpb matched by Zorro ID %d, %d\n", zap->manid, 86 zap->prodid); 87 #endif 88 89 return 10; 90 } 91 92 93 static void 94 cv3dpb_attach(device_t parent, device_t self, void *aux) 95 { 96 struct cv3dpb_softc *sc; 97 struct pcibus_attach_args pba; 98 struct zbus_args *zap; 99 100 sc = device_private(self); 101 pci_chipset_tag_t pc = &sc->apc; 102 sc->sc_dev = self; 103 zap = aux; 104 105 sc->ba = zap->va; 106 107 if(!(cv3dpb_bus_map(sc))) { 108 aprint_error_dev(self, 109 "couldn't map PCI configuration registers\n"); 110 return; 111 } 112 113 aprint_normal(": CyberVision 64/3D PCI bridge\n"); 114 115 #ifdef P5PB_DEBUG 116 aprint_normal("cv3dpb: mapped %x -> %x, %x -> %x\n, %x -> %x\n", 117 P5BUS_PCI_CONF_BASE, sc->pci_conf_area.base, 118 P5BUS_PCI_IO_BASE, sc->pci_io_area.base, 119 P5BUS_PCI_MEM_BASE, sc->pci_mem_area.base ); 120 #endif 121 122 /* Initialize the PCI chipset tag. */ 123 sc->apc.pc_conf_v = (void*) pc; 124 sc->apc.pc_bus_maxdevs = cv3dpb_pci_bus_maxdevs; 125 sc->apc.pc_make_tag = amiga_pci_make_tag; 126 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag; 127 sc->apc.pc_conf_read = cv3dpb_pci_conf_read; 128 sc->apc.pc_conf_write = cv3dpb_pci_conf_write; 129 //sc->apc.pc_attach_hook = cv3dpb_pci_attach_hook; 130 131 sc->apc.pc_intr_map = cv3dpb_pci_intr_map; 132 sc->apc.pc_intr_string = amiga_pci_intr_string; 133 sc->apc.pc_intr_establish = amiga_pci_intr_establish; 134 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish; 135 136 pba.pba_iot = &(sc->pci_io_area); 137 pba.pba_memt = &(sc->pci_mem_area); 138 pba.pba_dmat = NULL; 139 pba.pba_dmat64 = NULL; 140 pba.pba_pc = pc; 141 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 142 pba.pba_bus = 0; 143 pba.pba_bridgetag = NULL; 144 145 config_found_ia(self, "pcibus", &pba, pcibusprint); 146 } 147 148 pcireg_t 149 cv3dpb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 150 { 151 uint32_t data; 152 uint32_t bus, dev, func; 153 154 pci_decompose_tag(pc, tag, &bus, &dev, &func); 155 156 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah, 157 (func<<5) + reg); 158 #ifdef P5PB_DEBUG 159 aprint_normal("cv3dpb conf read va: %lx, bus: %d, dev: %d, " 160 "func: %d, reg: %d -r-> data %x\n", 161 pc->pci_conf_datah, bus, dev, func, reg, data); 162 #endif 163 return data; 164 } 165 166 void 167 cv3dpb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 168 { 169 uint32_t bus, dev, func; 170 171 pci_decompose_tag(pc, tag, &bus, &dev, &func); 172 173 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah, 174 (func << 5) + reg, val); 175 #ifdef P5PB_DEBUG 176 aprint_normal("cv3dpb conf write va: %lx, bus: %d, dev: %d, " 177 "func: %d, reg: %d -w-> data %x\n", 178 pc->pci_conf_datah, bus, dev, func, reg, val); 179 #endif 180 181 } 182 183 /* There can be only one. */ 184 int 185 cv3dpb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 186 { 187 return 1; 188 } 189 190 int 191 cv3dpb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 192 { 193 /* TODO: add sanity checking */ 194 195 *ihp = 2; /* XXX: untested */ 196 return 0; 197 } 198 199 bool 200 cv3dpb_bus_map(struct cv3dpb_softc *sc) { 201 #ifdef P5PB_DEBUG 202 aprint_normal("cv3dpb: cv3dpb_bus_map called, ba = %x\n", 203 (bus_addr_t) sc->ba); 204 #endif /* P5PB_DEBUG */ 205 206 sc->pci_conf_area.base = (bus_addr_t) sc->ba + CV643D_PCI_CONF_BASE; 207 sc->pci_conf_area.absm = &amiga_bus_stride_1; 208 209 sc->pci_mem_area.base = (bus_addr_t) sc->ba + CV643D_PCI_MEM_BASE; 210 sc->pci_mem_area.absm = &amiga_bus_stride_1; 211 212 sc->pci_io_area.base = (bus_addr_t) sc->ba + CV643D_PCI_IO_BASE; 213 sc->pci_io_area.absm = &amiga_bus_stride_1; 214 215 sc->apc.pci_conf_datat = &(sc->pci_conf_area); 216 217 if (bus_space_map(sc->apc.pci_conf_datat, 0, 218 CV643D_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah)) 219 return false; 220 221 return true; 222 } 223 224
Indexes created Tue Sep 30 20:09:53 GMT 2025