cv3dpb.c revision 1.6
1 /* $NetBSD: cv3dpb.c,v 1.6 2021/08/07 16:18:42 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 40 #include <uvm/uvm_extern.h> 41 42 #include <machine/bus.h> 43 #include <machine/cpu.h> 44 45 #include <amiga/dev/zbusvar.h> 46 #include <amiga/pci/cv3dpbreg.h> 47 #include <amiga/pci/cv3dpbvar.h> 48 49 #include <dev/pci/pcivar.h> 50 #include <dev/pci/pcireg.h> 51 #include <dev/pci/pcidevs.h> 52 #include <dev/pci/pciconf.h> 53 54 /* Zorro IDs */ 55 #define ZORRO_MANID_P5 8512 56 #define ZORRO_PRODID_CV643D_Z3 67 /* CV64/3D on Z3 bus */ 57 58 static int cv3dpb_match(device_t, cfdata_t, void *); 59 static void cv3dpb_attach(device_t, device_t, void *); 60 pcireg_t cv3dpb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 61 void cv3dpb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 62 int cv3dpb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno); 63 int cv3dpb_pci_intr_map(const struct pci_attach_args *pa, 64 pci_intr_handle_t *ihp); 65 static bool cv3dpb_bus_map(struct cv3dpb_softc *sc); 66 67 CFATTACH_DECL_NEW(cv3dpb, sizeof(struct cv3dpb_softc), 68 cv3dpb_match, cv3dpb_attach, NULL, NULL); 69 70 static int 71 cv3dpb_match(device_t parent, cfdata_t cf, void *aux) 72 { 73 struct zbus_args *zap; 74 75 zap = aux; 76 77 if (zap->manid != ZORRO_MANID_P5) 78 return 0; 79 80 if (zap->prodid != ZORRO_PRODID_CV643D_Z3) 81 return 0; 82 83 #ifdef P5PB_DEBUG 84 aprint_normal("cv3dpb matched by Zorro ID %d, %d\n", zap->manid, 85 zap->prodid); 86 #endif 87 88 return 10; 89 } 90 91 92 static void 93 cv3dpb_attach(device_t parent, device_t self, void *aux) 94 { 95 struct cv3dpb_softc *sc; 96 struct pcibus_attach_args pba; 97 struct zbus_args *zap; 98 99 sc = device_private(self); 100 pci_chipset_tag_t pc = &sc->apc; 101 sc->sc_dev = self; 102 zap = aux; 103 104 sc->ba = zap->va; 105 106 if(!(cv3dpb_bus_map(sc))) { 107 aprint_error_dev(self, 108 "couldn't map PCI configuration registers\n"); 109 return; 110 } 111 112 aprint_normal(": CyberVision 64/3D PCI bridge\n"); 113 114 #ifdef P5PB_DEBUG 115 aprint_normal("cv3dpb: mapped %x -> %x, %x -> %x\n, %x -> %x\n", 116 P5BUS_PCI_CONF_BASE, sc->pci_conf_area.base, 117 P5BUS_PCI_IO_BASE, sc->pci_io_area.base, 118 P5BUS_PCI_MEM_BASE, sc->pci_mem_area.base ); 119 #endif 120 121 /* Initialize the PCI chipset tag. */ 122 sc->apc.pc_conf_v = (void*) pc; 123 sc->apc.pc_bus_maxdevs = cv3dpb_pci_bus_maxdevs; 124 sc->apc.pc_make_tag = amiga_pci_make_tag; 125 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag; 126 sc->apc.pc_conf_read = cv3dpb_pci_conf_read; 127 sc->apc.pc_conf_write = cv3dpb_pci_conf_write; 128 //sc->apc.pc_attach_hook = cv3dpb_pci_attach_hook; 129 130 sc->apc.pc_intr_map = cv3dpb_pci_intr_map; 131 sc->apc.pc_intr_string = amiga_pci_intr_string; 132 sc->apc.pc_intr_establish = amiga_pci_intr_establish; 133 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish; 134 135 pba.pba_iot = &(sc->pci_io_area); 136 pba.pba_memt = &(sc->pci_mem_area); 137 pba.pba_dmat = NULL; 138 pba.pba_dmat64 = NULL; 139 pba.pba_pc = pc; 140 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 141 pba.pba_bus = 0; 142 pba.pba_bridgetag = NULL; 143 144 config_found(self, &pba, pcibusprint, CFARGS_NONE); 145 } 146 147 pcireg_t 148 cv3dpb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 149 { 150 uint32_t data; 151 uint32_t bus, dev, func; 152 153 if ((unsigned int)reg >= PCI_CONF_SIZE) 154 return (pcireg_t) -1; 155 156 pci_decompose_tag(pc, tag, &bus, &dev, &func); 157 158 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah, 159 (func<<5) + reg); 160 #ifdef P5PB_DEBUG 161 aprint_normal("cv3dpb conf read va: %lx, bus: %d, dev: %d, " 162 "func: %d, reg: %d -r-> data %x\n", 163 pc->pci_conf_datah, bus, dev, func, reg, data); 164 #endif 165 return data; 166 } 167 168 void 169 cv3dpb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 170 { 171 uint32_t bus, dev, func; 172 173 if ((unsigned int)reg >= PCI_CONF_SIZE) 174 return; 175 176 pci_decompose_tag(pc, tag, &bus, &dev, &func); 177 178 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah, 179 (func << 5) + reg, val); 180 #ifdef P5PB_DEBUG 181 aprint_normal("cv3dpb conf write va: %lx, bus: %d, dev: %d, " 182 "func: %d, reg: %d -w-> data %x\n", 183 pc->pci_conf_datah, bus, dev, func, reg, val); 184 #endif 185 186 } 187 188 /* There can be only one. */ 189 int 190 cv3dpb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 191 { 192 return 1; 193 } 194 195 int 196 cv3dpb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 197 { 198 /* TODO: add sanity checking */ 199 200 *ihp = 2; /* XXX: untested */ 201 return 0; 202 } 203 204 bool 205 cv3dpb_bus_map(struct cv3dpb_softc *sc) { 206 #ifdef P5PB_DEBUG 207 aprint_normal("cv3dpb: cv3dpb_bus_map called, ba = %x\n", 208 (bus_addr_t) sc->ba); 209 #endif /* P5PB_DEBUG */ 210 211 sc->pci_conf_area.base = (bus_addr_t) sc->ba + CV643D_PCI_CONF_BASE; 212 sc->pci_conf_area.absm = &amiga_bus_stride_1; 213 214 sc->pci_mem_area.base = (bus_addr_t) sc->ba + CV643D_PCI_MEM_BASE; 215 sc->pci_mem_area.absm = &amiga_bus_stride_1; 216 217 sc->pci_io_area.base = (bus_addr_t) sc->ba + CV643D_PCI_IO_BASE; 218 sc->pci_io_area.absm = &amiga_bus_stride_1; 219 220 sc->apc.pci_conf_datat = &(sc->pci_conf_area); 221 222 if (bus_space_map(sc->apc.pci_conf_datat, 0, 223 CV643D_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah)) 224 return false; 225 226 return true; 227 } 228 229
Indexes created Tue Sep 30 20:09:53 GMT 2025