p5pb.c revision 1.1
1 /* $NetBSD: p5pb.c,v 1.1 2011/08/04 17:48:51 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/extent.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <machine/bus.h> 44 #include <machine/cpu.h> 45 46 #include <m68k/bus_dma.h> 47 #include <amiga/dev/zbusvar.h> 48 #include <amiga/pci/p5pbreg.h> 49 50 #include <dev/pci/pcivar.h> 51 #include <dev/pci/pcireg.h> 52 #include <dev/pci/pcidevs.h> 53 #include <dev/pci/pciconf.h> 54 55 /* Zorro IDs */ 56 #define ZORRO_MANID_P5 8512 57 #define ZORRO_PRODID_BPPC 110 /* BlizzardPPC */ 58 #define ZORRO_PRODID_CSPPC 100 /* CyberStormPPC */ 59 #define ZORRO_PRODID_P5PB 101 /* CVPPC/BVPPC (/G-REX?) */ 60 /* Initial resolution as configured by the firmware */ 61 #define P5GFX_WIDTH 640 62 #define P5GFX_HEIGHT 480 63 #define P5GFX_DEPTH 8 64 #define P5GFX_LINEBYTES 640 65 66 struct p5pb_softc { 67 device_t sc_dev; 68 struct bus_space_tag pci_conf_area; 69 struct bus_space_tag pci_mem_area; 70 struct amiga_pci_chipset apc; 71 }; 72 73 static int p5pb_match(struct device *, struct cfdata *, void *); 74 static void p5pb_attach(struct device *, struct device *, void *); 75 void p5pb_set_props(struct p5pb_softc *sc); 76 pcireg_t p5pb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 77 void p5pb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 78 int p5pb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno); 79 int p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, int func, pcireg_t id); 80 void p5pb_pci_attach_hook (struct device *parent, struct device *self, struct pcibus_attach_args *pba); 81 pcitag_t p5pb_pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function); 82 void p5pb_pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, int *dp, int *fp); 83 84 CFATTACH_DECL_NEW(p5pb, sizeof(struct p5pb_softc), 85 p5pb_match, p5pb_attach, NULL, NULL); 86 87 88 static int p5pb_present = 0; 89 90 static int 91 p5pb_match(device_t parent, cfdata_t cf, void *aux) 92 { 93 struct zbus_args *zap; 94 95 zap = aux; 96 97 if (zap->manid != ZORRO_MANID_P5) 98 return 0; 99 100 if (zap->prodid != ZORRO_PRODID_P5PB) 101 return 0; 102 103 #ifdef P5PB_DEBUG 104 aprint_normal("p5pb matched by Zorro ID %d, %d\n", zap->manid, 105 zap->prodid); 106 #endif 107 108 if (p5pb_present) 109 return 0; /* Allow only one. */ 110 111 112 #ifdef I_HAVE_P5PB_REALLY 113 /* 114 * At least some firmware versions do not create AutoConfig entries for 115 * CyberVisionPPC/BlizzardVisionPPC (product ID 0101). There's no "nice" 116 * way to detect the PCI bus in this case. At least check for CSPPC/BPPC. 117 */ 118 if (zap->prodid = !(ZORRO_PRODID_BPPC || ZORRO_PRODID_CSPPC)) { 119 if (!p5pb_present) { 120 p5pb_present = 1; 121 return 100; /* XXX: This will break SCSI! */ 122 } 123 } 124 #endif 125 p5pb_present = 1; 126 return 1; 127 } 128 129 130 static void 131 p5pb_attach(device_t parent, device_t self, void *aux) 132 { 133 struct p5pb_softc *sc = device_private(self); 134 struct pcibus_attach_args pba; 135 136 pci_chipset_tag_t pc = &sc->apc; 137 sc->sc_dev = self; 138 aprint_normal(": Phase5 CVPPC/BVPPC PCI bridge\n"); 139 140 /* Setup bus space mappings. */ 141 sc->pci_conf_area.base = (bus_addr_t) zbusmap( 142 (void *) P5BUS_PCI_CONF_BASE, P5BUS_PCI_CONF_SIZE); 143 sc->pci_conf_area.absm = &amiga_bus_stride_1; 144 145 sc->pci_mem_area.base = (bus_addr_t) zbusmap( 146 (void *) P5BUS_PCI_MEM_BASE, P5BUS_PCI_MEM_SIZE); 147 sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs; 148 149 #ifdef P5PB_DEBUG 150 aprint_normal("p5pb mapped %x -> %x, %x -> %x\n", 151 P5BUS_PCI_CONF_BASE, sc->pci_conf_area.base, 152 P5BUS_PCI_MEM_BASE, sc->pci_mem_area.base ); 153 #endif 154 155 sc->apc.pci_conf_iot = &(sc->pci_conf_area); 156 157 if (bus_space_map(sc->apc.pci_conf_iot, OFF_PCI_CONF_DATA, 158 256, 0, &sc->apc.pci_conf_ioh)) 159 aprint_error_dev(self, 160 "couldn't map PCI configuration data space\n"); 161 162 /* Initialize the PCI chipset tag. */ 163 sc->apc.pc_conf_v = (void*) pc; 164 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs; 165 sc->apc.pc_make_tag = p5pb_pci_make_tag; 166 sc->apc.pc_decompose_tag = p5pb_pci_decompose_tag; 167 sc->apc.pc_conf_read = p5pb_pci_conf_read; 168 sc->apc.pc_conf_write = p5pb_pci_conf_write; 169 sc->apc.pc_attach_hook = p5pb_pci_attach_hook; 170 171 pba.pba_iot = NULL; 172 pba.pba_memt = &(sc->pci_mem_area); 173 pba.pba_dmat = NULL; 174 pba.pba_dmat64 = NULL; 175 pba.pba_pc = pc; 176 pba.pba_flags = PCI_FLAGS_MEM_OKAY; 177 pba.pba_bus = 0; 178 pba.pba_bridgetag = NULL; 179 180 p5pb_set_props(sc); 181 182 config_found_ia(self, "pcibus", &pba, pcibusprint); 183 } 184 185 /* 186 * Set properties needed to support fb driver. These are read later during 187 * autoconfg in device_register(). 188 */ 189 void 190 p5pb_set_props(struct p5pb_softc *sc) 191 { 192 prop_dictionary_t dict; 193 device_t dev; 194 195 dev = sc->sc_dev; 196 dict = device_properties(dev); 197 198 prop_dictionary_set_uint32(dict, "width", P5GFX_WIDTH); 199 prop_dictionary_set_uint32(dict, "height", P5GFX_HEIGHT); 200 prop_dictionary_set_uint8(dict, "depth", P5GFX_DEPTH); 201 prop_dictionary_set_uint16(dict, "linebytes", P5GFX_LINEBYTES); 202 prop_dictionary_set_uint64(dict, "address", P5BUS_PCI_MEM_BASE); 203 #if (NGENFB > 0) 204 /* 205 * Framebuffer starts at P5BUS_PCI_MEM_BASE, but genfb needs virtual 206 * address. 207 */ 208 prop_dictionary_set_uint64(dict, "virtual_address", 209 sc->pci_mem_area.base); 210 #endif 211 } 212 213 pcireg_t 214 p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 215 { 216 uint32_t data; 217 uint32_t bus, dev, func; 218 219 pci_decompose_tag(pc, tag, &bus, &dev, &func); 220 221 data = bus_space_read_4(pc->pci_conf_iot, pc->pci_conf_ioh, 222 (func<<5) + reg); 223 #ifdef P5PB_DEBUG 224 aprint_normal("p5pb conf read va: %lx, bus: %d, dev: %d, " 225 "func: %d, reg: %d -r-> data %x\n", 226 pc->pci_conf_ioh, bus, dev, func, reg, data); 227 #endif 228 return data; 229 } 230 231 void 232 p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 233 { 234 uint32_t bus, dev, func; 235 236 pci_decompose_tag(pc, tag, &bus, &dev, &func); 237 238 bus_space_write_4(pc->pci_conf_iot, pc->pci_conf_ioh, 239 (func << 5) + reg, val); 240 #ifdef P5PB_DEBUG 241 aprint_normal("p5pb conf write va: %lx, bus: %d, dev: %d, " 242 "func: %d, reg: %d -w-> data %x\n", 243 pc->pci_conf_ioh, bus, dev, func, reg, val); 244 #endif 245 246 } 247 248 int 249 p5pb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 250 { 251 252 /* Allow only one device. Obvious in case of CVPPC/BVPPC. */ 253 return 1; 254 } 255 256 pcitag_t 257 p5pb_pci_make_tag(pci_chipset_tag_t pc, int bus, int device, int function) 258 { 259 260 return (bus << 16) | (device << 11) | (function << 8); 261 } 262 263 void 264 p5pb_pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, int *bp, 265 int *dp, int *fp) 266 { 267 268 if (bp != NULL) 269 *bp = (tag >> 16) & 0xff; 270 if (dp != NULL) 271 *dp = (tag >> 11) & 0x1f; 272 if (fp != NULL) 273 *fp = (tag >> 8) & 0x07; 274 } 275 276 void 277 p5pb_pci_attach_hook(struct device *parent, struct device *self, 278 struct pcibus_attach_args *pba) 279 { 280 } 281 282
Indexes created Tue Sep 30 20:09:53 GMT 2025