p5pb.c revision 1.11
1 /* $NetBSD: p5pb.c,v 1.11 2012/07/13 08:47:07 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/kmem.h> 40 #include <sys/extent.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #define _M68K_BUS_DMA_PRIVATE 45 #include <machine/bus.h> 46 #include <machine/cpu.h> 47 48 #include <m68k/bus_dma.h> 49 #include <amiga/dev/zbusvar.h> 50 #include <amiga/dev/p5busvar.h> 51 #include <amiga/pci/p5pbreg.h> 52 #include <amiga/pci/p5pbvar.h> 53 #include <amiga/pci/p5membarvar.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 #ifdef PCI_NETBSD_CONFIGURE 59 #include <dev/pci/pciconf.h> 60 #endif /* PCI_NETBSD_CONFIGURE */ 61 62 #include "opt_p5pb.h" 63 #include "opt_pci.h" 64 65 /* Initial CVPPC/BVPPC resolution as configured by the firmware */ 66 #define P5GFX_WIDTH 640 67 #define P5GFX_HEIGHT 480 68 #define P5GFX_DEPTH 8 69 #define P5GFX_LINEBYTES 640 70 71 struct m68k_bus_dma_tag p5pb_bus_dma_tag = { 72 0, 73 0, 74 _bus_dmamap_create, 75 _bus_dmamap_destroy, 76 _bus_dmamap_load_direct, 77 _bus_dmamap_load_mbuf_direct, 78 _bus_dmamap_load_uio_direct, 79 _bus_dmamap_load_raw_direct, 80 _bus_dmamap_unload, 81 _bus_dmamap_sync, 82 _bus_dmamem_alloc, 83 _bus_dmamem_free, 84 _bus_dmamem_map, 85 _bus_dmamem_unmap, 86 _bus_dmamem_mmap 87 }; 88 89 static int p5pb_match(struct device *, struct cfdata *, void *); 90 static void p5pb_attach(struct device *, struct device *, void *); 91 void p5pb_set_props(struct p5pb_softc *sc); 92 pcireg_t p5pb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 93 void p5pb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 94 int p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t pc, int busno); 95 int p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t pc, int busno); 96 int p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t pc, int busno); 97 int p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, 98 int func, pcireg_t id); 99 void p5pb_pci_attach_hook (struct device *parent, 100 struct device *self, struct pcibus_attach_args *pba); 101 pcitag_t p5pb_pci_make_tag(pci_chipset_tag_t pc, int bus, int device, 102 int function); 103 void p5pb_pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 104 int *bp, int *dp, int *fp); 105 int p5pb_pci_intr_map(const struct pci_attach_args *pa, 106 pci_intr_handle_t *ihp); 107 bool p5pb_bus_map_memio(struct p5pb_softc *sc); 108 bool p5pb_bus_map_conf(struct p5pb_softc *sc); 109 uint8_t p5pb_find_resources(struct p5pb_softc *sc); 110 static bool p5pb_identify_bridge(struct p5pb_softc *sc); 111 void p5pb_membar_grex(struct p5pb_softc *sc); 112 static bool p5pb_cvppc_probe(struct p5pb_softc *sc); 113 #ifdef PCI_NETBSD_CONFIGURE 114 bool p5pb_bus_reconfigure(struct p5pb_softc *sc); 115 #endif /* PCI_NETBSD_CONFIGURE */ 116 #ifdef P5PB_DEBUG 117 void p5pb_usable_ranges(struct p5pb_softc *sc); 118 void p5pb_badaddr_range(struct p5pb_softc *sc, bus_space_tag_t bust, 119 bus_addr_t base, size_t len); 120 void p5pb_conf_search(struct p5pb_softc *sc, uint16_t val); 121 #endif /* P5PB_DEBUG */ 122 123 CFATTACH_DECL_NEW(p5pb, sizeof(struct p5pb_softc), 124 p5pb_match, p5pb_attach, NULL, NULL); 125 126 static int 127 p5pb_match(device_t parent, cfdata_t cf, void *aux) 128 { 129 struct p5bus_attach_args *p5baa; 130 131 p5baa = (struct p5bus_attach_args *) aux; 132 133 if (strcmp(p5baa->p5baa_name, "p5pb") == 0) 134 return 1; 135 136 return 0; 137 } 138 139 static void 140 p5pb_attach(device_t parent, device_t self, void *aux) 141 { 142 struct p5pb_softc *sc; 143 struct pcibus_attach_args pba; 144 145 sc = device_private(self); 146 sc->sc_dev = self; 147 sc->p5baa = (struct p5bus_attach_args *) aux; 148 149 pci_chipset_tag_t pc = &sc->apc; 150 151 if (!p5pb_bus_map_conf(sc)) { 152 aprint_error_dev(self, 153 "couldn't map PCI configuration space\n"); 154 return; 155 } 156 157 if (!p5pb_identify_bridge(sc)) { 158 return; 159 } 160 161 if (sc->bridge_type == P5PB_BRIDGE_CVPPC) { 162 sc->pci_mem_lowest = P5BUS_PCI_MEM_BASE; 163 sc->pci_mem_highest = P5BUS_PCI_MEM_BASE + P5BUS_PCI_MEM_SIZE; 164 } else { 165 p5pb_membar_grex(sc); 166 } 167 168 if (!p5pb_bus_map_memio(sc)) { 169 aprint_error_dev(self, 170 "couldn't map PCI I/O and memory space\n"); 171 return; 172 } 173 174 #ifdef P5PB_DEBUG 175 aprint_normal("p5pb: map conf %x -> %x, io %x -> %x, mem %x -> %x\n", 176 kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base, 177 kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base, 178 kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base ); 179 #endif 180 181 /* Initialize the PCI chipset tag. */ 182 183 if (sc->bridge_type == P5PB_BRIDGE_GREX1200) 184 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex1200; 185 else if (sc->bridge_type == P5PB_BRIDGE_GREX4000) 186 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex4000; 187 else 188 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_cvppc; 189 190 sc->apc.pc_conf_v = (void*) pc; 191 sc->apc.pc_make_tag = amiga_pci_make_tag; 192 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag; 193 sc->apc.pc_conf_read = p5pb_pci_conf_read; 194 sc->apc.pc_conf_write = p5pb_pci_conf_write; 195 sc->apc.pc_conf_hook = p5pb_pci_conf_hook; 196 sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt; 197 sc->apc.pc_attach_hook = p5pb_pci_attach_hook; 198 199 sc->apc.pc_intr_map = p5pb_pci_intr_map; 200 sc->apc.pc_intr_string = amiga_pci_intr_string; 201 sc->apc.pc_intr_establish = amiga_pci_intr_establish; 202 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish; 203 204 #ifdef PCI_NETBSD_CONFIGURE 205 /* Never reconfigure the bus on CVPPC/BVPPC, avoid the fb breakage. */ 206 if (sc->bridge_type != P5PB_BRIDGE_CVPPC) { 207 p5pb_bus_reconfigure(sc); 208 } 209 #endif /* PCI_NETBSD_CONFIGURE */ 210 211 /* Initialize the bus attachment structure. */ 212 213 pba.pba_iot = &(sc->pci_io_area); 214 pba.pba_memt = &(sc->pci_mem_area); 215 pba.pba_dmat = &p5pb_bus_dma_tag; 216 pba.pba_dmat64 = NULL; 217 pba.pba_pc = pc; 218 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 219 pba.pba_bus = 0; 220 pba.pba_bridgetag = NULL; 221 222 p5pb_set_props(sc); 223 224 config_found_ia(self, "pcibus", &pba, pcibusprint); 225 } 226 227 /* 228 * Try to detect what kind of bridge are we dealing with. 229 */ 230 static bool 231 p5pb_identify_bridge(struct p5pb_softc *sc) 232 { 233 int pcires_count; /* Number of AutoConfig(TM) PCI resources */ 234 235 pcires_count = p5pb_find_resources(sc); 236 237 switch (pcires_count) { 238 case 0: 239 /* 240 * Zero AutoConfig(TM) PCI resources, means that there's nothing 241 * OR there's a CVPPC/BVPPC with a pre-44.69 firmware. 242 */ 243 if (p5pb_cvppc_probe(sc)) { 244 sc->bridge_type = P5PB_BRIDGE_CVPPC; 245 aprint_normal(": Phase5 CVPPC/BVPPC PCI bridge\n"); 246 } else { 247 aprint_normal(": no PCI bridges detected\n"); 248 return false; 249 } 250 break; 251 case 6: 252 /* 253 * We have a slight possibility, that there's a CVPPC/BVPPC with 254 * the new firmware. So check for it first. 255 */ 256 if (p5pb_cvppc_probe(sc)) { 257 /* New firmware, treat as one-slot GREX. */ 258 sc->bridge_type = P5PB_BRIDGE_CVPPC; 259 aprint_normal( 260 ": Phase5 CVPPC/BVPPC PCI bridge (44.69/44.71)\n"); 261 break; 262 } 263 default: 264 /* We have a G-REX surely. */ 265 266 if (sc->p5baa->p5baa_cardtype == P5_CARDTYPE_CS) { 267 sc->bridge_type = P5PB_BRIDGE_GREX4000; 268 aprint_normal(": DCE G-REX 4000 PCI bridge\n"); 269 } else { 270 sc->bridge_type = P5PB_BRIDGE_GREX1200; 271 aprint_normal(": DCE G-REX 1200 PCI bridge\n"); 272 } 273 break; 274 } 275 return true; 276 } 277 278 /* 279 * Find AutoConfig(TM) resuorces (for boards running G-REX firmware). Return the 280 * total number of found resources. 281 */ 282 uint8_t 283 p5pb_find_resources(struct p5pb_softc *sc) 284 { 285 uint8_t i, rv; 286 struct p5pb_autoconf_entry *auto_entry; 287 struct p5membar_softc *membar_sc; 288 device_t p5membar_dev; 289 290 rv = 0; 291 292 TAILQ_INIT(&sc->auto_bars); 293 294 /* 255 should be enough for everybody */ 295 for(i = 0; i < 255; i++) { 296 297 if ((p5membar_dev = 298 device_find_by_driver_unit("p5membar", i)) != NULL) { 299 300 rv++; 301 302 membar_sc = device_private(p5membar_dev); 303 if (membar_sc->sc_type == P5MEMBAR_TYPE_INTERNAL) 304 continue; 305 306 auto_entry = 307 kmem_alloc(sizeof(struct p5pb_autoconf_entry), 308 KM_SLEEP); 309 310 auto_entry->base = membar_sc->sc_base; 311 auto_entry->size = membar_sc->sc_size; 312 313 TAILQ_INSERT_TAIL(&sc->auto_bars, auto_entry, entries); 314 } 315 } 316 return rv; 317 } 318 319 /* 320 * Set properties needed to support fb driver. These are read later during 321 * autoconfg in device_register(). Needed for CVPPC/BVPPC. 322 */ 323 void 324 p5pb_set_props(struct p5pb_softc *sc) 325 { 326 prop_dictionary_t dict; 327 device_t dev; 328 329 dev = sc->sc_dev; 330 dict = device_properties(dev); 331 332 /* genfb needs additional properties, like virtual, physical address */ 333 #if (NGENFB > 0) 334 /* XXX: currently genfb is supported only on CVPPC/BVPPC */ 335 prop_dictionary_set_uint64(dict, "virtual_address", 336 sc->pci_mem_area.base); 337 prop_dictionary_set_uint64(dict, "address", 338 kvtop((void*) sc->pci_mem_area.base)); 339 #endif 340 } 341 342 pcireg_t 343 p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 344 { 345 uint32_t data; 346 uint32_t bus, dev, func; 347 uint32_t offset; 348 349 pci_decompose_tag(pc, tag, &bus, &dev, &func); 350 351 offset = (OFF_PCI_DEVICE << dev) + reg; 352 353 if(func == 0) /* ugly, ugly hack */ 354 offset += 0; 355 else if(func == 1) 356 offset += OFF_PCI_FUNCTION; 357 else 358 return 0xFFFFFFFF; 359 360 if(badaddr((void *)__UNVOLATILE(((uint32_t) 361 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 362 + offset)))) 363 return 0xFFFFFFFF; 364 365 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah, 366 offset); 367 #ifdef P5PB_DEBUG_CONF 368 aprint_normal("p5pb conf read va: %lx, bus: %d, dev: %d, " 369 "func: %d, reg: %d -r-> data %x\n", 370 pc->pci_conf_datah, bus, dev, func, reg, data); 371 #endif 372 return data; 373 } 374 375 void 376 p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 377 { 378 uint32_t bus, dev, func; 379 uint32_t offset; 380 381 pci_decompose_tag(pc, tag, &bus, &dev, &func); 382 383 offset = (OFF_PCI_DEVICE << dev) + reg; 384 385 if(func == 0) /* ugly, ugly hack */ 386 offset += 0; 387 else if(func == 1) 388 offset += OFF_PCI_FUNCTION; 389 else 390 return; 391 392 if(badaddr((void *)__UNVOLATILE(((uint32_t) 393 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 394 + offset)))) 395 return; 396 397 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah, 398 offset, val); 399 #ifdef P5PB_DEBUG_CONF 400 aprint_normal("p5pb conf write va: %lx, bus: %d, dev: %d, " 401 "func: %d, reg: %d -w-> data %x\n", 402 pc->pci_conf_datah, bus, dev, func, reg, val); 403 #endif 404 405 } 406 407 int 408 p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t pc, int busno) 409 { 410 /* CVPPC/BVPPC has only 1 "slot". */ 411 return 1; 412 } 413 414 int 415 p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t pc, int busno) 416 { 417 /* G-REX 4000 has 4, G-REX 4000T has 3 slots? */ 418 return 4; 419 } 420 421 int 422 p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t pc, int busno) 423 { 424 /* G-REX 1200 has 5 slots. */ 425 return 4; /* XXX: 5 not yet! */ 426 } 427 428 void 429 p5pb_pci_attach_hook(struct device *parent, struct device *self, 430 struct pcibus_attach_args *pba) 431 { 432 } 433 434 int 435 p5pb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 436 { 437 /* TODO: add sanity checking */ 438 439 *ihp = 2; 440 return 0; 441 } 442 443 /* Probe for CVPPC/BVPPC. */ 444 static bool 445 p5pb_cvppc_probe(struct p5pb_softc *sc) 446 { 447 bus_space_handle_t probe_h; 448 uint16_t prodid, manid; 449 void* data; 450 bool rv; 451 452 manid = 0; prodid = 0; 453 rv = false; 454 455 if (bus_space_map(sc->apc.pci_conf_datat, 0, 4, 0, &probe_h)) 456 return rv; 457 458 data = bus_space_vaddr(sc->apc.pci_conf_datat, probe_h); 459 460 if (badaddr((void *)__UNVOLATILE((uint32_t) data))) { 461 #ifdef P5PB_DEBUG_PROBE 462 aprint_normal("p5pb: CVPPC configuration space not usable!\n"); 463 #endif /* P5PB_DEBUG_PROBE */ 464 } else { 465 prodid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 0); 466 manid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 2); 467 468 if ((prodid == P5PB_PM2_PRODUCT_ID) && 469 (manid == P5PB_PM2_VENDOR_ID)) 470 rv = true; 471 } 472 473 #ifdef P5PB_DEBUG_PROBE 474 aprint_normal("p5pb: CVPPC probe for PCI ID: %x, %x returns %d\n", 475 manid, prodid, (int) rv); 476 #endif /* P5PB_DEBUG_PROBE */ 477 478 bus_space_unmap(sc->apc.pci_conf_datat, probe_h, 4); 479 return rv; 480 } 481 482 #ifdef PCI_NETBSD_CONFIGURE 483 /* Reconfigure the bus. */ 484 bool 485 p5pb_bus_reconfigure(struct p5pb_softc *sc) 486 { 487 struct extent *ioext, *memext; 488 pci_chipset_tag_t pc; 489 490 pc = &sc->apc; 491 492 ioext = extent_create("p5pbio", 0, P5BUS_PCI_IO_SIZE, NULL, 0, 493 EX_NOWAIT); 494 495 memext = extent_create("p5pbmem", sc->pci_mem_lowest, 496 sc->pci_mem_highest - 1, NULL, 0, EX_NOWAIT); 497 498 if ( (!ioext) || (!memext) ) 499 return false; 500 501 #ifdef P5PB_DEBUG 502 aprint_normal("p5pb: reconfiguring the bus!\n"); 503 #endif /* P5PB_DEBUG */ 504 pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE); 505 506 extent_destroy(ioext); 507 extent_destroy(memext); 508 509 return true; /* TODO: better error handling */ 510 } 511 #endif /* PCI_NETBSD_CONFIGURE */ 512 513 /* Determine the PCI memory space (done G-REX-style). */ 514 void 515 p5pb_membar_grex(struct p5pb_softc *sc) 516 { 517 struct p5pb_autoconf_entry *membar_entry; 518 uint32_t bar_address; 519 520 sc->pci_mem_lowest = 0xFFFFFFFF; 521 sc->pci_mem_highest = 0; 522 523 /* Iterate over membar entries to find lowest and highest address. */ 524 TAILQ_FOREACH(membar_entry, &sc->auto_bars, entries) { 525 526 bar_address = (uint32_t) membar_entry->base; 527 if ((bar_address + membar_entry->size) > sc->pci_mem_highest) 528 sc->pci_mem_highest = bar_address + membar_entry->size; 529 if (bar_address < sc->pci_mem_lowest) 530 sc->pci_mem_lowest = bar_address; 531 532 #ifdef P5PB_DEBUG_BAR 533 aprint_normal("p5pb: %d kB mem BAR at %p, hi = %x, lo = %x\n", 534 membar_entry->size / 1024, membar_entry->base, 535 sc->pci_mem_highest, sc->pci_mem_lowest); 536 #endif /* P5PB_DEBUG_BAR */ 537 } 538 539 aprint_normal("p5pb: %d kB PCI memory space (%8p to %8p)\n", 540 (sc->pci_mem_highest - sc->pci_mem_lowest) / 1024, 541 (void*) sc->pci_mem_lowest, (void*) sc->pci_mem_highest); 542 543 } 544 545 bool 546 p5pb_bus_map_conf(struct p5pb_softc *sc) 547 { 548 sc->pci_conf_area.base = (bus_addr_t) zbusmap( 549 (void *) P5BUS_PCI_CONF_BASE, P5BUS_PCI_CONF_SIZE); 550 sc->pci_conf_area.absm = &amiga_bus_stride_1; 551 552 sc->apc.pci_conf_datat = &(sc->pci_conf_area); 553 554 if (bus_space_map(sc->apc.pci_conf_datat, OFF_PCI_CONF_DATA, 555 P5BUS_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah)) 556 return false; 557 558 return true; 559 } 560 561 /* Map I/O and memory space. */ 562 bool 563 p5pb_bus_map_memio(struct p5pb_softc *sc) 564 { 565 sc->pci_io_area.base = (bus_addr_t) zbusmap( 566 (void *) P5BUS_PCI_IO_BASE, P5BUS_PCI_IO_SIZE); 567 sc->pci_io_area.absm = &amiga_bus_stride_1swap; 568 569 sc->pci_mem_area.base = (bus_addr_t) zbusmap( 570 (void *) sc->pci_mem_lowest, 571 sc->pci_mem_highest - sc->pci_mem_lowest); 572 sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs; 573 574 return true; 575 } 576 577 int 578 p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, 579 int func, pcireg_t id) 580 { 581 /* XXX: What should we do on CVPPC/BVPPC? It breaks genfb. */ 582 583 return PCI_CONF_DEFAULT; 584 } 585 586 #ifdef P5PB_DEBUG 587 /* Check which config and I/O ranges are usable. */ 588 void 589 p5pb_usable_ranges(struct p5pb_softc *sc) 590 { 591 p5pb_badaddr_range(sc, &(sc->pci_conf_area), 0, P5BUS_PCI_CONF_SIZE); 592 p5pb_badaddr_range(sc, &(sc->pci_io_area), 0, P5BUS_PCI_IO_SIZE); 593 } 594 595 void 596 p5pb_badaddr_range(struct p5pb_softc *sc, bus_space_tag_t bust, bus_addr_t base, 597 size_t len) 598 { 599 int i, state, prev_state; 600 bus_space_handle_t bush; 601 volatile void *data; 602 603 state = -1; 604 prev_state = -1; 605 606 bus_space_map(bust, base, len, 0, &bush); 607 608 aprint_normal("p5pb: badaddr range check from %x (%x) to %x (%x)\n", 609 (bus_addr_t) bush, /* start VA */ 610 (bus_addr_t) kvtop((void*) bush), /* start PA */ 611 (bus_addr_t) bush + len, /* end VA */ 612 (bus_addr_t) kvtop((void*) (bush + len)));/* end PA */ 613 614 data = bus_space_vaddr(bust, bush); 615 616 for(i = 0; i < len; i++) { 617 state = badaddr((void *)__UNVOLATILE(((uint32_t) data + i))); 618 if(state != prev_state) { 619 aprint_normal("p5pb: badaddr %p (%x) : %d\n", 620 (void*) ((uint32_t) data + i), 621 (bus_addr_t) kvtop((void*) ((uint32_t) data + i)), 622 state); 623 prev_state = state; 624 } 625 626 } 627 628 bus_space_unmap(bust, bush, len); 629 } 630 631 /* Search for 16-bit value in the configuration space. */ 632 void 633 p5pb_conf_search(struct p5pb_softc *sc, uint16_t val) 634 { 635 int i, state; 636 uint16_t readv; 637 void *va; 638 639 va = bus_space_vaddr(sc->apc.pci_conf_datat, sc->apc.pci_conf_datah); 640 641 for (i = 0; i < P5BUS_PCI_CONF_SIZE; i++) { 642 state = badaddr((void *)__UNVOLATILE(((uint32_t) va + i))); 643 if(state == 0) { 644 readv = bus_space_read_2(sc->apc.pci_conf_datat, 645 sc->apc.pci_conf_datah, i); 646 if(readv == val) 647 aprint_normal("p5pb: found val %x @ %x (%x)\n", 648 readv, (uint32_t) sc->apc.pci_conf_datah 649 + i, (bus_addr_t) kvtop((void*) 650 ((uint32_t) sc->apc.pci_conf_datah + i))); 651 } 652 } 653 } 654 655 #endif /* P5PB_DEBUG */ 656 657 #ifdef P5PB_CONSOLE 658 void 659 p5pb_device_register(device_t dev, void *aux) 660 { 661 prop_dictionary_t dict, parent_dict; 662 struct pci_attach_args *pa = aux; 663 664 if (device_parent(dev) && device_is_a(device_parent(dev), "pci")) { 665 666 dict = device_properties(dev); 667 668 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 669 670 /* Handle the CVPPC/BVPPC card... */ 671 if ( ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TI) 672 && (PCI_PRODUCT(pa->pa_id) == 673 PCI_PRODUCT_TI_TVP4020) ) || 674 /* ...and 3Dfx Voodoo 3 in G-REX. */ 675 ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) 676 && (PCI_PRODUCT(pa->pa_id) == 677 PCI_PRODUCT_3DFX_VOODOO3) )) { 678 679 parent_dict = device_properties( 680 device_parent(device_parent(dev))); 681 682 prop_dictionary_set_uint32(dict, "width", 683 P5GFX_WIDTH); 684 685 prop_dictionary_set_uint32(dict, "height", 686 P5GFX_HEIGHT); 687 688 prop_dictionary_set_uint32(dict, "depth", 689 P5GFX_DEPTH); 690 691 #if (NGENFB > 0) 692 prop_dictionary_set_uint32(dict, "linebytes", 693 P5GFX_LINEBYTES); 694 695 prop_dictionary_set(dict, "address", 696 prop_dictionary_get(parent_dict, 697 "address")); 698 prop_dictionary_set(dict, "virtual_address", 699 prop_dictionary_get(parent_dict, 700 "virtual_address")); 701 #endif 702 prop_dictionary_set_bool(dict, "is_console", 703 true); 704 } 705 } 706 } 707 } 708 #endif /* P5PB_CONSOLE */ 709 710
Indexes created Tue Sep 30 20:09:53 GMT 2025