p5pb.c revision 1.15
1 /* $NetBSD: p5pb.c,v 1.15 2015/10/30 12:14:32 phx Exp $ */ 2 3 /*- 4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/kmem.h> 40 #include <sys/extent.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #define _M68K_BUS_DMA_PRIVATE 45 #include <machine/bus.h> 46 #include <machine/cpu.h> 47 48 #include <m68k/bus_dma.h> 49 #include <amiga/dev/zbusvar.h> 50 #include <amiga/dev/p5busvar.h> 51 #include <amiga/pci/p5pbreg.h> 52 #include <amiga/pci/p5pbvar.h> 53 #include <amiga/pci/p5membarvar.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 #ifdef PCI_NETBSD_CONFIGURE 59 #include <dev/pci/pciconf.h> 60 #endif /* PCI_NETBSD_CONFIGURE */ 61 62 #include "opt_p5pb.h" 63 #include "opt_pci.h" 64 #include "genfb.h" 65 66 /* Initial CVPPC/BVPPC resolution as configured by the firmware */ 67 #define P5GFX_WIDTH 640 68 #define P5GFX_HEIGHT 480 69 #define P5GFX_DEPTH 8 70 #define P5GFX_LINEBYTES 640 71 72 struct m68k_bus_dma_tag p5pb_bus_dma_tag = { 73 0, 74 0, 75 _bus_dmamap_create, 76 _bus_dmamap_destroy, 77 _bus_dmamap_load_direct, 78 _bus_dmamap_load_mbuf_direct, 79 _bus_dmamap_load_uio_direct, 80 _bus_dmamap_load_raw_direct, 81 _bus_dmamap_unload, 82 _bus_dmamap_sync, 83 _bus_dmamem_alloc, 84 _bus_dmamem_free, 85 _bus_dmamem_map, 86 _bus_dmamem_unmap, 87 _bus_dmamem_mmap 88 }; 89 90 static int p5pb_match(device_t, cfdata_t, void *); 91 static void p5pb_attach(device_t, device_t, void *); 92 void p5pb_set_props(struct p5pb_softc *); 93 pcireg_t p5pb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 94 void p5pb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 95 int p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t, int); 96 int p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t, int); 97 int p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t, int); 98 int p5pb_pci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 99 void p5pb_pci_attach_hook (device_t, device_t, 100 struct pcibus_attach_args *); 101 pcitag_t p5pb_pci_make_tag(pci_chipset_tag_t, int, int, int); 102 void p5pb_pci_decompose_tag(pci_chipset_tag_t, pcitag_t, 103 int *, int *, int *); 104 int p5pb_pci_intr_map(const struct pci_attach_args *, 105 pci_intr_handle_t *); 106 bool p5pb_bus_map_memio(struct p5pb_softc *); 107 bool p5pb_bus_map_conf(struct p5pb_softc *); 108 uint8_t p5pb_find_resources(struct p5pb_softc *); 109 static bool p5pb_identify_bridge(struct p5pb_softc *); 110 void p5pb_membar_grex(struct p5pb_softc *); 111 static bool p5pb_cvppc_probe(struct p5pb_softc *); 112 #ifdef PCI_NETBSD_CONFIGURE 113 bool p5pb_bus_reconfigure(struct p5pb_softc *); 114 #endif /* PCI_NETBSD_CONFIGURE */ 115 #ifdef P5PB_DEBUG 116 void p5pb_usable_ranges(struct p5pb_softc *); 117 void p5pb_badaddr_range(struct p5pb_softc *, bus_space_tag_t, 118 bus_addr_t, size_t); 119 void p5pb_conf_search(struct p5pb_softc *, uint16_t); 120 #endif /* P5PB_DEBUG */ 121 122 CFATTACH_DECL_NEW(p5pb, sizeof(struct p5pb_softc), 123 p5pb_match, p5pb_attach, NULL, NULL); 124 125 static int 126 p5pb_match(device_t parent, cfdata_t cf, void *aux) 127 { 128 struct p5bus_attach_args *p5baa; 129 130 p5baa = (struct p5bus_attach_args *) aux; 131 132 if (strcmp(p5baa->p5baa_name, "p5pb") == 0) 133 return 1; 134 135 return 0; 136 } 137 138 static void 139 p5pb_attach(device_t parent, device_t self, void *aux) 140 { 141 struct p5pb_softc *sc; 142 struct pcibus_attach_args pba; 143 144 sc = device_private(self); 145 sc->sc_dev = self; 146 sc->p5baa = (struct p5bus_attach_args *) aux; 147 148 pci_chipset_tag_t pc = &sc->apc; 149 150 if (!p5pb_bus_map_conf(sc)) { 151 aprint_error_dev(self, 152 "couldn't map PCI configuration space\n"); 153 return; 154 } 155 156 if (!p5pb_identify_bridge(sc)) { 157 return; 158 } 159 160 if (sc->bridge_type == P5PB_BRIDGE_CVPPC) { 161 sc->pci_mem_lowest = P5BUS_PCI_MEM_BASE; 162 sc->pci_mem_highest = P5BUS_PCI_MEM_BASE + P5BUS_PCI_MEM_SIZE; 163 } else { 164 p5pb_membar_grex(sc); 165 } 166 167 if (!p5pb_bus_map_memio(sc)) { 168 aprint_error_dev(self, 169 "couldn't map PCI I/O and memory space\n"); 170 return; 171 } 172 173 #ifdef P5PB_DEBUG 174 aprint_normal("p5pb: map conf %x -> %x, io %x -> %x, mem %x -> %x\n", 175 kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base, 176 kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base, 177 kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base ); 178 #endif 179 180 /* Initialize the PCI chipset tag. */ 181 182 if (sc->bridge_type == P5PB_BRIDGE_GREX1200) 183 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex1200; 184 else if (sc->bridge_type == P5PB_BRIDGE_GREX4000) 185 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex4000; 186 else 187 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_cvppc; 188 189 sc->apc.pc_conf_v = (void*) pc; 190 sc->apc.pc_make_tag = amiga_pci_make_tag; 191 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag; 192 sc->apc.pc_conf_read = p5pb_pci_conf_read; 193 sc->apc.pc_conf_write = p5pb_pci_conf_write; 194 sc->apc.pc_conf_hook = p5pb_pci_conf_hook; 195 sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt; 196 sc->apc.pc_attach_hook = p5pb_pci_attach_hook; 197 198 sc->apc.pc_intr_map = p5pb_pci_intr_map; 199 sc->apc.pc_intr_string = amiga_pci_intr_string; 200 sc->apc.pc_intr_establish = amiga_pci_intr_establish; 201 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish; 202 203 #ifdef PCI_NETBSD_CONFIGURE 204 /* Never reconfigure the bus on CVPPC/BVPPC, avoid the fb breakage. */ 205 if (sc->bridge_type != P5PB_BRIDGE_CVPPC) { 206 p5pb_bus_reconfigure(sc); 207 } 208 #endif /* PCI_NETBSD_CONFIGURE */ 209 210 /* Initialize the bus attachment structure. */ 211 212 pba.pba_iot = &(sc->pci_io_area); 213 pba.pba_memt = &(sc->pci_mem_area); 214 pba.pba_dmat = &p5pb_bus_dma_tag; 215 pba.pba_dmat64 = NULL; 216 pba.pba_pc = pc; 217 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 218 pba.pba_bus = 0; 219 pba.pba_bridgetag = NULL; 220 221 p5pb_set_props(sc); 222 223 config_found_ia(self, "pcibus", &pba, pcibusprint); 224 } 225 226 /* 227 * Try to detect what kind of bridge are we dealing with. 228 */ 229 static bool 230 p5pb_identify_bridge(struct p5pb_softc *sc) 231 { 232 int pcires_count; /* Number of AutoConfig(TM) PCI resources */ 233 234 pcires_count = p5pb_find_resources(sc); 235 236 switch (pcires_count) { 237 case 0: 238 /* 239 * Zero AutoConfig(TM) PCI resources, means that there's nothing 240 * OR there's a CVPPC/BVPPC with a pre-44.69 firmware. 241 */ 242 if (p5pb_cvppc_probe(sc)) { 243 sc->bridge_type = P5PB_BRIDGE_CVPPC; 244 aprint_normal(": Phase5 CVPPC/BVPPC PCI bridge\n"); 245 } else { 246 aprint_normal(": no PCI bridges detected\n"); 247 return false; 248 } 249 break; 250 case 6: 251 /* 252 * We have a slight possibility, that there's a CVPPC/BVPPC with 253 * the new firmware. So check for it first. 254 */ 255 if (p5pb_cvppc_probe(sc)) { 256 /* New firmware, treat as one-slot GREX. */ 257 sc->bridge_type = P5PB_BRIDGE_CVPPC; 258 aprint_normal( 259 ": Phase5 CVPPC/BVPPC PCI bridge (44.69/44.71)\n"); 260 break; 261 } 262 default: 263 /* We have a G-REX surely. */ 264 265 if (sc->p5baa->p5baa_cardtype == P5_CARDTYPE_CS) { 266 sc->bridge_type = P5PB_BRIDGE_GREX4000; 267 aprint_normal(": DCE G-REX 4000 PCI bridge\n"); 268 } else { 269 sc->bridge_type = P5PB_BRIDGE_GREX1200; 270 aprint_normal(": DCE G-REX 1200 PCI bridge\n"); 271 } 272 break; 273 } 274 return true; 275 } 276 277 /* 278 * Find AutoConfig(TM) resuorces (for boards running G-REX firmware). Return the 279 * total number of found resources. 280 */ 281 uint8_t 282 p5pb_find_resources(struct p5pb_softc *sc) 283 { 284 uint8_t i, rv; 285 struct p5pb_autoconf_entry *auto_entry; 286 struct p5membar_softc *membar_sc; 287 device_t p5membar_dev; 288 289 rv = 0; 290 291 TAILQ_INIT(&sc->auto_bars); 292 293 /* 255 should be enough for everybody */ 294 for(i = 0; i < 255; i++) { 295 296 if ((p5membar_dev = 297 device_find_by_driver_unit("p5membar", i)) != NULL) { 298 299 rv++; 300 301 membar_sc = device_private(p5membar_dev); 302 if (membar_sc->sc_type == P5MEMBAR_TYPE_INTERNAL) 303 continue; 304 305 auto_entry = 306 kmem_alloc(sizeof(struct p5pb_autoconf_entry), 307 KM_SLEEP); 308 309 auto_entry->base = membar_sc->sc_base; 310 auto_entry->size = membar_sc->sc_size; 311 312 TAILQ_INSERT_TAIL(&sc->auto_bars, auto_entry, entries); 313 } 314 } 315 return rv; 316 } 317 318 /* 319 * Set properties needed to support fb driver. These are read later during 320 * autoconfg in device_register(). Needed for CVPPC/BVPPC. 321 */ 322 void 323 p5pb_set_props(struct p5pb_softc *sc) 324 { 325 #if NGENFB > 0 326 prop_dictionary_t dict; 327 device_t dev; 328 329 dev = sc->sc_dev; 330 dict = device_properties(dev); 331 332 /* genfb needs additional properties, like virtual, physical address */ 333 /* XXX: currently genfb is supported only on CVPPC/BVPPC */ 334 prop_dictionary_set_uint64(dict, "virtual_address", 335 sc->pci_mem_area.base); 336 prop_dictionary_set_uint64(dict, "address", 337 kvtop((void*) sc->pci_mem_area.base)); 338 #endif 339 } 340 341 pcireg_t 342 p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 343 { 344 uint32_t data; 345 uint32_t bus, dev, func; 346 uint32_t offset; 347 348 if ((unsigned int)reg >= PCI_CONF_SIZE) 349 return 0xFFFFFFFF; 350 351 pci_decompose_tag(pc, tag, &bus, &dev, &func); 352 353 offset = (OFF_PCI_DEVICE << dev) + reg; 354 355 if(func == 0) /* ugly, ugly hack */ 356 offset += 0; 357 else if(func == 1) 358 offset += OFF_PCI_FUNCTION; 359 else 360 return 0xFFFFFFFF; 361 362 if(badaddr((void *)__UNVOLATILE(((uint32_t) 363 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 364 + offset)))) 365 return 0xFFFFFFFF; 366 367 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah, 368 offset); 369 #ifdef P5PB_DEBUG_CONF 370 aprint_normal("p5pb conf read va: %lx, bus: %d, dev: %d, " 371 "func: %d, reg: %d -r-> data %x\n", 372 pc->pci_conf_datah, bus, dev, func, reg, data); 373 #endif 374 return data; 375 } 376 377 void 378 p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 379 { 380 uint32_t bus, dev, func; 381 uint32_t offset; 382 383 if ((unsigned int)reg >= PCI_CONF_SIZE) 384 return; 385 386 pci_decompose_tag(pc, tag, &bus, &dev, &func); 387 388 offset = (OFF_PCI_DEVICE << dev) + reg; 389 390 if(func == 0) /* ugly, ugly hack */ 391 offset += 0; 392 else if(func == 1) 393 offset += OFF_PCI_FUNCTION; 394 else 395 return; 396 397 if(badaddr((void *)__UNVOLATILE(((uint32_t) 398 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 399 + offset)))) 400 return; 401 402 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah, 403 offset, val); 404 #ifdef P5PB_DEBUG_CONF 405 aprint_normal("p5pb conf write va: %lx, bus: %d, dev: %d, " 406 "func: %d, reg: %d -w-> data %x\n", 407 pc->pci_conf_datah, bus, dev, func, reg, val); 408 #endif 409 410 } 411 412 int 413 p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t pc, int busno) 414 { 415 /* CVPPC/BVPPC has only 1 "slot". */ 416 return 1; 417 } 418 419 int 420 p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t pc, int busno) 421 { 422 /* G-REX 4000 has 4, G-REX 4000T has 3 slots? */ 423 return 4; 424 } 425 426 int 427 p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t pc, int busno) 428 { 429 /* G-REX 1200 has 5 slots. */ 430 return 4; /* XXX: 5 not yet! */ 431 } 432 433 void 434 p5pb_pci_attach_hook(device_t parent, device_t self, 435 struct pcibus_attach_args *pba) 436 { 437 } 438 439 int 440 p5pb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 441 { 442 /* TODO: add sanity checking */ 443 444 *ihp = 2; 445 return 0; 446 } 447 448 /* Probe for CVPPC/BVPPC. */ 449 static bool 450 p5pb_cvppc_probe(struct p5pb_softc *sc) 451 { 452 bus_space_handle_t probe_h; 453 uint16_t prodid, manid; 454 void* data; 455 bool rv; 456 457 manid = 0; prodid = 0; 458 rv = false; 459 460 if (bus_space_map(sc->apc.pci_conf_datat, 0, 4, 0, &probe_h)) 461 return rv; 462 463 data = bus_space_vaddr(sc->apc.pci_conf_datat, probe_h); 464 465 if (badaddr((void *)__UNVOLATILE((uint32_t) data))) { 466 #ifdef P5PB_DEBUG_PROBE 467 aprint_normal("p5pb: CVPPC configuration space not usable!\n"); 468 #endif /* P5PB_DEBUG_PROBE */ 469 } else { 470 prodid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 0); 471 manid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 2); 472 473 if ((prodid == P5PB_PM2_PRODUCT_ID) && 474 (manid == P5PB_PM2_VENDOR_ID)) 475 rv = true; 476 } 477 478 #ifdef P5PB_DEBUG_PROBE 479 aprint_normal("p5pb: CVPPC probe for PCI ID: %x, %x returns %d\n", 480 manid, prodid, (int) rv); 481 #endif /* P5PB_DEBUG_PROBE */ 482 483 bus_space_unmap(sc->apc.pci_conf_datat, probe_h, 4); 484 return rv; 485 } 486 487 #ifdef PCI_NETBSD_CONFIGURE 488 /* Reconfigure the bus. */ 489 bool 490 p5pb_bus_reconfigure(struct p5pb_softc *sc) 491 { 492 struct extent *ioext, *memext; 493 pci_chipset_tag_t pc; 494 495 pc = &sc->apc; 496 497 ioext = extent_create("p5pbio", 0, P5BUS_PCI_IO_SIZE, NULL, 0, 498 EX_NOWAIT); 499 500 memext = extent_create("p5pbmem", sc->pci_mem_lowest, 501 sc->pci_mem_highest - 1, NULL, 0, EX_NOWAIT); 502 503 if ( (!ioext) || (!memext) ) 504 return false; 505 506 #ifdef P5PB_DEBUG 507 aprint_normal("p5pb: reconfiguring the bus!\n"); 508 #endif /* P5PB_DEBUG */ 509 pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE); 510 511 extent_destroy(ioext); 512 extent_destroy(memext); 513 514 return true; /* TODO: better error handling */ 515 } 516 #endif /* PCI_NETBSD_CONFIGURE */ 517 518 /* Determine the PCI memory space (done G-REX-style). */ 519 void 520 p5pb_membar_grex(struct p5pb_softc *sc) 521 { 522 struct p5pb_autoconf_entry *membar_entry; 523 uint32_t bar_address; 524 525 sc->pci_mem_lowest = 0xFFFFFFFF; 526 sc->pci_mem_highest = 0; 527 528 /* Iterate over membar entries to find lowest and highest address. */ 529 TAILQ_FOREACH(membar_entry, &sc->auto_bars, entries) { 530 531 bar_address = (uint32_t) membar_entry->base; 532 if ((bar_address + membar_entry->size) > sc->pci_mem_highest) 533 sc->pci_mem_highest = bar_address + membar_entry->size; 534 if (bar_address < sc->pci_mem_lowest) 535 sc->pci_mem_lowest = bar_address; 536 537 #ifdef P5PB_DEBUG_BAR 538 aprint_normal("p5pb: %d kB mem BAR at %p, hi = %x, lo = %x\n", 539 membar_entry->size / 1024, membar_entry->base, 540 sc->pci_mem_highest, sc->pci_mem_lowest); 541 #endif /* P5PB_DEBUG_BAR */ 542 } 543 544 aprint_normal("p5pb: %d kB PCI memory space (%8p to %8p)\n", 545 (sc->pci_mem_highest - sc->pci_mem_lowest) / 1024, 546 (void*) sc->pci_mem_lowest, (void*) sc->pci_mem_highest); 547 548 } 549 550 bool 551 p5pb_bus_map_conf(struct p5pb_softc *sc) 552 { 553 sc->pci_conf_area.base = (bus_addr_t) zbusmap( 554 (void *) P5BUS_PCI_CONF_BASE, P5BUS_PCI_CONF_SIZE); 555 sc->pci_conf_area.absm = &amiga_bus_stride_1; 556 557 sc->apc.pci_conf_datat = &(sc->pci_conf_area); 558 559 if (bus_space_map(sc->apc.pci_conf_datat, OFF_PCI_CONF_DATA, 560 P5BUS_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah)) 561 return false; 562 563 return true; 564 } 565 566 /* Map I/O and memory space. */ 567 bool 568 p5pb_bus_map_memio(struct p5pb_softc *sc) 569 { 570 sc->pci_io_area.base = (bus_addr_t) zbusmap( 571 (void *) P5BUS_PCI_IO_BASE, P5BUS_PCI_IO_SIZE); 572 sc->pci_io_area.absm = &amiga_bus_stride_1swap; 573 574 sc->pci_mem_area.base = (bus_addr_t) zbusmap( 575 (void *) sc->pci_mem_lowest, 576 sc->pci_mem_highest - sc->pci_mem_lowest); 577 sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs; 578 579 return true; 580 } 581 582 int 583 p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, 584 int func, pcireg_t id) 585 { 586 /* XXX: What should we do on CVPPC/BVPPC? It breaks genfb. */ 587 588 return PCI_CONF_DEFAULT; 589 } 590 591 #ifdef P5PB_DEBUG 592 /* Check which config and I/O ranges are usable. */ 593 void 594 p5pb_usable_ranges(struct p5pb_softc *sc) 595 { 596 p5pb_badaddr_range(sc, &(sc->pci_conf_area), 0, P5BUS_PCI_CONF_SIZE); 597 p5pb_badaddr_range(sc, &(sc->pci_io_area), 0, P5BUS_PCI_IO_SIZE); 598 } 599 600 void 601 p5pb_badaddr_range(struct p5pb_softc *sc, bus_space_tag_t bust, bus_addr_t base, 602 size_t len) 603 { 604 int i, state, prev_state; 605 bus_space_handle_t bush; 606 volatile void *data; 607 608 state = -1; 609 prev_state = -1; 610 611 bus_space_map(bust, base, len, 0, &bush); 612 613 aprint_normal("p5pb: badaddr range check from %x (%x) to %x (%x)\n", 614 (bus_addr_t) bush, /* start VA */ 615 (bus_addr_t) kvtop((void*) bush), /* start PA */ 616 (bus_addr_t) bush + len, /* end VA */ 617 (bus_addr_t) kvtop((void*) (bush + len)));/* end PA */ 618 619 data = bus_space_vaddr(bust, bush); 620 621 for(i = 0; i < len; i++) { 622 state = badaddr((void *)__UNVOLATILE(((uint32_t) data + i))); 623 if(state != prev_state) { 624 aprint_normal("p5pb: badaddr %p (%x) : %d\n", 625 (void*) ((uint32_t) data + i), 626 (bus_addr_t) kvtop((void*) ((uint32_t) data + i)), 627 state); 628 prev_state = state; 629 } 630 631 } 632 633 bus_space_unmap(bust, bush, len); 634 } 635 636 /* Search for 16-bit value in the configuration space. */ 637 void 638 p5pb_conf_search(struct p5pb_softc *sc, uint16_t val) 639 { 640 int i, state; 641 uint16_t readv; 642 void *va; 643 644 va = bus_space_vaddr(sc->apc.pci_conf_datat, sc->apc.pci_conf_datah); 645 646 for (i = 0; i < P5BUS_PCI_CONF_SIZE; i++) { 647 state = badaddr((void *)__UNVOLATILE(((uint32_t) va + i))); 648 if(state == 0) { 649 readv = bus_space_read_2(sc->apc.pci_conf_datat, 650 sc->apc.pci_conf_datah, i); 651 if(readv == val) 652 aprint_normal("p5pb: found val %x @ %x (%x)\n", 653 readv, (uint32_t) sc->apc.pci_conf_datah 654 + i, (bus_addr_t) kvtop((void*) 655 ((uint32_t) sc->apc.pci_conf_datah + i))); 656 } 657 } 658 } 659 660 #endif /* P5PB_DEBUG */ 661 662 #ifdef P5PB_CONSOLE 663 void 664 p5pb_device_register(device_t dev, void *aux) 665 { 666 prop_dictionary_t dict, parent_dict; 667 struct pci_attach_args *pa = aux; 668 669 if (device_parent(dev) && device_is_a(device_parent(dev), "pci")) { 670 671 dict = device_properties(dev); 672 673 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 674 675 /* Handle the CVPPC/BVPPC card... */ 676 if ( ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TI) 677 && (PCI_PRODUCT(pa->pa_id) == 678 PCI_PRODUCT_TI_TVP4020) ) || 679 /* ...and 3Dfx Voodoo 3 in G-REX. */ 680 ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) 681 && (PCI_PRODUCT(pa->pa_id) == 682 PCI_PRODUCT_3DFX_VOODOO3) )) { 683 684 parent_dict = device_properties( 685 device_parent(device_parent(dev))); 686 687 prop_dictionary_set_uint32(dict, "width", 688 P5GFX_WIDTH); 689 690 prop_dictionary_set_uint32(dict, "height", 691 P5GFX_HEIGHT); 692 693 prop_dictionary_set_uint32(dict, "depth", 694 P5GFX_DEPTH); 695 696 #if NGENFB > 0 697 prop_dictionary_set_uint32(dict, "linebytes", 698 P5GFX_LINEBYTES); 699 700 prop_dictionary_set(dict, "address", 701 prop_dictionary_get(parent_dict, 702 "address")); 703 prop_dictionary_set(dict, "virtual_address", 704 prop_dictionary_get(parent_dict, 705 "virtual_address")); 706 #endif 707 prop_dictionary_set_bool(dict, "is_console", 708 true); 709 } 710 } 711 } 712 } 713 #endif /* P5PB_CONSOLE */ 714
Indexes created Tue Sep 30 20:09:53 GMT 2025