p5pb.c revision 1.19
1 /* $NetBSD: p5pb.c,v 1.19 2021/08/07 16:18:42 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/kmem.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #define _M68K_BUS_DMA_PRIVATE 44 #include <machine/bus.h> 45 #include <machine/cpu.h> 46 47 #include <m68k/bus_dma.h> 48 #include <amiga/dev/zbusvar.h> 49 #include <amiga/dev/p5busvar.h> 50 #include <amiga/pci/p5pbreg.h> 51 #include <amiga/pci/p5pbvar.h> 52 #include <amiga/pci/p5membarvar.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcidevs.h> 57 #ifdef PCI_NETBSD_CONFIGURE 58 #include <dev/pci/pciconf.h> 59 #endif /* PCI_NETBSD_CONFIGURE */ 60 61 #include "opt_p5pb.h" 62 #include "opt_pci.h" 63 #include "genfb.h" 64 65 /* Initial CVPPC/BVPPC resolution as configured by the firmware */ 66 #define P5GFX_WIDTH 640 67 #define P5GFX_HEIGHT 480 68 #define P5GFX_DEPTH 8 69 #define P5GFX_LINEBYTES 640 70 71 struct m68k_bus_dma_tag p5pb_bus_dma_tag = { 72 0, 73 0, 74 _bus_dmamap_create, 75 _bus_dmamap_destroy, 76 _bus_dmamap_load_direct, 77 _bus_dmamap_load_mbuf_direct, 78 _bus_dmamap_load_uio_direct, 79 _bus_dmamap_load_raw_direct, 80 _bus_dmamap_unload, 81 _bus_dmamap_sync, 82 _bus_dmamem_alloc, 83 _bus_dmamem_free, 84 _bus_dmamem_map, 85 _bus_dmamem_unmap, 86 _bus_dmamem_mmap 87 }; 88 89 static int p5pb_match(device_t, cfdata_t, void *); 90 static void p5pb_attach(device_t, device_t, void *); 91 void p5pb_set_props(struct p5pb_softc *); 92 pcireg_t p5pb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 93 void p5pb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 94 int p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t, int); 95 int p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t, int); 96 int p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t, int); 97 int p5pb_pci_conf_hook(pci_chipset_tag_t, int, int, int, pcireg_t); 98 void p5pb_pci_attach_hook (device_t, device_t, 99 struct pcibus_attach_args *); 100 pcitag_t p5pb_pci_make_tag(pci_chipset_tag_t, int, int, int); 101 void p5pb_pci_decompose_tag(pci_chipset_tag_t, pcitag_t, 102 int *, int *, int *); 103 int p5pb_pci_intr_map(const struct pci_attach_args *, 104 pci_intr_handle_t *); 105 bool p5pb_bus_map_memio(struct p5pb_softc *); 106 bool p5pb_bus_map_conf(struct p5pb_softc *); 107 uint8_t p5pb_find_resources(struct p5pb_softc *); 108 static bool p5pb_identify_bridge(struct p5pb_softc *); 109 void p5pb_membar_grex(struct p5pb_softc *); 110 static bool p5pb_cvppc_probe(struct p5pb_softc *); 111 #ifdef PCI_NETBSD_CONFIGURE 112 bool p5pb_bus_reconfigure(struct p5pb_softc *); 113 #endif /* PCI_NETBSD_CONFIGURE */ 114 #ifdef P5PB_DEBUG 115 void p5pb_usable_ranges(struct p5pb_softc *); 116 void p5pb_badaddr_range(struct p5pb_softc *, bus_space_tag_t, 117 bus_addr_t, size_t); 118 void p5pb_conf_search(struct p5pb_softc *, uint16_t); 119 #endif /* P5PB_DEBUG */ 120 121 CFATTACH_DECL_NEW(p5pb, sizeof(struct p5pb_softc), 122 p5pb_match, p5pb_attach, NULL, NULL); 123 124 static int 125 p5pb_match(device_t parent, cfdata_t cf, void *aux) 126 { 127 struct p5bus_attach_args *p5baa; 128 129 p5baa = (struct p5bus_attach_args *) aux; 130 131 if (strcmp(p5baa->p5baa_name, "p5pb") == 0) 132 return 1; 133 134 return 0; 135 } 136 137 static void 138 p5pb_attach(device_t parent, device_t self, void *aux) 139 { 140 struct p5pb_softc *sc; 141 struct pcibus_attach_args pba; 142 143 sc = device_private(self); 144 sc->sc_dev = self; 145 sc->p5baa = (struct p5bus_attach_args *) aux; 146 147 pci_chipset_tag_t pc = &sc->apc; 148 149 if (!p5pb_bus_map_conf(sc)) { 150 aprint_error_dev(self, 151 "couldn't map PCI configuration space\n"); 152 return; 153 } 154 155 if (!p5pb_identify_bridge(sc)) { 156 return; 157 } 158 159 if (sc->bridge_type == P5PB_BRIDGE_CVPPC) { 160 sc->pci_mem_lowest = P5BUS_PCI_MEM_BASE; 161 sc->pci_mem_highest = P5BUS_PCI_MEM_BASE + P5BUS_PCI_MEM_SIZE; 162 } else { 163 p5pb_membar_grex(sc); 164 } 165 166 if (!p5pb_bus_map_memio(sc)) { 167 aprint_error_dev(self, 168 "couldn't map PCI I/O and memory space\n"); 169 return; 170 } 171 172 #ifdef P5PB_DEBUG 173 aprint_normal("p5pb: map conf %x -> %x, io %x -> %x, mem %x -> %x\n", 174 kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base, 175 kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base, 176 kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base ); 177 #endif 178 179 /* Initialize the PCI chipset tag. */ 180 181 if (sc->bridge_type == P5PB_BRIDGE_GREX1200) 182 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex1200; 183 else if (sc->bridge_type == P5PB_BRIDGE_GREX4000) 184 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex4000; 185 else 186 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_cvppc; 187 188 sc->apc.pc_conf_v = (void*) pc; 189 sc->apc.pc_make_tag = amiga_pci_make_tag; 190 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag; 191 sc->apc.pc_conf_read = p5pb_pci_conf_read; 192 sc->apc.pc_conf_write = p5pb_pci_conf_write; 193 sc->apc.pc_conf_hook = p5pb_pci_conf_hook; 194 sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt; 195 sc->apc.pc_attach_hook = p5pb_pci_attach_hook; 196 197 sc->apc.pc_intr_map = p5pb_pci_intr_map; 198 sc->apc.pc_intr_string = amiga_pci_intr_string; 199 sc->apc.pc_intr_establish = amiga_pci_intr_establish; 200 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish; 201 202 #ifdef PCI_NETBSD_CONFIGURE 203 /* Never reconfigure the bus on CVPPC/BVPPC, avoid the fb breakage. */ 204 if (sc->bridge_type != P5PB_BRIDGE_CVPPC) { 205 p5pb_bus_reconfigure(sc); 206 } 207 #endif /* PCI_NETBSD_CONFIGURE */ 208 209 /* Initialize the bus attachment structure. */ 210 211 pba.pba_iot = &(sc->pci_io_area); 212 pba.pba_memt = &(sc->pci_mem_area); 213 pba.pba_dmat = &p5pb_bus_dma_tag; 214 pba.pba_dmat64 = NULL; 215 pba.pba_pc = pc; 216 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 217 pba.pba_bus = 0; 218 pba.pba_bridgetag = NULL; 219 220 p5pb_set_props(sc); 221 222 config_found(self, &pba, pcibusprint, CFARGS_NONE); 223 } 224 225 /* 226 * Try to detect what kind of bridge are we dealing with. 227 */ 228 static bool 229 p5pb_identify_bridge(struct p5pb_softc *sc) 230 { 231 int pcires_count; /* Number of AutoConfig(TM) PCI resources */ 232 233 pcires_count = p5pb_find_resources(sc); 234 235 switch (pcires_count) { 236 case 0: 237 /* 238 * Zero AutoConfig(TM) PCI resources, means that there's nothing 239 * OR there's a CVPPC/BVPPC with a pre-44.69 firmware. 240 */ 241 if (p5pb_cvppc_probe(sc)) { 242 sc->bridge_type = P5PB_BRIDGE_CVPPC; 243 aprint_normal(": Phase5 CVPPC/BVPPC PCI bridge\n"); 244 } else { 245 aprint_normal(": no PCI bridges detected\n"); 246 return false; 247 } 248 break; 249 case 6: 250 /* 251 * We have a slight possibility, that there's a CVPPC/BVPPC with 252 * the new firmware. So check for it first. 253 */ 254 if (p5pb_cvppc_probe(sc)) { 255 /* New firmware, treat as one-slot GREX. */ 256 sc->bridge_type = P5PB_BRIDGE_CVPPC; 257 aprint_normal( 258 ": Phase5 CVPPC/BVPPC PCI bridge (44.69/44.71)\n"); 259 break; 260 } 261 default: 262 /* We have a G-REX surely. */ 263 264 if (sc->p5baa->p5baa_cardtype == P5_CARDTYPE_CS) { 265 sc->bridge_type = P5PB_BRIDGE_GREX4000; 266 aprint_normal(": DCE G-REX 4000 PCI bridge\n"); 267 } else { 268 sc->bridge_type = P5PB_BRIDGE_GREX1200; 269 aprint_normal(": DCE G-REX 1200 PCI bridge\n"); 270 } 271 break; 272 } 273 return true; 274 } 275 276 /* 277 * Find AutoConfig(TM) resuorces (for boards running G-REX firmware). Return the 278 * total number of found resources. 279 */ 280 uint8_t 281 p5pb_find_resources(struct p5pb_softc *sc) 282 { 283 uint8_t i, rv; 284 struct p5pb_autoconf_entry *auto_entry; 285 struct p5membar_softc *membar_sc; 286 device_t p5membar_dev; 287 288 rv = 0; 289 290 TAILQ_INIT(&sc->auto_bars); 291 292 /* 255 should be enough for everybody */ 293 for(i = 0; i < 255; i++) { 294 295 if ((p5membar_dev = 296 device_find_by_driver_unit("p5membar", i)) != NULL) { 297 298 rv++; 299 300 membar_sc = device_private(p5membar_dev); 301 if (membar_sc->sc_type == P5MEMBAR_TYPE_INTERNAL) 302 continue; 303 304 auto_entry = 305 kmem_alloc(sizeof(struct p5pb_autoconf_entry), 306 KM_SLEEP); 307 308 auto_entry->base = membar_sc->sc_base; 309 auto_entry->size = membar_sc->sc_size; 310 311 TAILQ_INSERT_TAIL(&sc->auto_bars, auto_entry, entries); 312 } 313 } 314 return rv; 315 } 316 317 /* 318 * Set properties needed to support fb driver. These are read later during 319 * autoconfg in device_register(). Needed for CVPPC/BVPPC. 320 */ 321 void 322 p5pb_set_props(struct p5pb_softc *sc) 323 { 324 #if NGENFB > 0 325 prop_dictionary_t dict; 326 device_t dev; 327 328 dev = sc->sc_dev; 329 dict = device_properties(dev); 330 331 /* genfb needs additional properties, like virtual, physical address */ 332 /* XXX: currently genfb is supported only on CVPPC/BVPPC */ 333 prop_dictionary_set_uint64(dict, "virtual_address", 334 sc->pci_mem_area.base); 335 prop_dictionary_set_uint64(dict, "address", 336 kvtop((void*) sc->pci_mem_area.base)); 337 #endif 338 } 339 340 pcireg_t 341 p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 342 { 343 uint32_t data; 344 uint32_t bus, dev, func; 345 uint32_t offset; 346 347 if ((unsigned int)reg >= PCI_CONF_SIZE) 348 return 0xFFFFFFFF; 349 350 pci_decompose_tag(pc, tag, &bus, &dev, &func); 351 352 offset = (OFF_PCI_DEVICE << dev) + reg; 353 354 if(func == 0) /* ugly, ugly hack */ 355 offset += 0; 356 else if(func == 1) 357 offset += OFF_PCI_FUNCTION; 358 else 359 return 0xFFFFFFFF; 360 361 if(badaddr((void *)__UNVOLATILE(((uint32_t) 362 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 363 + offset)))) 364 return 0xFFFFFFFF; 365 366 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah, 367 offset); 368 #ifdef P5PB_DEBUG_CONF 369 aprint_normal("p5pb conf read va: %lx, bus: %d, dev: %d, " 370 "func: %d, reg: %d -r-> data %x\n", 371 pc->pci_conf_datah, bus, dev, func, reg, data); 372 #endif 373 return data; 374 } 375 376 void 377 p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 378 { 379 uint32_t bus, dev, func; 380 uint32_t offset; 381 382 if ((unsigned int)reg >= PCI_CONF_SIZE) 383 return; 384 385 pci_decompose_tag(pc, tag, &bus, &dev, &func); 386 387 offset = (OFF_PCI_DEVICE << dev) + reg; 388 389 if(func == 0) /* ugly, ugly hack */ 390 offset += 0; 391 else if(func == 1) 392 offset += OFF_PCI_FUNCTION; 393 else 394 return; 395 396 if(badaddr((void *)__UNVOLATILE(((uint32_t) 397 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 398 + offset)))) 399 return; 400 401 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah, 402 offset, val); 403 #ifdef P5PB_DEBUG_CONF 404 aprint_normal("p5pb conf write va: %lx, bus: %d, dev: %d, " 405 "func: %d, reg: %d -w-> data %x\n", 406 pc->pci_conf_datah, bus, dev, func, reg, val); 407 #endif 408 409 } 410 411 int 412 p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t pc, int busno) 413 { 414 /* CVPPC/BVPPC has only 1 "slot". */ 415 return 1; 416 } 417 418 int 419 p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t pc, int busno) 420 { 421 /* G-REX 4000 has 4, G-REX 4000T has 3 slots? */ 422 return 4; 423 } 424 425 int 426 p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t pc, int busno) 427 { 428 /* G-REX 1200 has 5 slots. */ 429 return 4; /* XXX: 5 not yet! */ 430 } 431 432 void 433 p5pb_pci_attach_hook(device_t parent, device_t self, 434 struct pcibus_attach_args *pba) 435 { 436 } 437 438 int 439 p5pb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 440 { 441 /* TODO: add sanity checking */ 442 443 *ihp = 2; 444 return 0; 445 } 446 447 /* Probe for CVPPC/BVPPC. */ 448 static bool 449 p5pb_cvppc_probe(struct p5pb_softc *sc) 450 { 451 bus_space_handle_t probe_h; 452 uint16_t prodid, manid; 453 void* data; 454 bool rv; 455 456 manid = 0; prodid = 0; 457 rv = false; 458 459 if (bus_space_map(sc->apc.pci_conf_datat, 0, 4, 0, &probe_h)) 460 return rv; 461 462 data = bus_space_vaddr(sc->apc.pci_conf_datat, probe_h); 463 464 if (badaddr((void *)__UNVOLATILE((uint32_t) data))) { 465 #ifdef P5PB_DEBUG_PROBE 466 aprint_normal("p5pb: CVPPC configuration space not usable!\n"); 467 #endif /* P5PB_DEBUG_PROBE */ 468 } else { 469 prodid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 0); 470 manid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 2); 471 472 if ((prodid == P5PB_PM2_PRODUCT_ID) && 473 (manid == P5PB_PM2_VENDOR_ID)) 474 rv = true; 475 } 476 477 #ifdef P5PB_DEBUG_PROBE 478 aprint_normal("p5pb: CVPPC probe for PCI ID: %x, %x returns %d\n", 479 manid, prodid, (int) rv); 480 #endif /* P5PB_DEBUG_PROBE */ 481 482 bus_space_unmap(sc->apc.pci_conf_datat, probe_h, 4); 483 return rv; 484 } 485 486 #ifdef PCI_NETBSD_CONFIGURE 487 /* Reconfigure the bus. */ 488 bool 489 p5pb_bus_reconfigure(struct p5pb_softc *sc) 490 { 491 pci_chipset_tag_t pc; 492 493 pc = &sc->apc; 494 495 struct pciconf_resources *pcires = pciconf_resource_init(); 496 497 pciconf_resource_add(pcires, PCICONF_RESOURCE_IO, 498 0, P5BUS_PCI_IO_SIZE); 499 pciconf_resource_add(pcires, PCICONF_RESOURCE_MEM, 500 sc->pci_mem_lowest, sc->pci_mem_highest - sc->pci_mem_lowest); 501 502 #ifdef P5PB_DEBUG 503 aprint_normal("p5pb: reconfiguring the bus!\n"); 504 #endif /* P5PB_DEBUG */ 505 pci_configure_bus(pc, pcires, 0, CACHELINE_SIZE); 506 507 pciconf_resource_fini(pcires); 508 509 return true; /* TODO: better error handling */ 510 } 511 #endif /* PCI_NETBSD_CONFIGURE */ 512 513 /* Determine the PCI memory space (done G-REX-style). */ 514 void 515 p5pb_membar_grex(struct p5pb_softc *sc) 516 { 517 struct p5pb_autoconf_entry *membar_entry; 518 uint32_t bar_address; 519 520 sc->pci_mem_lowest = 0xFFFFFFFF; 521 sc->pci_mem_highest = 0; 522 523 /* Iterate over membar entries to find lowest and highest address. */ 524 TAILQ_FOREACH(membar_entry, &sc->auto_bars, entries) { 525 526 bar_address = (uint32_t) membar_entry->base; 527 if ((bar_address + membar_entry->size) > sc->pci_mem_highest) 528 sc->pci_mem_highest = bar_address + membar_entry->size; 529 if (bar_address < sc->pci_mem_lowest) 530 sc->pci_mem_lowest = bar_address; 531 532 #ifdef P5PB_DEBUG_BAR 533 aprint_normal("p5pb: %d kB mem BAR at %p, hi = %x, lo = %x\n", 534 membar_entry->size / 1024, membar_entry->base, 535 sc->pci_mem_highest, sc->pci_mem_lowest); 536 #endif /* P5PB_DEBUG_BAR */ 537 } 538 539 aprint_normal("p5pb: %d kB PCI memory space (%8p to %8p)\n", 540 (sc->pci_mem_highest - sc->pci_mem_lowest) / 1024, 541 (void*) sc->pci_mem_lowest, (void*) sc->pci_mem_highest); 542 543 } 544 545 bool 546 p5pb_bus_map_conf(struct p5pb_softc *sc) 547 { 548 sc->pci_conf_area.base = (bus_addr_t) zbusmap( 549 (void *) P5BUS_PCI_CONF_BASE, P5BUS_PCI_CONF_SIZE); 550 sc->pci_conf_area.absm = &amiga_bus_stride_1; 551 552 sc->apc.pci_conf_datat = &(sc->pci_conf_area); 553 554 if (bus_space_map(sc->apc.pci_conf_datat, OFF_PCI_CONF_DATA, 555 P5BUS_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah)) 556 return false; 557 558 return true; 559 } 560 561 /* Map I/O and memory space. */ 562 bool 563 p5pb_bus_map_memio(struct p5pb_softc *sc) 564 { 565 sc->pci_io_area.base = (bus_addr_t) zbusmap( 566 (void *) P5BUS_PCI_IO_BASE, P5BUS_PCI_IO_SIZE); 567 sc->pci_io_area.absm = &amiga_bus_stride_1swap; 568 569 sc->pci_mem_area.base = (bus_addr_t) zbusmap( 570 (void *) sc->pci_mem_lowest, 571 sc->pci_mem_highest - sc->pci_mem_lowest); 572 sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs; 573 574 return true; 575 } 576 577 int 578 p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, 579 int func, pcireg_t id) 580 { 581 /* XXX: What should we do on CVPPC/BVPPC? It breaks genfb. */ 582 583 return PCI_CONF_DEFAULT; 584 } 585 586 #ifdef P5PB_DEBUG 587 /* Check which config and I/O ranges are usable. */ 588 void 589 p5pb_usable_ranges(struct p5pb_softc *sc) 590 { 591 p5pb_badaddr_range(sc, &(sc->pci_conf_area), 0, P5BUS_PCI_CONF_SIZE); 592 p5pb_badaddr_range(sc, &(sc->pci_io_area), 0, P5BUS_PCI_IO_SIZE); 593 } 594 595 void 596 p5pb_badaddr_range(struct p5pb_softc *sc, bus_space_tag_t bust, bus_addr_t base, 597 size_t len) 598 { 599 int i, state, prev_state; 600 bus_space_handle_t bush; 601 volatile void *data; 602 603 state = -1; 604 prev_state = -1; 605 606 bus_space_map(bust, base, len, 0, &bush); 607 608 aprint_normal("p5pb: badaddr range check from %x (%x) to %x (%x)\n", 609 (bus_addr_t) bush, /* start VA */ 610 (bus_addr_t) kvtop((void*) bush), /* start PA */ 611 (bus_addr_t) bush + len, /* end VA */ 612 (bus_addr_t) kvtop((void*) (bush + len)));/* end PA */ 613 614 data = bus_space_vaddr(bust, bush); 615 616 for(i = 0; i < len; i++) { 617 state = badaddr((void *)__UNVOLATILE(((uint32_t) data + i))); 618 if(state != prev_state) { 619 aprint_normal("p5pb: badaddr %p (%x) : %d\n", 620 (void*) ((uint32_t) data + i), 621 (bus_addr_t) kvtop((void*) ((uint32_t) data + i)), 622 state); 623 prev_state = state; 624 } 625 626 } 627 628 bus_space_unmap(bust, bush, len); 629 } 630 631 /* Search for 16-bit value in the configuration space. */ 632 void 633 p5pb_conf_search(struct p5pb_softc *sc, uint16_t val) 634 { 635 int i, state; 636 uint16_t readv; 637 void *va; 638 639 va = bus_space_vaddr(sc->apc.pci_conf_datat, sc->apc.pci_conf_datah); 640 641 for (i = 0; i < P5BUS_PCI_CONF_SIZE; i++) { 642 state = badaddr((void *)__UNVOLATILE(((uint32_t) va + i))); 643 if(state == 0) { 644 readv = bus_space_read_2(sc->apc.pci_conf_datat, 645 sc->apc.pci_conf_datah, i); 646 if(readv == val) 647 aprint_normal("p5pb: found val %x @ %x (%x)\n", 648 readv, (uint32_t) sc->apc.pci_conf_datah 649 + i, (bus_addr_t) kvtop((void*) 650 ((uint32_t) sc->apc.pci_conf_datah + i))); 651 } 652 } 653 } 654 655 #endif /* P5PB_DEBUG */ 656 657 #ifdef P5PB_CONSOLE 658 void 659 p5pb_device_register(device_t dev, void *aux) 660 { 661 prop_dictionary_t dict, parent_dict; 662 struct pci_attach_args *pa = aux; 663 664 if (device_parent(dev) && device_is_a(device_parent(dev), "pci")) { 665 666 dict = device_properties(dev); 667 668 if (PCI_CLASS(pa->pa_class) == PCI_CLASS_DISPLAY) { 669 670 /* Handle the CVPPC/BVPPC card... */ 671 if ( ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_TI) 672 && (PCI_PRODUCT(pa->pa_id) == 673 PCI_PRODUCT_TI_TVP4020) ) || 674 /* ...and 3Dfx Voodoo 3 in G-REX. */ 675 ((PCI_VENDOR(pa->pa_id) == PCI_VENDOR_3DFX) 676 && (PCI_PRODUCT(pa->pa_id) == 677 PCI_PRODUCT_3DFX_VOODOO3) )) { 678 679 parent_dict = device_properties( 680 device_parent(device_parent(dev))); 681 682 prop_dictionary_set_uint32(dict, "width", 683 P5GFX_WIDTH); 684 685 prop_dictionary_set_uint32(dict, "height", 686 P5GFX_HEIGHT); 687 688 prop_dictionary_set_uint32(dict, "depth", 689 P5GFX_DEPTH); 690 691 #if NGENFB > 0 692 prop_dictionary_set_uint32(dict, "linebytes", 693 P5GFX_LINEBYTES); 694 695 prop_dictionary_set(dict, "address", 696 prop_dictionary_get(parent_dict, 697 "address")); 698 prop_dictionary_set(dict, "virtual_address", 699 prop_dictionary_get(parent_dict, 700 "virtual_address")); 701 #endif 702 prop_dictionary_set_bool(dict, "is_console", 703 true); 704 } 705 } 706 } 707 } 708 #endif /* P5PB_CONSOLE */ 709
Indexes created Tue Sep 30 20:09:53 GMT 2025