p5pb.c revision 1.5
1 /* $NetBSD: p5pb.c,v 1.5 2012/01/10 20:29:50 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/extent.h> 40 #include <sys/kmem.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #include <machine/bus.h> 45 #include <machine/cpu.h> 46 47 #include <m68k/bus_dma.h> 48 #include <amiga/dev/zbusvar.h> 49 #include <amiga/dev/p5busvar.h> 50 #include <amiga/pci/p5pbreg.h> 51 #include <amiga/pci/p5pbvar.h> 52 #include <amiga/pci/p5membarvar.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <dev/pci/pcireg.h> 56 #include <dev/pci/pcidevs.h> 57 #include <dev/pci/pciconf.h> 58 59 /* Initial CVPPC/BVPPC resolution as configured by the firmware */ 60 #define P5GFX_WIDTH 640 61 #define P5GFX_HEIGHT 480 62 #define P5GFX_DEPTH 8 63 #define P5GFX_LINEBYTES 640 64 65 static int p5pb_match(struct device *, struct cfdata *, void *); 66 static void p5pb_attach(struct device *, struct device *, void *); 67 void p5pb_set_props(struct p5pb_softc *sc); 68 pcireg_t p5pb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 69 void p5pb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 70 int p5pb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno); 71 int p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, 72 int func, pcireg_t id); 73 void p5pb_pci_attach_hook (struct device *parent, 74 struct device *self, struct pcibus_attach_args *pba); 75 pcitag_t p5pb_pci_make_tag(pci_chipset_tag_t pc, int bus, int device, 76 int function); 77 void p5pb_pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 78 int *bp, int *dp, int *fp); 79 int p5pb_pci_intr_map(const struct pci_attach_args *pa, 80 pci_intr_handle_t *ihp); 81 bool p5pb_bus_map_cvppc(struct p5pb_softc *sc); 82 bool p5pb_bus_map_grex(struct p5pb_softc *sc); 83 bool p5pb_bus_map_common(struct p5pb_softc *sc); 84 uint8_t p5pb_find_resources(struct p5pb_softc *sc); 85 86 CFATTACH_DECL_NEW(p5pb, sizeof(struct p5pb_softc), 87 p5pb_match, p5pb_attach, NULL, NULL); 88 89 static int 90 p5pb_match(device_t parent, cfdata_t cf, void *aux) 91 { 92 struct p5bus_attach_args *p5baa; 93 94 p5baa = (struct p5bus_attach_args *) aux; 95 96 if (strcmp(p5baa->p5baa_name, "p5pb") == 0) 97 return 1; 98 99 return 0; 100 } 101 102 103 static void 104 p5pb_attach(device_t parent, device_t self, void *aux) 105 { 106 struct p5pb_softc *sc; 107 struct pcibus_attach_args pba; 108 109 sc = device_private(self); 110 pci_chipset_tag_t pc = &sc->apc; 111 sc->sc_dev = self; 112 113 if (p5pb_find_resources(sc) > 0) { 114 sc->p5pb_bus_map = &p5pb_bus_map_grex; 115 } else { 116 #ifdef P5PB_OLD_FIRMWARE 117 sc->p5pb_bus_map = &p5pb_bus_map_cvppc; 118 #else 119 aprint_normal(": no PCI bridges detected\n"); 120 return; 121 #endif /* P5PB_OLD_FIRMWARE */ 122 } 123 124 aprint_normal(": Phase5 CVPPC/BVPPC/G-REX PCI bridge\n"); 125 126 if(!p5pb_bus_map_common(sc)) { 127 aprint_error_dev(self, 128 "couldn't map PCI configuration and I/O spaces\n"); 129 return; 130 } 131 132 if(!(sc->p5pb_bus_map(sc))) { 133 aprint_error_dev(self, 134 "couldn't map PCI memory space\n"); 135 return; 136 } 137 138 #ifdef P5PB_DEBUG 139 aprint_normal("p5pb: mapped %x -> %x, %x -> %x\n, %x -> %x\n", 140 P5BUS_PCI_CONF_BASE, sc->pci_conf_area.base, 141 P5BUS_PCI_IO_BASE, sc->pci_io_area.base, 142 P5BUS_PCI_MEM_BASE, sc->pci_mem_area.base ); 143 #endif 144 145 /* Initialize the PCI chipset tag. */ 146 sc->apc.pc_conf_v = (void*) pc; 147 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs; 148 sc->apc.pc_make_tag = amiga_pci_make_tag; 149 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag; 150 sc->apc.pc_conf_read = p5pb_pci_conf_read; 151 sc->apc.pc_conf_write = p5pb_pci_conf_write; 152 sc->apc.pc_attach_hook = p5pb_pci_attach_hook; 153 154 sc->apc.pc_intr_map = p5pb_pci_intr_map; 155 sc->apc.pc_intr_string = amiga_pci_intr_string; 156 sc->apc.pc_intr_establish = amiga_pci_intr_establish; 157 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish; 158 159 pba.pba_iot = &(sc->pci_io_area); 160 pba.pba_memt = &(sc->pci_mem_area); 161 pba.pba_dmat = NULL; 162 pba.pba_dmat64 = NULL; 163 pba.pba_pc = pc; 164 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 165 pba.pba_bus = 0; 166 pba.pba_bridgetag = NULL; 167 168 #ifdef P5PB_GENFB 169 p5pb_set_props(sc); 170 #endif /* P5PB_GENFB */ 171 172 config_found_ia(self, "pcibus", &pba, pcibusprint); 173 } 174 175 /* 176 * Find autoconfigured resuorces (for boards running G-REX firmware). Return the 177 * total number of found resources. 178 */ 179 uint8_t 180 p5pb_find_resources(struct p5pb_softc *sc) 181 { 182 uint8_t i, rv; 183 struct p5pb_autoconf_entry *auto_entry; 184 struct p5membar_softc *membar_sc; 185 device_t p5membar_dev; 186 187 rv = 0; 188 189 TAILQ_INIT(&sc->auto_bars); 190 191 /* 255 should be enough for everybody */ 192 for(i = 0; i < 255; i++) { 193 194 if ((p5membar_dev = 195 device_find_by_driver_unit("p5membar", i)) != NULL) { 196 197 rv++; 198 199 membar_sc = device_private(p5membar_dev); 200 if (membar_sc->sc_type == P5MEMBAR_TYPE_INTERNAL) 201 continue; 202 203 auto_entry = 204 kmem_alloc(sizeof(struct p5pb_autoconf_entry), 205 KM_SLEEP); 206 207 auto_entry->base = membar_sc->sc_base; 208 auto_entry->size = membar_sc->sc_size; 209 210 TAILQ_INSERT_TAIL(&sc->auto_bars, auto_entry, entries); 211 } 212 } 213 return rv; 214 } 215 216 /* 217 * Set properties needed to support fb driver. These are read later during 218 * autoconfg in device_register(). 219 */ 220 void 221 p5pb_set_props(struct p5pb_softc *sc) 222 { 223 prop_dictionary_t dict; 224 device_t dev; 225 226 dev = sc->sc_dev; 227 dict = device_properties(dev); 228 229 prop_dictionary_set_uint32(dict, "width", P5GFX_WIDTH); 230 prop_dictionary_set_uint32(dict, "height", P5GFX_HEIGHT); 231 prop_dictionary_set_uint8(dict, "depth", P5GFX_DEPTH); 232 prop_dictionary_set_uint16(dict, "linebytes", P5GFX_LINEBYTES); 233 prop_dictionary_set_uint64(dict, "address", P5BUS_PCI_MEM_BASE); 234 #if (NGENFB > 0) 235 /* 236 * Framebuffer starts at P5BUS_PCI_MEM_BASE, but genfb needs virtual 237 * address. 238 */ 239 prop_dictionary_set_uint64(dict, "virtual_address", 240 sc->pci_mem_area.base); 241 #endif 242 } 243 244 pcireg_t 245 p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 246 { 247 uint32_t data; 248 uint32_t bus, dev, func; 249 250 pci_decompose_tag(pc, tag, &bus, &dev, &func); 251 252 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah, 253 (func<<5) + reg); 254 #ifdef P5PB_DEBUG 255 aprint_normal("p5pb conf read va: %lx, bus: %d, dev: %d, " 256 "func: %d, reg: %d -r-> data %x\n", 257 pc->pci_conf_datah, bus, dev, func, reg, data); 258 #endif 259 return data; 260 } 261 262 void 263 p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 264 { 265 uint32_t bus, dev, func; 266 267 pci_decompose_tag(pc, tag, &bus, &dev, &func); 268 269 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah, 270 (func << 5) + reg, val); 271 #ifdef P5PB_DEBUG 272 aprint_normal("p5pb conf write va: %lx, bus: %d, dev: %d, " 273 "func: %d, reg: %d -w-> data %x\n", 274 pc->pci_conf_datah, bus, dev, func, reg, val); 275 #endif 276 277 } 278 279 int 280 p5pb_pci_bus_maxdevs(pci_chipset_tag_t pc, int busno) 281 { 282 /* G-REX has max 5 slots. CVPPC/BVPPC has only 1. */ 283 return 1; 284 } 285 286 void 287 p5pb_pci_attach_hook(struct device *parent, struct device *self, 288 struct pcibus_attach_args *pba) 289 { 290 } 291 292 int 293 p5pb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 294 { 295 /* TODO: add sanity checking */ 296 297 *ihp = 2; 298 return 0; 299 } 300 301 /* PCI memory mapping done G-REX-style. */ 302 bool 303 p5pb_bus_map_grex(struct p5pb_softc *sc) 304 { 305 struct p5pb_autoconf_entry *membar_entry; 306 bus_addr_t bar_address; 307 bus_addr_t pci_mem_highest; 308 309 pci_mem_highest = P5BUS_PCI_MEM_BASE; 310 311 #ifdef P5PB_DEBUG 312 aprint_normal("p5pb: p5pb_bus_map_grex called\n"); 313 #endif /* P5PB_DEBUG */ 314 315 /* Determine the highest address used by any PCI card. */ 316 TAILQ_FOREACH(membar_entry, &sc->auto_bars, entries) { 317 318 bar_address = (bus_addr_t) membar_entry->base; 319 if ((bar_address + membar_entry->size) > pci_mem_highest) 320 pci_mem_highest = bar_address + membar_entry->size; 321 322 #ifdef P5PB_DEBUG 323 aprint_normal("p5pb: memory BAR at %p, highest address %x\n", 324 membar_entry->base, pci_mem_highest); 325 #endif /* P5PB_DEBUG */ 326 } 327 328 sc->pci_mem_area.base = (bus_addr_t) zbusmap( 329 (void *) P5BUS_PCI_MEM_BASE, pci_mem_highest - P5BUS_PCI_MEM_BASE); 330 sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs; 331 332 return true; 333 } 334 335 /* Map things common for all supported bridges. */ 336 bool 337 p5pb_bus_map_common(struct p5pb_softc *sc) 338 { 339 #ifdef P5PB_DEBUG 340 aprint_normal("p5pb: p5pb_bus_map_common called\n"); 341 #endif /* P5PB_DEBUG */ 342 343 sc->pci_conf_area.base = (bus_addr_t) zbusmap( 344 (void *) P5BUS_PCI_CONF_BASE, P5BUS_PCI_CONF_SIZE); 345 sc->pci_conf_area.absm = &amiga_bus_stride_1; 346 347 sc->pci_io_area.base = (bus_addr_t) zbusmap( 348 (void *) P5BUS_PCI_IO_BASE, P5BUS_PCI_IO_SIZE); 349 sc->pci_io_area.absm = &amiga_bus_stride_1swap_abs; 350 351 sc->apc.pci_conf_datat = &(sc->pci_conf_area); 352 sc->apc.pci_conf_addresst = &(sc->pci_conf_area); 353 354 if (bus_space_map(sc->apc.pci_conf_datat, OFF_PCI_CONF_DATA, 355 256, 0, &sc->apc.pci_conf_datah)) 356 return false; 357 358 /* XXX */ 359 /* if (bus_space_map(sc->apc.pci_conf_addresst, OFF_PCI_CONF_ADDR, 360 256, 0, &sc->apc.pci_conf_addressh)) 361 return false; */ 362 363 return true; 364 } 365 366 /* Hard-coded memory mapping for CVPPC/BVPPC (without G-REX firmware). */ 367 bool 368 p5pb_bus_map_cvppc(struct p5pb_softc *sc) 369 { 370 #ifdef P5PB_DEBUG 371 aprint_normal("p5pb: p5pb_bus_map_cvppc called\n"); 372 #endif /* P5PB_DEBUG */ 373 sc->pci_mem_area.base = (bus_addr_t) zbusmap( 374 (void *) P5BUS_PCI_MEM_BASE, P5BUS_PCI_MEM_SIZE); 375 sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs; 376 377 return true; 378 } 379 380
Indexes created Tue Sep 30 20:09:53 GMT 2025