p5pb.c revision 1.9
1 /* $NetBSD: p5pb.c,v 1.9 2012/07/11 17:13:31 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2011, 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/types.h> 33 #include <sys/param.h> 34 #include <sys/time.h> 35 #include <sys/systm.h> 36 #include <sys/errno.h> 37 #include <sys/device.h> 38 #include <sys/malloc.h> 39 #include <sys/kmem.h> 40 #include <sys/extent.h> 41 42 #include <uvm/uvm_extern.h> 43 44 #define _M68K_BUS_DMA_PRIVATE 45 #include <machine/bus.h> 46 #include <machine/cpu.h> 47 48 #include <m68k/bus_dma.h> 49 #include <amiga/dev/zbusvar.h> 50 #include <amiga/dev/p5busvar.h> 51 #include <amiga/pci/p5pbreg.h> 52 #include <amiga/pci/p5pbvar.h> 53 #include <amiga/pci/p5membarvar.h> 54 55 #include <dev/pci/pcivar.h> 56 #include <dev/pci/pcireg.h> 57 #include <dev/pci/pcidevs.h> 58 #ifdef PCI_NETBSD_CONFIGURE 59 #include <dev/pci/pciconf.h> 60 #endif /* PCI_NETBSD_CONFIGURE */ 61 62 #include "opt_p5pb.h" 63 #include "opt_pci.h" 64 65 /* Initial CVPPC/BVPPC resolution as configured by the firmware */ 66 #define P5GFX_WIDTH 640 67 #define P5GFX_HEIGHT 480 68 #define P5GFX_DEPTH 8 69 #define P5GFX_LINEBYTES 640 70 71 struct m68k_bus_dma_tag p5pb_bus_dma_tag = { 72 0, 73 0, 74 _bus_dmamap_create, 75 _bus_dmamap_destroy, 76 _bus_dmamap_load_direct, 77 _bus_dmamap_load_mbuf_direct, 78 _bus_dmamap_load_uio_direct, 79 _bus_dmamap_load_raw_direct, 80 _bus_dmamap_unload, 81 _bus_dmamap_sync 82 }; 83 84 static int p5pb_match(struct device *, struct cfdata *, void *); 85 static void p5pb_attach(struct device *, struct device *, void *); 86 void p5pb_set_props(struct p5pb_softc *sc); 87 pcireg_t p5pb_pci_conf_read(pci_chipset_tag_t, pcitag_t, int); 88 void p5pb_pci_conf_write(pci_chipset_tag_t, pcitag_t, int, pcireg_t); 89 int p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t pc, int busno); 90 int p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t pc, int busno); 91 int p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t pc, int busno); 92 int p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, 93 int func, pcireg_t id); 94 void p5pb_pci_attach_hook (struct device *parent, 95 struct device *self, struct pcibus_attach_args *pba); 96 pcitag_t p5pb_pci_make_tag(pci_chipset_tag_t pc, int bus, int device, 97 int function); 98 void p5pb_pci_decompose_tag(pci_chipset_tag_t pc, pcitag_t tag, 99 int *bp, int *dp, int *fp); 100 int p5pb_pci_intr_map(const struct pci_attach_args *pa, 101 pci_intr_handle_t *ihp); 102 bool p5pb_bus_map_memio(struct p5pb_softc *sc); 103 bool p5pb_bus_map_conf(struct p5pb_softc *sc); 104 uint8_t p5pb_find_resources(struct p5pb_softc *sc); 105 static bool p5pb_identify_bridge(struct p5pb_softc *sc); 106 void p5pb_membar_grex(struct p5pb_softc *sc); 107 static bool p5pb_cvppc_probe(struct p5pb_softc *sc); 108 #ifdef PCI_NETBSD_CONFIGURE 109 bool p5pb_bus_reconfigure(struct p5pb_softc *sc); 110 #endif /* PCI_NETBSD_CONFIGURE */ 111 #ifdef P5PB_DEBUG 112 void p5pb_usable_ranges(struct p5pb_softc *sc); 113 void p5pb_badaddr_range(struct p5pb_softc *sc, bus_space_tag_t bust, 114 bus_addr_t base, size_t len); 115 void p5pb_conf_search(struct p5pb_softc *sc, uint16_t val); 116 #endif /* P5PB_DEBUG */ 117 118 CFATTACH_DECL_NEW(p5pb, sizeof(struct p5pb_softc), 119 p5pb_match, p5pb_attach, NULL, NULL); 120 121 static int 122 p5pb_match(device_t parent, cfdata_t cf, void *aux) 123 { 124 struct p5bus_attach_args *p5baa; 125 126 p5baa = (struct p5bus_attach_args *) aux; 127 128 if (strcmp(p5baa->p5baa_name, "p5pb") == 0) 129 return 1; 130 131 return 0; 132 } 133 134 static void 135 p5pb_attach(device_t parent, device_t self, void *aux) 136 { 137 struct p5pb_softc *sc; 138 struct pcibus_attach_args pba; 139 140 sc = device_private(self); 141 sc->sc_dev = self; 142 sc->p5baa = (struct p5bus_attach_args *) aux; 143 144 pci_chipset_tag_t pc = &sc->apc; 145 146 if (!p5pb_bus_map_conf(sc)) { 147 aprint_error_dev(self, 148 "couldn't map PCI configuration space\n"); 149 return; 150 } 151 152 if (!p5pb_identify_bridge(sc)) { 153 return; 154 } 155 156 if (sc->bridge_type == P5PB_BRIDGE_CVPPC) { 157 sc->pci_mem_lowest = P5BUS_PCI_MEM_BASE; 158 sc->pci_mem_highest = P5BUS_PCI_MEM_BASE + P5BUS_PCI_MEM_SIZE; 159 } else { 160 p5pb_membar_grex(sc); 161 } 162 163 if (!p5pb_bus_map_memio(sc)) { 164 aprint_error_dev(self, 165 "couldn't map PCI I/O and memory space\n"); 166 return; 167 } 168 169 #ifdef P5PB_DEBUG 170 aprint_normal("p5pb: map conf %x -> %x, io %x -> %x, mem %x -> %x\n", 171 kvtop((void*) sc->pci_conf_area.base), sc->pci_conf_area.base, 172 kvtop((void*) sc->pci_io_area.base), sc->pci_io_area.base, 173 kvtop((void*) sc->pci_mem_area.base), sc->pci_mem_area.base ); 174 #endif 175 176 /* Initialize the PCI chipset tag. */ 177 178 if (sc->bridge_type == P5PB_BRIDGE_GREX1200) 179 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex1200; 180 else if (sc->bridge_type == P5PB_BRIDGE_GREX4000) 181 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_grex4000; 182 else 183 sc->apc.pc_bus_maxdevs = p5pb_pci_bus_maxdevs_cvppc; 184 185 sc->apc.pc_conf_v = (void*) pc; 186 sc->apc.pc_make_tag = amiga_pci_make_tag; 187 sc->apc.pc_decompose_tag = amiga_pci_decompose_tag; 188 sc->apc.pc_conf_read = p5pb_pci_conf_read; 189 sc->apc.pc_conf_write = p5pb_pci_conf_write; 190 sc->apc.pc_conf_hook = p5pb_pci_conf_hook; 191 sc->apc.pc_conf_interrupt = amiga_pci_conf_interrupt; 192 sc->apc.pc_attach_hook = p5pb_pci_attach_hook; 193 194 sc->apc.pc_intr_map = p5pb_pci_intr_map; 195 sc->apc.pc_intr_string = amiga_pci_intr_string; 196 sc->apc.pc_intr_establish = amiga_pci_intr_establish; 197 sc->apc.pc_intr_disestablish = amiga_pci_intr_disestablish; 198 199 #ifdef PCI_NETBSD_CONFIGURE 200 /* Never reconfigure the bus on CVPPC/BVPPC, avoid the fb breakage. */ 201 if (sc->bridge_type != P5PB_BRIDGE_CVPPC) { 202 p5pb_bus_reconfigure(sc); 203 } 204 #endif /* PCI_NETBSD_CONFIGURE */ 205 206 /* Initialize the bus attachment structure. */ 207 208 pba.pba_iot = &(sc->pci_io_area); 209 pba.pba_memt = &(sc->pci_mem_area); 210 pba.pba_dmat = &p5pb_bus_dma_tag; 211 pba.pba_dmat64 = NULL; 212 pba.pba_pc = pc; 213 pba.pba_flags = PCI_FLAGS_MEM_OKAY | PCI_FLAGS_IO_OKAY; 214 pba.pba_bus = 0; 215 pba.pba_bridgetag = NULL; 216 217 p5pb_set_props(sc); 218 219 config_found_ia(self, "pcibus", &pba, pcibusprint); 220 } 221 222 /* 223 * Try to detect what kind of bridge are we dealing with. 224 */ 225 static bool 226 p5pb_identify_bridge(struct p5pb_softc *sc) 227 { 228 int pcires_count; /* Number of AutoConfig(TM) PCI resources */ 229 230 pcires_count = p5pb_find_resources(sc); 231 232 switch (pcires_count) { 233 case 0: 234 /* 235 * Zero AutoConfig(TM) PCI resources, means that there's nothing 236 * OR there's a CVPPC/BVPPC with a pre-44.69 firmware. 237 */ 238 if (p5pb_cvppc_probe(sc)) { 239 sc->bridge_type = P5PB_BRIDGE_CVPPC; 240 aprint_normal(": Phase5 CVPPC/BVPPC PCI bridge\n"); 241 } else { 242 aprint_normal(": no PCI bridges detected\n"); 243 return false; 244 } 245 break; 246 case 6: 247 /* 248 * We have a slight possibility, that there's a CVPPC/BVPPC with 249 * the new firmware. So check for it first. 250 */ 251 if (p5pb_cvppc_probe(sc)) { 252 /* New firmware, treat as one-slot GREX. */ 253 sc->bridge_type = P5PB_BRIDGE_CVPPC; 254 aprint_normal( 255 ": Phase5 CVPPC/BVPPC PCI bridge (44.69/44.71)\n"); 256 break; 257 } 258 default: 259 /* We have a G-REX surely. */ 260 261 if (sc->p5baa->p5baa_cardtype == P5_CARDTYPE_CS) { 262 sc->bridge_type = P5PB_BRIDGE_GREX4000; 263 aprint_normal(": DCE G-REX 4000 PCI bridge\n"); 264 } else { 265 sc->bridge_type = P5PB_BRIDGE_GREX1200; 266 aprint_normal(": DCE G-REX 1200 PCI bridge\n"); 267 } 268 break; 269 } 270 return true; 271 } 272 273 /* 274 * Find AutoConfig(TM) resuorces (for boards running G-REX firmware). Return the 275 * total number of found resources. 276 */ 277 uint8_t 278 p5pb_find_resources(struct p5pb_softc *sc) 279 { 280 uint8_t i, rv; 281 struct p5pb_autoconf_entry *auto_entry; 282 struct p5membar_softc *membar_sc; 283 device_t p5membar_dev; 284 285 rv = 0; 286 287 TAILQ_INIT(&sc->auto_bars); 288 289 /* 255 should be enough for everybody */ 290 for(i = 0; i < 255; i++) { 291 292 if ((p5membar_dev = 293 device_find_by_driver_unit("p5membar", i)) != NULL) { 294 295 rv++; 296 297 membar_sc = device_private(p5membar_dev); 298 if (membar_sc->sc_type == P5MEMBAR_TYPE_INTERNAL) 299 continue; 300 301 auto_entry = 302 kmem_alloc(sizeof(struct p5pb_autoconf_entry), 303 KM_SLEEP); 304 305 auto_entry->base = membar_sc->sc_base; 306 auto_entry->size = membar_sc->sc_size; 307 308 TAILQ_INSERT_TAIL(&sc->auto_bars, auto_entry, entries); 309 } 310 } 311 return rv; 312 } 313 314 /* 315 * Set properties needed to support fb driver. These are read later during 316 * autoconfg in device_register(). Needed for CVPPC/BVPPC and Voodoo in G-REX. 317 */ 318 void 319 p5pb_set_props(struct p5pb_softc *sc) 320 { 321 prop_dictionary_t dict; 322 device_t dev; 323 324 dev = sc->sc_dev; 325 dict = device_properties(dev); 326 327 prop_dictionary_set_uint32(dict, "width", P5GFX_WIDTH); 328 prop_dictionary_set_uint32(dict, "height", P5GFX_HEIGHT); 329 prop_dictionary_set_uint8(dict, "depth", P5GFX_DEPTH); 330 331 /* genfb needs additional properties, like virtual, physical address */ 332 #if (NGENFB > 0) 333 /* XXX: currently genfb is supported only on CVPPC/BVPPC */ 334 prop_dictionary_set_uint16(dict, "linebytes", P5GFX_LINEBYTES); 335 prop_dictionary_set_uint64(dict, "virtual_address", 336 sc->pci_mem_area.base); 337 prop_dictionary_set_uint64(dict, "address", 338 kvtop((void*) sc->pci_mem_area.base)); 339 #endif 340 341 #ifdef P5PB_CONSOLE 342 prop_dictionary_set_bool(dict, "is_console", true); 343 #else 344 prop_dictionary_set_bool(dict, "is_console", false); 345 #endif 346 347 } 348 349 pcireg_t 350 p5pb_pci_conf_read(pci_chipset_tag_t pc, pcitag_t tag, int reg) 351 { 352 uint32_t data; 353 uint32_t bus, dev, func; 354 uint32_t offset; 355 356 pci_decompose_tag(pc, tag, &bus, &dev, &func); 357 358 offset = (OFF_PCI_DEVICE << dev) + reg; 359 360 if(func == 0) /* ugly, ugly hack */ 361 offset += 0; 362 else if(func == 1) 363 offset += OFF_PCI_FUNCTION; 364 else 365 return 0xFFFFFFFF; 366 367 if(badaddr((void *)__UNVOLATILE(((uint32_t) 368 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 369 + offset)))) 370 return 0xFFFFFFFF; 371 372 data = bus_space_read_4(pc->pci_conf_datat, pc->pci_conf_datah, 373 offset); 374 #ifdef P5PB_DEBUG_CONF 375 aprint_normal("p5pb conf read va: %lx, bus: %d, dev: %d, " 376 "func: %d, reg: %d -r-> data %x\n", 377 pc->pci_conf_datah, bus, dev, func, reg, data); 378 #endif 379 return data; 380 } 381 382 void 383 p5pb_pci_conf_write(pci_chipset_tag_t pc, pcitag_t tag, int reg, pcireg_t val) 384 { 385 uint32_t bus, dev, func; 386 uint32_t offset; 387 388 pci_decompose_tag(pc, tag, &bus, &dev, &func); 389 390 offset = (OFF_PCI_DEVICE << dev) + reg; 391 392 if(func == 0) /* ugly, ugly hack */ 393 offset += 0; 394 else if(func == 1) 395 offset += OFF_PCI_FUNCTION; 396 else 397 return; 398 399 if(badaddr((void *)__UNVOLATILE(((uint32_t) 400 bus_space_vaddr(pc->pci_conf_datat, pc->pci_conf_datah) 401 + offset)))) 402 return; 403 404 bus_space_write_4(pc->pci_conf_datat, pc->pci_conf_datah, 405 offset, val); 406 #ifdef P5PB_DEBUG_CONF 407 aprint_normal("p5pb conf write va: %lx, bus: %d, dev: %d, " 408 "func: %d, reg: %d -w-> data %x\n", 409 pc->pci_conf_datah, bus, dev, func, reg, val); 410 #endif 411 412 } 413 414 int 415 p5pb_pci_bus_maxdevs_cvppc(pci_chipset_tag_t pc, int busno) 416 { 417 /* CVPPC/BVPPC has only 1 "slot". */ 418 return 1; 419 } 420 421 int 422 p5pb_pci_bus_maxdevs_grex4000(pci_chipset_tag_t pc, int busno) 423 { 424 /* G-REX 4000 has 4, G-REX 4000T has 3 slots? */ 425 return 4; 426 } 427 428 int 429 p5pb_pci_bus_maxdevs_grex1200(pci_chipset_tag_t pc, int busno) 430 { 431 /* G-REX 1200 has 5 slots. */ 432 return 4; /* XXX: 5 not yet! */ 433 } 434 435 void 436 p5pb_pci_attach_hook(struct device *parent, struct device *self, 437 struct pcibus_attach_args *pba) 438 { 439 } 440 441 int 442 p5pb_pci_intr_map(const struct pci_attach_args *pa, pci_intr_handle_t *ihp) 443 { 444 /* TODO: add sanity checking */ 445 446 *ihp = 2; 447 return 0; 448 } 449 450 /* Probe for CVPPC/BVPPC. */ 451 static bool 452 p5pb_cvppc_probe(struct p5pb_softc *sc) 453 { 454 bus_space_handle_t probe_h; 455 uint16_t prodid, manid; 456 void* data; 457 bool rv; 458 459 manid = 0; prodid = 0; 460 rv = false; 461 462 if (bus_space_map(sc->apc.pci_conf_datat, 0, 4, 0, &probe_h)) 463 return rv; 464 465 data = bus_space_vaddr(sc->apc.pci_conf_datat, probe_h); 466 467 if (badaddr((void *)__UNVOLATILE((uint32_t) data))) { 468 #ifdef P5PB_DEBUG_PROBE 469 aprint_normal("p5pb: CVPPC configuration space not usable!\n"); 470 #endif /* P5PB_DEBUG_PROBE */ 471 } else { 472 prodid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 0); 473 manid = bus_space_read_2(sc->apc.pci_conf_datat, probe_h, 2); 474 475 if ((prodid == P5PB_PM2_PRODUCT_ID) && 476 (manid == P5PB_PM2_VENDOR_ID)) 477 rv = true; 478 } 479 480 #ifdef P5PB_DEBUG_PROBE 481 aprint_normal("p5pb: CVPPC probe for PCI ID: %x, %x returns %d\n", 482 manid, prodid, (int) rv); 483 #endif /* P5PB_DEBUG_PROBE */ 484 485 bus_space_unmap(sc->apc.pci_conf_datat, probe_h, 4); 486 return rv; 487 } 488 489 #ifdef PCI_NETBSD_CONFIGURE 490 /* Reconfigure the bus. */ 491 bool 492 p5pb_bus_reconfigure(struct p5pb_softc *sc) 493 { 494 struct extent *ioext, *memext; 495 pci_chipset_tag_t pc; 496 497 pc = &sc->apc; 498 499 ioext = extent_create("p5pbio", 0, P5BUS_PCI_IO_SIZE, NULL, 0, 500 EX_NOWAIT); 501 502 memext = extent_create("p5pbmem", sc->pci_mem_lowest, 503 sc->pci_mem_highest - 1, NULL, 0, EX_NOWAIT); 504 505 if ( (!ioext) || (!memext) ) 506 return false; 507 508 #ifdef P5PB_DEBUG 509 aprint_normal("p5pb: reconfiguring the bus!\n"); 510 #endif /* P5PB_DEBUG */ 511 pci_configure_bus(pc, ioext, memext, NULL, 0, CACHELINE_SIZE); 512 513 extent_destroy(ioext); 514 extent_destroy(memext); 515 516 return true; /* TODO: better error handling */ 517 } 518 #endif /* PCI_NETBSD_CONFIGURE */ 519 520 /* Determine the PCI memory space (done G-REX-style). */ 521 void 522 p5pb_membar_grex(struct p5pb_softc *sc) 523 { 524 struct p5pb_autoconf_entry *membar_entry; 525 uint32_t bar_address; 526 527 sc->pci_mem_lowest = 0xFFFFFFFF; 528 sc->pci_mem_highest = 0; 529 530 /* Iterate over membar entries to find lowest and highest address. */ 531 TAILQ_FOREACH(membar_entry, &sc->auto_bars, entries) { 532 533 bar_address = (uint32_t) membar_entry->base; 534 if ((bar_address + membar_entry->size) > sc->pci_mem_highest) 535 sc->pci_mem_highest = bar_address + membar_entry->size; 536 if (bar_address < sc->pci_mem_lowest) 537 sc->pci_mem_lowest = bar_address; 538 539 #ifdef P5PB_DEBUG_BAR 540 aprint_normal("p5pb: %d kB mem BAR at %p, hi = %x, lo = %x\n", 541 membar_entry->size / 1024, membar_entry->base, 542 sc->pci_mem_highest, sc->pci_mem_lowest); 543 #endif /* P5PB_DEBUG_BAR */ 544 } 545 546 aprint_normal("p5pb: %d kB PCI memory space (%8p to %8p)\n", 547 (sc->pci_mem_highest - sc->pci_mem_lowest) / 1024, 548 (void*) sc->pci_mem_lowest, (void*) sc->pci_mem_highest); 549 550 } 551 552 bool 553 p5pb_bus_map_conf(struct p5pb_softc *sc) 554 { 555 sc->pci_conf_area.base = (bus_addr_t) zbusmap( 556 (void *) P5BUS_PCI_CONF_BASE, P5BUS_PCI_CONF_SIZE); 557 sc->pci_conf_area.absm = &amiga_bus_stride_1; 558 559 sc->apc.pci_conf_datat = &(sc->pci_conf_area); 560 561 if (bus_space_map(sc->apc.pci_conf_datat, OFF_PCI_CONF_DATA, 562 P5BUS_PCI_CONF_SIZE, 0, &sc->apc.pci_conf_datah)) 563 return false; 564 565 return true; 566 } 567 568 /* Map I/O and memory space. */ 569 bool 570 p5pb_bus_map_memio(struct p5pb_softc *sc) 571 { 572 sc->pci_io_area.base = (bus_addr_t) zbusmap( 573 (void *) P5BUS_PCI_IO_BASE, P5BUS_PCI_IO_SIZE); 574 sc->pci_io_area.absm = &amiga_bus_stride_1swap; 575 576 sc->pci_mem_area.base = (bus_addr_t) zbusmap( 577 (void *) sc->pci_mem_lowest, 578 sc->pci_mem_highest - sc->pci_mem_lowest); 579 sc->pci_mem_area.absm = &amiga_bus_stride_1swap_abs; 580 581 return true; 582 } 583 584 int 585 p5pb_pci_conf_hook(pci_chipset_tag_t pct, int bus, int dev, 586 int func, pcireg_t id) 587 { 588 /* XXX: What should we do on CVPPC/BVPPC? It breaks genfb. */ 589 590 return PCI_CONF_DEFAULT; 591 } 592 593 #ifdef P5PB_DEBUG 594 /* Check which config and I/O ranges are usable. */ 595 void 596 p5pb_usable_ranges(struct p5pb_softc *sc) 597 { 598 p5pb_badaddr_range(sc, &(sc->pci_conf_area), 0, P5BUS_PCI_CONF_SIZE); 599 p5pb_badaddr_range(sc, &(sc->pci_io_area), 0, P5BUS_PCI_IO_SIZE); 600 } 601 602 void 603 p5pb_badaddr_range(struct p5pb_softc *sc, bus_space_tag_t bust, bus_addr_t base, 604 size_t len) 605 { 606 int i, state, prev_state; 607 bus_space_handle_t bush; 608 volatile void *data; 609 610 state = -1; 611 prev_state = -1; 612 613 bus_space_map(bust, base, len, 0, &bush); 614 615 aprint_normal("p5pb: badaddr range check from %x (%x) to %x (%x)\n", 616 (bus_addr_t) bush, /* start VA */ 617 (bus_addr_t) kvtop((void*) bush), /* start PA */ 618 (bus_addr_t) bush + len, /* end VA */ 619 (bus_addr_t) kvtop((void*) (bush + len)));/* end PA */ 620 621 data = bus_space_vaddr(bust, bush); 622 623 for(i = 0; i < len; i++) { 624 state = badaddr((void *)__UNVOLATILE(((uint32_t) data + i))); 625 if(state != prev_state) { 626 aprint_normal("p5pb: badaddr %p (%x) : %d\n", 627 (void*) ((uint32_t) data + i), 628 (bus_addr_t) kvtop((void*) ((uint32_t) data + i)), 629 state); 630 prev_state = state; 631 } 632 633 } 634 635 bus_space_unmap(bust, bush, len); 636 } 637 638 /* Search for 16-bit value in the configuration space. */ 639 void 640 p5pb_conf_search(struct p5pb_softc *sc, uint16_t val) 641 { 642 int i, state; 643 uint16_t readv; 644 void *va; 645 646 va = bus_space_vaddr(sc->apc.pci_conf_datat, sc->apc.pci_conf_datah); 647 648 for (i = 0; i < P5BUS_PCI_CONF_SIZE; i++) { 649 state = badaddr((void *)__UNVOLATILE(((uint32_t) va + i))); 650 if(state == 0) { 651 readv = bus_space_read_2(sc->apc.pci_conf_datat, 652 sc->apc.pci_conf_datah, i); 653 if(readv == val) 654 aprint_normal("p5pb: found val %x @ %x (%x)\n", 655 readv, (uint32_t) sc->apc.pci_conf_datah 656 + i, (bus_addr_t) kvtop((void*) 657 ((uint32_t) sc->apc.pci_conf_datah + i))); 658 } 659 } 660 } 661 662 #endif /* P5PB_DEBUG */ 663 664
Indexes created Tue Sep 30 20:09:53 GMT 2025