p5pbreg.h revision 1.5
1 /* $NetBSD: p5pbreg.h,v 1.5 2012/01/11 17:04:29 rkujawa Exp $ */ 2 3 /*- 4 * Copyright (c) 2011 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Reverse engineered Phase5 PCI bridge memory map (firmware 44.71): 34 * 35 * 0xFFFA0000 - PCI register space, 64KB 36 * 0xFFFC0000 - PCI configuration mechanism #1 data, 128KB 37 * 0xFFFE0000 - (unknown, maybe PCI configuration mechanism #1 address, 4KB) 38 * 39 * 0xE0000000 - Permedia RAM on CVPPC/BVPPC (1st aperture), 8MB 40 * 0xE0800000 - Permedia RAM on CVPPC/BVPPC (2nd aperture), 8MB 41 * 0xE1000000 - Permedia registers, 128KB 42 * 43 * Note: this map may not look the same for every firmware revision. 44 * 45 * The bridge is probably capable of DMA and interrupts, but this would 46 * need further reverse engineering, and is not really needed to drive 47 * the Permedia 2 chip on CVPPC/BVPPC cards. 48 */ 49 #ifndef _AMIGA_P5PBREG_H_ 50 51 #define P5BUS_PCI_CONF_BASE 0xFFFC0000 52 #define P5BUS_PCI_CONF_SIZE 0x00020000 /* up to 128kB */ 53 54 /* XXX: This is OK for CVPPC/BVPPC only! */ 55 #define P5BUS_PCI_MEM_BASE 0xE0000000 56 #define P5BUS_PCI_MEM_SIZE 0x01010000 /* actually 0x01020000 */ 57 58 #define P5BUS_PCI_IO_BASE 0xFFFA0000 59 #define P5BUS_PCI_IO_SIZE 0x0000FFFF /* 64kB */ 60 61 #define P5BUS_PCI_BRIDGE_BASE 0xFFFE0000 62 #define P5BUS_PCI_BRIDGE_SIZE 0x0000FFFF /* 64kB, 4kB on some fw revs */ 63 64 #define OFF_PCI_CONF_DATA 0x00000000 65 66 #define P5BUS_CONF_ENDIAN 0x0000 /* PCI_BRIDGE_BASE + offset */ 67 #define P5BUS_CONF_ENDIAN_BIG 0x02 /* to switch into BE mode */ 68 #define P5BUS_CONF_INTR 0x0010 /* ? XXX interrupt enable? */ 69 #define P5BUS_CONF_INTR_INT2 0x01 /* ? XXX INT2? */ 70 71 /* typical configuration of Permedia 2 on CVPPC/BVPPC */ 72 #define OFF_P2_APERTURE_1 0x0 73 #define OFF_P2_APERTURE_2 0x00800000 74 #define OFF_P2_REGS 0x01000000 75 /* #define OFF_P2_REGS 0x0F000000 */ /* ? alt. Permedia regs */ 76 77 /* PCI configuration register on CV64/3D, base is an offset from card base */ 78 #define CV643D_PCI_CONF_BASE 0xC0E0000 79 #define CV643D_PCI_CONF_SIZE 0xFFF 80 #define CV643D_PCI_MEM_BASE 0x4000000 81 #define CV643D_PCI_MEM_SIZ 0x4000FFF 82 #define CV643D_PCI_IO_BASE 0xC000000 83 #define CV643D_PCI_IO_SIZE 0xFFFF 84 85 #endif /* _AMIGA_P5PBREG_H_ */ 86
Indexes created Tue Sep 30 20:09:53 GMT 2025