intr.h revision 1.3
1/* $NetBSD: intr.h,v 1.3 2000/08/22 19:46:31 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ignatios Souvatzis. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * machine/intr.h for the Amiga port. 41 * Currently, only a wrapper, for most of the stuff, around the old 42 * include files. 43 */ 44 45#ifndef _MACHINE_INTR_H_ 46#define _MACHINE_INTR_H_ 47 48#include <amiga/amiga/isr.h> 49#include <amiga/include/mtpr.h> 50 51#define __GENERIC_SOFT_INTERRUPTS 52/* ADAM: commented out 53#define IPL_SOFTSERIAL 1 54#define IPL_SOFTNET 1 55*/ 56 57#ifdef splaudio 58#undef splaudio 59#define splaudio spl6 60#endif 61 62#define spllpt() spl6() 63 64/* ADAM: from macppc/intr.h */ 65/* Interrupt priority `levels'. */ 66#define IPL_NONE 9 /* nothing */ 67#define IPL_SOFTCLOCK 8 /* timeouts */ 68#define IPL_SOFTNET 7 /* protocol stacks */ 69#define IPL_BIO 6 /* block I/O */ 70#define IPL_NET 5 /* network */ 71#define IPL_SOFTSERIAL 4 /* serial */ 72#define IPL_TTY 3 /* terminal */ 73#define IPL_IMP 3 /* memory allocation */ 74#define IPL_AUDIO 2 /* audio */ 75#define IPL_CLOCK 1 /* clock */ 76#define IPL_HIGH 1 /* everything */ 77#define IPL_SERIAL 0 /* serial */ 78#define NIPL 10 79 80/* Interrupt sharing types. */ 81#define IST_NONE 0 /* none */ 82#define IST_PULSE 1 /* pulsed */ 83#define IST_EDGE 2 /* edge-triggered */ 84#define IST_LEVEL 3 /* level-triggered */ 85 86#ifndef _LOCORE 87 88/* 89 * Interrupt handler chains. intr_establish() inserts a handler into 90 * the list. The handler is called with its (single) argument. 91 */ 92struct intrhand { 93 int (*ih_fun) __P((void *)); 94 void *ih_arg; 95 u_long ih_count; 96 struct intrhand *ih_next; 97 int ih_level; 98 int ih_irq; 99}; 100 101/* 102void setsoftclock __P((void)); 103*/ 104void clearsoftclock __P((void)); 105int splsoftclock __P((void)); 106/* 107void setsoftnet __P((void)); 108*/ 109void clearsoftnet __P((void)); 110int splsoftnet __P((void)); 111 112void do_pending_int __P((void)); 113 114static __inline int splraise __P((int)); 115static __inline int spllower __P((int)); 116static __inline void splx __P((int)); 117static __inline void softintr __P((int)); 118 119/* 120extern volatile int cpl, ipending, astpending, tickspending; 121*/ 122extern int imask[]; 123 124/* 125 * Reorder protection in the following inline functions is 126 * achived with the "eieio" instruction which the assembler 127 * seems to detect and then doen't move instructions past.... 128 */ 129static __inline int 130splraise(ncpl) 131 int ncpl; 132{ 133 int ocpl; 134 135 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 136/* 137 ocpl = cpl; 138 cpl = ocpl | ncpl; 139*/ 140 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 141 return (ocpl); 142} 143 144static __inline void 145splx(ncpl) 146 int ncpl; 147{ 148 149 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 150/* 151 cpl = ncpl; 152 if (ipending & ~ncpl) 153 do_pending_int(); 154*/ 155 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 156} 157 158static __inline int 159spllower(ncpl) 160 int ncpl; 161{ 162 int ocpl; 163 164 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 165/* 166 ocpl = cpl; 167 cpl = ncpl; 168 if (ipending & ~ncpl) 169 do_pending_int(); 170*/ 171 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 172 return (ocpl); 173} 174 175/* Following code should be implemented with lwarx/stwcx to avoid 176 * the disable/enable. i need to read the manual once more.... */ 177static __inline void 178softintr(ipl) 179 int ipl; 180{ 181 int msrsave; 182 183 __asm__ volatile("mfmsr %0" : "=r"(msrsave)); 184 __asm__ volatile("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 185// ipending |= 1 << ipl; 186 __asm__ volatile("mtmsr %0" :: "r"(msrsave)); 187} 188 189#define ICU_LEN 32 190 191/* Soft interrupt masks. */ 192/* 193#define SIR_CLOCK 28 194#define SIR_NET 29 195#define SIR_SERIAL 30 196*/ 197#define SPL_CLOCK 31 198 199/* 200 * Hardware interrupt masks 201 */ 202#define splbio() splraise(imask[IPL_BIO]) 203#define splnet() splraise(imask[IPL_NET]) 204#define spltty() splraise(imask[IPL_TTY]) 205#define splaudio() splraise(imask[IPL_AUDIO]) 206#define splclock() splraise(imask[IPL_CLOCK]) 207#define splstatclock() splclock() 208#define splserial() splraise(imask[IPL_SERIAL]) 209 210/* ADAM: see above 211#define spllpt() spltty() 212*/ 213 214/* 215 * Software interrupt masks 216 * 217 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 218 * clock to softclock before it calls softclock(). 219 */ 220#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 221#define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 222#define splsoftnet() splraise(imask[IPL_SOFTNET]) 223#define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 224 225/* 226 * Miscellaneous 227 */ 228#define splimp() splraise(imask[IPL_IMP]) 229#define splhigh() splraise(imask[IPL_HIGH]) 230#define splsched() splhigh() 231#define spllock() splhigh() 232#define spl0() spllower(0) 233 234/* 235#define setsoftclock() softintr(SIR_CLOCK) 236#define setsoftnet() softintr(SIR_NET) 237#define setsoftserial() softintr(SIR_SERIAL) 238*/ 239extern long intrcnt[]; 240 241#define CNT_IRQ0 0 242#define CNT_CLOCK 64 243#define CNT_SOFTCLOCK 65 244#define CNT_SOFTNET 66 245#define CNT_SOFTSERIAL 67 246 247#endif /* !_LOCORE */ 248 249#endif /* !_MACPPC_INTR_H_ */ 250