intr.h revision 1.5
1/* $NetBSD: intr.h,v 1.5 2001/01/14 23:50:29 thorpej Exp $ */ 2 3/*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Ignatios Souvatzis. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the NetBSD 21 * Foundation, Inc. and its contributors. 22 * 4. Neither the name of The NetBSD Foundation nor the names of its 23 * contributors may be used to endorse or promote products derived 24 * from this software without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 28 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 29 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 30 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 31 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 32 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 33 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 34 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 36 * POSSIBILITY OF SUCH DAMAGE. 37 */ 38 39/* 40 * machine/intr.h for the Amiga port. 41 * Currently, only a wrapper, for most of the stuff, around the old 42 * include files. 43 */ 44 45#ifndef _MACHINE_INTR_H_ 46#define _MACHINE_INTR_H_ 47 48#include <amiga/amiga/isr.h> 49#include <amiga/include/mtpr.h> 50 51/* ADAM: commented out 52#define IPL_SOFTSERIAL 1 53#define IPL_SOFTNET 1 54*/ 55 56#ifdef splaudio 57#undef splaudio 58#define splaudio spl6 59#endif 60 61#define spllpt() spl6() 62 63/* ADAM: from macppc/intr.h */ 64/* Interrupt priority `levels'. */ 65#define IPL_NONE 9 /* nothing */ 66#define IPL_SOFTCLOCK 8 /* timeouts */ 67#define IPL_SOFTNET 7 /* protocol stacks */ 68#define IPL_BIO 6 /* block I/O */ 69#define IPL_NET 5 /* network */ 70#define IPL_SOFTSERIAL 4 /* serial */ 71#define IPL_TTY 3 /* terminal */ 72#define IPL_IMP 3 /* memory allocation */ 73#define IPL_AUDIO 2 /* audio */ 74#define IPL_CLOCK 1 /* clock */ 75#define IPL_HIGH 1 /* everything */ 76#define IPL_SERIAL 0 /* serial */ 77#define NIPL 10 78 79/* Interrupt sharing types. */ 80#define IST_NONE 0 /* none */ 81#define IST_PULSE 1 /* pulsed */ 82#define IST_EDGE 2 /* edge-triggered */ 83#define IST_LEVEL 3 /* level-triggered */ 84 85#ifndef _LOCORE 86 87/* 88 * Interrupt handler chains. intr_establish() inserts a handler into 89 * the list. The handler is called with its (single) argument. 90 */ 91struct intrhand { 92 int (*ih_fun) __P((void *)); 93 void *ih_arg; 94 u_long ih_count; 95 struct intrhand *ih_next; 96 int ih_level; 97 int ih_irq; 98}; 99 100/* 101void setsoftclock __P((void)); 102*/ 103void clearsoftclock __P((void)); 104int splsoftclock __P((void)); 105/* 106void setsoftnet __P((void)); 107*/ 108void clearsoftnet __P((void)); 109int splsoftnet __P((void)); 110 111void do_pending_int __P((void)); 112 113static __inline int splraise __P((int)); 114static __inline int spllower __P((int)); 115static __inline void splx __P((int)); 116static __inline void softintr __P((int)); 117 118/* 119extern volatile int cpl, ipending, astpending, tickspending; 120*/ 121extern int imask[]; 122 123/* 124 * Reorder protection in the following inline functions is 125 * achived with the "eieio" instruction which the assembler 126 * seems to detect and then doen't move instructions past.... 127 */ 128static __inline int 129splraise(ncpl) 130 int ncpl; 131{ 132 int ocpl; 133 134 __asm__ volatile("sync; eieio\n"); /* don't reorder.... */ 135/* 136 ocpl = cpl; 137 cpl = ocpl | ncpl; 138*/ 139 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 140 return (ocpl); 141} 142 143static __inline void 144splx(ncpl) 145 int ncpl; 146{ 147 148 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 149/* 150 cpl = ncpl; 151 if (ipending & ~ncpl) 152 do_pending_int(); 153*/ 154 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 155} 156 157static __inline int 158spllower(ncpl) 159 int ncpl; 160{ 161 int ocpl; 162 163 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 164/* 165 ocpl = cpl; 166 cpl = ncpl; 167 if (ipending & ~ncpl) 168 do_pending_int(); 169*/ 170 __asm__ volatile("sync; eieio\n"); /* reorder protect */ 171 return (ocpl); 172} 173 174/* Following code should be implemented with lwarx/stwcx to avoid 175 * the disable/enable. i need to read the manual once more.... */ 176static __inline void 177softintr(ipl) 178 int ipl; 179{ 180 int msrsave; 181 182 __asm__ volatile("mfmsr %0" : "=r"(msrsave)); 183 __asm__ volatile("mtmsr %0" :: "r"(msrsave & ~PSL_EE)); 184// ipending |= 1 << ipl; 185 __asm__ volatile("mtmsr %0" :: "r"(msrsave)); 186} 187 188#define ICU_LEN 32 189 190/* Soft interrupt masks. */ 191/* 192#define SIR_CLOCK 28 193#define SIR_NET 29 194#define SIR_SERIAL 30 195*/ 196#define SPL_CLOCK 31 197 198/* 199 * Hardware interrupt masks 200 */ 201#define splbio() splraise(imask[IPL_BIO]) 202#define splnet() splraise(imask[IPL_NET]) 203#define spltty() splraise(imask[IPL_TTY]) 204#define splaudio() splraise(imask[IPL_AUDIO]) 205#define splclock() splraise(imask[IPL_CLOCK]) 206#define splstatclock() splclock() 207#define splserial() splraise(imask[IPL_SERIAL]) 208 209/* ADAM: see above 210#define spllpt() spltty() 211*/ 212 213/* 214 * Software interrupt masks 215 * 216 * NOTE: splsoftclock() is used by hardclock() to lower the priority from 217 * clock to softclock before it calls softclock(). 218 */ 219#define spllowersoftclock() spllower(imask[IPL_SOFTCLOCK]) 220#define splsoftclock() splraise(imask[IPL_SOFTCLOCK]) 221#define splsoftnet() splraise(imask[IPL_SOFTNET]) 222#define splsoftserial() splraise(imask[IPL_SOFTSERIAL]) 223 224/* 225 * Miscellaneous 226 */ 227#define splimp() splraise(imask[IPL_IMP]) 228#define splvm() splraise(imask[IPL_IMP]) 229#define splhigh() splraise(imask[IPL_HIGH]) 230#define splsched() splhigh() 231#define spllock() splhigh() 232#define spl0() spllower(0) 233 234/* 235#define setsoftclock() softintr(SIR_CLOCK) 236#define setsoftnet() softintr(SIR_NET) 237#define setsoftserial() softintr(SIR_SERIAL) 238*/ 239extern long intrcnt[]; 240 241#define CNT_IRQ0 0 242#define CNT_CLOCK 64 243#define CNT_SOFTCLOCK 65 244#define CNT_SOFTNET 66 245#define CNT_SOFTSERIAL 67 246 247#endif /* !_LOCORE */ 248 249#endif /* !_MACPPC_INTR_H_ */ 250