TODO revision 1.20
1$NetBSD: TODO,v 1.20 2005/04/19 12:12:28 tsutsui Exp $ 2 3To do list (in some particular order) 4XXX some entries might be obsolete. 5 6 o sysinst 7 maybe MD fdisk partitioning support is required to load files 8 from FAT partition on ARC BIOS prompt. 9 10 o install notes 11 12 13 o use MI driver 14 15 - make fd driver MI, and share it with other ports 16 (contact christos about MI fd driver) 17 18 - use MI bha driver instead of home grown btl 19 XXX needs fixes of DESKstation support 20 21 o VXL framebuffer support (Magnum, RISCstation 2200) 22 23 o com_jazzio.c 24 - clock handling clean up (obtain from ARC BIOS) 25 - fifo disabling may be only needed on some Magnum? 26 27 o remove pccons and switch to wscons completely 28 (XXX what's the problem to remove pccons?) 29 30 o AD1848 audio support 31 32 o missing MI devices 33 ses?, vcoda, ... 34 35 36 o Xserver 37 38 - VXL Magnum, RISCstation 2200 39 - vga/S3 PICA, Image RISCstation - OpenBSD's? 40 - vga/cirrus RISCserver 2200, Express5800/240 R4400 EISA 41 - vga/??? DESKstation Tyne, rPC44 42 - TGA RISCstation 2250, Express5800/230 R4400 PCI 43 44 o Find out why bitmap load to S3-928 flashes screen. (X server) 45 Know why (enable linear mode). Need S3 info. 46 47 48 o repair DESKstation support 49 - requires bounce buffer bus_dma for Tyne 50 XXX - too small bounce buffer size (128KB) 51 52 o Olivetti M700 support 53 54 o NEC Express5800/230 R10000 PCI (NEC-J95) support 55 (needs MI R10000 support) 56 57 o SNI RM200PCI/RM300/RM400/RM600 support 58 59 60 o parse ARC BIOS configuration information and use it 61 62 o increase MAXPHYS to 64KB 63 (XXX why is it limited to 32KB?) 64 65 o fix kernel start address 66 (maybe requires bootloader support) 67 68 o allocate PICA_TL_BASE dynamically 69 70 o remove inb/outb 71 72 o remove UADDR 73 74 o fix mem_clusters[] usage. 75 76 o intrcnt[] name cleanup, use MI evcnt(9) 77 78 o test and merge soren's clean up about proc0.p_addr. 79 80 o redesign interrupt handler framework. 81 i/o bus devices should have sane IPL, but currently doesn't. 82 83 also, current MIPS interrupt handler has overblocking and 84 other problems as follows: 85 86 - SR_INT_IE should be enabled before calling hardclock(). 87 Since this is not done currently, spllowersoftclock() 88 on hardclock() doesn't have effect, and softclock() is 89 handled with all interrupt disabled in this case. 90 -> overblocking, possibly causes missing hardclock() 91 92 - MIPS3_CLKF_BASEPRI() doesn't work correctly, 93 when MIPS_INT_MASK_5 (== MIPS_INT_MASK_CLOCK) is disabled. 94 -> micro optimization on hardclock() doesn't work. 95 but currently this may make hardclock() latency better 96 due to above SR_INT_IE problem. 97 s/MIPS_INT_MASK/MIPS3_INT_MASK/ makes this work, although tricky. 98 99 - if (ipending & INT_MASK_REAL_DEV) == 0, 100 softnet() and softclock() are handled with all interrupt disabled. 101 -> overblocking, possibly causes missing hardclock() 102 103 - `netisr' handling in netintr() implies potential race condition. 104 The access to `netisr' should be protected by splnet(). 105 Currently this is not real problem due to above overblocking. 106 107 - INT_MASK_REAL_DEV should be removed 108 109 - make CLKF_INTR() work. 110 111 o it is better to always disable MIPS_INT_MASK_CLOCK. 112 those are the points which should be fixed: 113 mips_idle: li t0, (MIPS_INT_MASK | MIPS_SR_INT_IE) 114 machdep.c: curpcb->pcb_context[11] = MIPS_INT_MASK | MIPS_SR_INT_IE; 115 spl0() 116 splnone() 117 118 - MIPS_INT_MASK_CLOCK should be removed in someway 119 120 o XXX at least 2000/06/07 version is already quite unstable 121 on PICA and NEC Image RISCstation. (but almost OK on Magnum) 122 Userland commands dumps core randomly. 123 This version is before _MIPS_PADDR_T_64BIT changes 124 and MIPS3_TLB_WIRED_UPAGES changes. 125 126 "vm_page_zero_enable = FALSE" makes this problem disappeared. 127 (vm_page_zero_enable = FALSE by default on all archs w/ UBC, now) 128 129 currently, page zero in the idle loop is also disabled on 130 untested platforms like DESKstation rPC44/Tyne and SNI for safety. 131 132 XXX what's the current status of uvm_pageidlezero()? 133 134 135 o resolve "XXX" 136 137 138(following entries might be MI MIPS items) 139 140 o Move the RO and WIRED attribute from the pte to the pv table. 141 This saves four instructions in the tlb miss handler. 142 143 o Can we have 32 double registers? 144 145 o 64bit kernel/userland 146 147 o fix implementation of DELAY(), clean up clock implementation 148 149 o omit __SWAP_BROKEN in <mips/types.h> 150 151 o clean up ALEAF/NLEAF/NON_LEAF/NNON_LEAF in userland. 152 153Lots of other things..... 154