cpu.h revision 1.1.1.2
1 /* $OpenBSD: cpu.h,v 1.8 1997/04/19 17:19:56 pefo Exp $ */ 2 3 /*- 4 * Copyright (c) 1992, 1993 5 * The Regents of the University of California. All rights reserved. 6 * 7 * This code is derived from software contributed to Berkeley by 8 * Ralph Campbell and Rick Macklem. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. All advertising materials mentioning features or use of this software 19 * must display the following acknowledgement: 20 * This product includes software developed by the University of 21 * California, Berkeley and its contributors. 22 * 4. Neither the name of the University nor the names of its contributors 23 * may be used to endorse or promote products derived from this software 24 * without specific prior written permission. 25 * 26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 36 * SUCH DAMAGE. 37 * 38 * Copyright (C) 1989 Digital Equipment Corporation. 39 * Permission to use, copy, modify, and distribute this software and 40 * its documentation for any purpose and without fee is hereby granted, 41 * provided that the above copyright notice appears in all copies. 42 * Digital Equipment Corporation makes no representations about the 43 * suitability of this software for any purpose. It is provided "as is" 44 * without express or implied warranty. 45 * 46 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94 47 */ 48 49 #ifndef _CPU_H_ 50 #define _CPU_H_ 51 52 #define KUSEG_ADDR 0x0 53 #define CACHED_MEMORY_ADDR 0x80000000 54 #define UNCACHED_MEMORY_ADDR 0xa0000000 55 #define KSEG2_ADDR 0xc0000000 56 #define MAX_MEM_ADDR 0xbe000000 57 #define RESERVED_ADDR 0xbfc80000 58 59 #define CACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 60 #define PHYS_TO_CACHED(x) ((unsigned)(x) | CACHED_MEMORY_ADDR) 61 #define UNCACHED_TO_PHYS(x) ((unsigned)(x) & 0x1fffffff) 62 #define PHYS_TO_UNCACHED(x) ((unsigned)(x) | UNCACHED_MEMORY_ADDR) 63 #define VA_TO_CINDEX(x) ((unsigned)(x) & 0xffffff | CACHED_MEMORY_ADDR) 64 65 #ifdef _KERNEL 66 /* 67 * The bits in the cause register. 68 * 69 * CR_BR_DELAY Exception happened in branch delay slot. 70 * CR_COP_ERR Coprocessor error. 71 * CR_IP Interrupt pending bits defined below. 72 * CR_EXC_CODE The exception type (see exception codes below). 73 */ 74 #define CR_BR_DELAY 0x80000000 75 #define CR_COP_ERR 0x30000000 76 #define CR_EXC_CODE 0x0000007C 77 #define CR_IP 0x0000FF00 78 #define CR_EXC_CODE_SHIFT 2 79 80 /* 81 * The bits in the status register. All bits are active when set to 1. 82 */ 83 #define SR_COP_USABILITY 0xf0000000 84 #define SR_COP_0_BIT 0x10000000 85 #define SR_COP_1_BIT 0x20000000 86 #define SR_RP 0x08000000 87 #define SR_FR_32 0x04000000 88 #define SR_RE 0x02000000 89 #define SR_BOOT_EXC_VEC 0x00400000 90 #define SR_TLB_SHUTDOWN 0x00200000 91 #define SR_SOFT_RESET 0x00100000 92 #define SR_DIAG_CH 0x00040000 93 #define SR_DIAG_CE 0x00020000 94 #define SR_DIAG_PE 0x00010000 95 #define SR_KX 0x00000080 96 #define SR_SX 0x00000040 97 #define SR_UX 0x00000020 98 #define SR_KSU_MASK 0x00000018 99 #define SR_KSU_USER 0x00000010 100 #define SR_KSU_SUPER 0x00000008 101 #define SR_KSU_KERNEL 0x00000000 102 #define SR_ERL 0x00000004 103 #define SR_EXL 0x00000002 104 #define SR_INT_ENAB 0x00000001 105 /*#define SR_INT_MASK 0x0000ff00*/ 106 107 /* 108 * The interrupt masks. 109 * If a bit in the mask is 1 then the interrupt is enabled (or pending). 110 */ 111 #define INT_MASK 0x7f00 112 #define INT_MASK_5 0x8000 /* Not used (on chip timer) */ 113 #define INT_MASK_4 0x4000 114 #define INT_MASK_3 0x2000 115 #define INT_MASK_2 0x1000 116 #define INT_MASK_1 0x0800 117 #define INT_MASK_0 0x0400 118 #define HARD_INT_MASK 0x7c00 119 #define SOFT_INT_MASK_1 0x0200 120 #define SOFT_INT_MASK_0 0x0100 121 122 /* 123 * The bits in the context register. 124 */ 125 #define CNTXT_PTE_BASE 0xFF800000 126 #define CNTXT_BAD_VPN2 0x007FFFF0 127 128 /* 129 * Location of exception vectors. 130 */ 131 #define RESET_EXC_VEC 0xBFC00000 132 #define TLB_MISS_EXC_VEC 0x80000000 133 #define XTLB_MISS_EXC_VEC 0x80000080 134 #define CACHE_ERR_EXC_VEC 0x80000100 135 #define GEN_EXC_VEC 0x80000180 136 137 /* 138 * Coprocessor 0 registers: 139 */ 140 #define COP_0_TLB_INDEX $0 141 #define COP_0_TLB_RANDOM $1 142 #define COP_0_TLB_LO0 $2 143 #define COP_0_TLB_LO1 $3 144 #define COP_0_TLB_CONTEXT $4 145 #define COP_0_TLB_PG_MASK $5 146 #define COP_0_TLB_WIRED $6 147 #define COP_0_BAD_VADDR $8 148 #define COP_0_TLB_HI $10 149 #define COP_0_STATUS_REG $12 150 #define COP_0_CAUSE_REG $13 151 #define COP_0_EXC_PC $14 152 #define COP_0_PRID $15 153 #define COP_0_CONFIG $16 154 #define COP_0_LLADDR $17 155 #define COP_0_WATCH_LO $18 156 #define COP_0_WATCH_HI $19 157 #define COP_0_TLB_XCONTEXT $20 158 #define COP_0_ECC $26 159 #define COP_0_CACHE_ERR $27 160 #define COP_0_TAG_LO $28 161 #define COP_0_TAG_HI $29 162 #define COP_0_ERROR_PC $30 163 164 /* 165 * Values for the code field in a break instruction. 166 */ 167 #define BREAK_INSTR 0x0000000d 168 #define BREAK_VAL_MASK 0x03ff0000 169 #define BREAK_VAL_SHIFT 16 170 #define BREAK_KDB_VAL 512 171 #define BREAK_SSTEP_VAL 513 172 #define BREAK_BRKPT_VAL 514 173 #define BREAK_SOVER_VAL 515 174 #define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT)) 175 #define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT)) 176 #define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT)) 177 #define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT)) 178 179 /* 180 * Mininum and maximum cache sizes. 181 */ 182 #define MIN_CACHE_SIZE (16 * 1024) 183 #define MAX_CACHE_SIZE (256 * 1024) 184 185 /* 186 * The floating point version and status registers. 187 */ 188 #define FPC_ID $0 189 #define FPC_CSR $31 190 191 /* 192 * The floating point coprocessor status register bits. 193 */ 194 #define FPC_ROUNDING_BITS 0x00000003 195 #define FPC_ROUND_RN 0x00000000 196 #define FPC_ROUND_RZ 0x00000001 197 #define FPC_ROUND_RP 0x00000002 198 #define FPC_ROUND_RM 0x00000003 199 #define FPC_STICKY_BITS 0x0000007c 200 #define FPC_STICKY_INEXACT 0x00000004 201 #define FPC_STICKY_UNDERFLOW 0x00000008 202 #define FPC_STICKY_OVERFLOW 0x00000010 203 #define FPC_STICKY_DIV0 0x00000020 204 #define FPC_STICKY_INVALID 0x00000040 205 #define FPC_ENABLE_BITS 0x00000f80 206 #define FPC_ENABLE_INEXACT 0x00000080 207 #define FPC_ENABLE_UNDERFLOW 0x00000100 208 #define FPC_ENABLE_OVERFLOW 0x00000200 209 #define FPC_ENABLE_DIV0 0x00000400 210 #define FPC_ENABLE_INVALID 0x00000800 211 #define FPC_EXCEPTION_BITS 0x0003f000 212 #define FPC_EXCEPTION_INEXACT 0x00001000 213 #define FPC_EXCEPTION_UNDERFLOW 0x00002000 214 #define FPC_EXCEPTION_OVERFLOW 0x00004000 215 #define FPC_EXCEPTION_DIV0 0x00008000 216 #define FPC_EXCEPTION_INVALID 0x00010000 217 #define FPC_EXCEPTION_UNIMPL 0x00020000 218 #define FPC_COND_BIT 0x00800000 219 #define FPC_FLUSH_BIT 0x01000000 220 #define FPC_MBZ_BITS 0xfe7c0000 221 222 /* 223 * Constants to determine if have a floating point instruction. 224 */ 225 #define OPCODE_SHIFT 26 226 #define OPCODE_C1 0x11 227 228 /* 229 * The low part of the TLB entry. 230 */ 231 #define VMTLB_PF_NUM 0x3fffffc0 232 #define VMTLB_ATTR_MASK 0x00000038 233 #define VMTLB_MOD_BIT 0x00000004 234 #define VMTLB_VALID_BIT 0x00000002 235 #define VMTLB_GLOBAL_BIT 0x00000001 236 237 #define VMTLB_PHYS_PAGE_SHIFT 6 238 239 /* 240 * The high part of the TLB entry. 241 */ 242 #define VMTLB_VIRT_PAGE_NUM 0xffffe000 243 #define VMTLB_PID 0x000000ff 244 #define VMTLB_PID_SHIFT 0 245 #define VMTLB_VIRT_PAGE_SHIFT 12 246 247 /* 248 * The number of TLB entries and the first one that write random hits. 249 */ 250 /*#define VMNUM_TLB_ENTRIES 48 XXX We never use this... */ 251 #define VMWIRED_ENTRIES 8 252 253 /* 254 * The number of process id entries. 255 */ 256 #define VMNUM_PIDS 256 257 258 /* 259 * TLB probe return codes. 260 */ 261 #define VMTLB_NOT_FOUND 0 262 #define VMTLB_FOUND 1 263 #define VMTLB_FOUND_WITH_PATCH 2 264 #define VMTLB_PROBE_ERROR 3 265 266 /* 267 * Kernel virtual address for user page table entries 268 * (i.e., the address for the context register). 269 */ 270 #define VMPTE_BASE 0xFF800000 271 272 #endif /* _KERNEL */ 273 274 /* 275 * Exported definitions unique to mips cpu support. 276 */ 277 278 /* 279 * definitions of cpu-dependent requirements 280 * referenced in generic code 281 */ 282 #define COPY_SIGCODE /* copy sigcode above user stack in exec */ 283 284 #define cpu_wait(p) /* nothing */ 285 #define cpu_set_init_frame(p, fp) /* nothing */ 286 #define cpu_swapout(p) panic("cpu_swapout: can't get here"); 287 288 #ifndef _LOCORE 289 /* 290 * Arguments to hardclock and gatherstats encapsulate the previous 291 * machine state in an opaque clockframe. 292 */ 293 struct clockframe { 294 int pc; /* program counter at time of interrupt */ 295 int sr; /* status register at time of interrupt */ 296 int cr; /* cause register at time of interrupt */ 297 }; 298 299 #define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER) 300 #define CLKF_BASEPRI(framep) ((~(framep)->sr & (INT_MASK|SR_INT_ENAB)) == 0) 301 #define CLKF_PC(framep) ((framep)->pc) 302 #define CLKF_INTR(framep) (0) 303 304 /* 305 * Preempt the current process if in interrupt from user mode, 306 * or after the current trap/syscall if in system mode. 307 */ 308 #define need_resched() { want_resched = 1; aston(); } 309 310 /* 311 * Give a profiling tick to the current process when the user profiling 312 * buffer pages are invalid. On the PICA, request an ast to send us 313 * through trap, marking the proc as needing a profiling tick. 314 */ 315 #define need_proftick(p) { (p)->p_flag |= P_OWEUPC; aston(); } 316 317 /* 318 * Notify the current process (p) that it has a signal pending, 319 * process as soon as possible. 320 */ 321 #define signotify(p) aston() 322 323 #define aston() (astpending = 1) 324 325 int astpending; /* need to trap before returning to user mode */ 326 int want_resched; /* resched() was called */ 327 328 /* 329 * CPU identification, from PRID register. 330 */ 331 union cpuprid { 332 int cpuprid; 333 struct { 334 #if BYTE_ORDER == BIG_ENDIAN 335 u_int pad1:16; /* reserved */ 336 u_int cp_imp:8; /* implementation identifier */ 337 u_int cp_majrev:4; /* major revision identifier */ 338 u_int cp_minrev:4; /* minor revision identifier */ 339 #else 340 u_int cp_minrev:4; /* minor revision identifier */ 341 u_int cp_majrev:4; /* major revision identifier */ 342 u_int cp_imp:8; /* implementation identifier */ 343 u_int pad1:16; /* reserved */ 344 #endif 345 } cpu; 346 }; 347 348 /* 349 * CTL_MACHDEP definitions. 350 */ 351 #define CPU_CONSDEV 1 /* dev_t: console terminal device */ 352 #define CPU_MAXID 2 /* number of valid machdep ids */ 353 354 #define CTL_MACHDEP_NAMES { \ 355 { 0, 0 }, \ 356 { "console_device", CTLTYPE_STRUCT }, \ 357 } 358 359 #endif /* !_LOCORE */ 360 361 /* 362 * MIPS CPU types (cp_imp). 363 */ 364 #define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */ 365 #define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */ 366 #define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */ 367 #define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */ 368 #define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */ 369 #define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */ 370 #define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */ 371 #define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */ 372 #define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */ 373 #define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */ 374 #define MIPS_UNKC2 0x0c /* unnanounced product cpu ISA III */ 375 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 376 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 377 #define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */ 378 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */ 379 #define MIPS_R5000 0x23 /* MIPS R5000 based CPU ISA IV */ 380 #define MIPS_RM5230 0x28 /* QED RM5230 based CPU ISA IV */ 381 382 /* 383 * MIPS FPU types 384 */ 385 #define MIPS_SOFT 0x00 /* Software emulation ISA I */ 386 #define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */ 387 #define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */ 388 #define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */ 389 #define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */ 390 #define MIPS_R4010 0x05 /* MIPS R4000/R4400 FPC ISA II */ 391 #define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */ 392 #define MIPS_R10010 0x09 /* MIPS R10000/T5 FPU ISA IV */ 393 #define MIPS_R4210 0x0a /* MIPS R4200 FPC (ICE) ISA III */ 394 #define MIPS_UNKF1 0x0b /* unnanounced product cpu ISA III */ 395 #define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */ 396 #define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */ 397 #define MIPS_R3SONY 0x21 /* Sony R3000 based FPU ISA I */ 398 #define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */ 399 #define MIPS_R5010 0x23 /* MIPS R5000 based FPU ISA IV */ 400 #define MIPS_RM5230 0x28 /* QED RM5230 based FPU ISA IV */ 401 402 #if defined(_KERNEL) && !defined(_LOCORE) 403 union cpuprid cpu_id; 404 union cpuprid fpu_id; 405 u_int CpuPrimaryDataCacheSize; 406 u_int CpuPrimaryInstCacheSize; 407 u_int CpuPrimaryDataCacheLSize; 408 u_int CpuPrimaryInstCacheLSize; 409 u_int CpuCacheAliasMask; 410 u_int CpuTwoWayCache; 411 int l2cache_is_snooping; 412 extern struct intr_tab intr_tab[]; 413 414 struct tlb; 415 struct user; 416 417 int R4K_ConfigCache __P((void)); 418 void R4K_SetWIRED __P((int)); 419 void R4K_SetPID __P((int)); 420 void R4K_FlushCache __P((void)); 421 void R4K_FlushDCache __P((vm_offset_t, int)); 422 void R4K_HitFlushDCache __P((vm_offset_t, int)); 423 void R4K_FlushICache __P((vm_offset_t, int)); 424 void R4K_TLBFlush __P((int)); 425 void R4K_TLBFlushAddr __P((vm_offset_t)); 426 void R4K_TLBWriteIndexed __P((int, struct tlb *)); 427 void R4K_TLBUpdate __P((vm_offset_t, unsigned)); 428 void R4K_TLBRead __P((int, struct tlb *)); 429 void wbflush __P((void)); 430 void savectx __P((struct user *, int)); 431 int copykstack __P((struct user *)); 432 void switch_exit __P((void)); 433 void MachSaveCurFPState __P((struct proc *)); 434 #ifdef DEBUG 435 void mdbpanic __P((void)); 436 #endif 437 438 #endif 439 440 /* 441 * Enable realtime clock (always enabled). 442 */ 443 #define enablertclock() 444 445 #endif /* _CPU_H_ */ 446
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