intr.h revision 1.1 1 /* $NetBSD: intr.h,v 1.1 2000/01/23 20:24:28 soda Exp $ */
2
3 /*
4 * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Charles M. Hannum.
17 * 4. The name of the author may not be used to endorse or promote products
18 * derived from this software without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 */
31
32 #ifndef _ARC_INTR_H_
33 #define _ARC_INTR_H_
34
35 /* Interrupt priority `levels'; not mutually exclusive. */
36 #define IPL_BIO 0 /* block I/O */
37 #define IPL_NET 1 /* network */
38 #define IPL_TTY 2 /* terminal */
39 #define IPL_CLOCK 3 /* clock */
40 #define IPL_IMP 4 /* memory allocation */
41 #define IPL_NONE 5 /* nothing */
42 #define IPL_HIGH 6 /* everything */
43
44 /* Interrupt sharing types. */
45 #define IST_NONE 0 /* none */
46 #define IST_PULSE 1 /* pulsed */
47 #define IST_EDGE 2 /* edge-triggered */
48 #define IST_LEVEL 3 /* level-triggered */
49
50 /* Soft interrupt masks. */
51 #define SIR_CLOCK 31
52 #define SIR_CLOCKMASK ((1 << SIR_CLOCK))
53 #define SIR_NET 30
54 #define SIR_NETMASK ((1 << SIR_NET) | SIR_CLOCKMASK)
55 #define SIR_TTY 29
56 #define SIR_TTYMASK ((1 << SIR_TTY) | SIR_CLOCKMASK)
57 #define SIR_ALLMASK (SIR_CLOCKMASK | SIR_NETMASK | SIR_TTYMASK)
58
59 #ifndef _LOCORE
60
61 void setsoftclock __P((void));
62 void clearsoftclock __P((void));
63 int splsoftclock __P((void));
64 void setsoftnet __P((void));
65 void clearsoftnet __P((void));
66 int splsoftnet __P((void));
67
68 struct clockframe;
69 void set_intr __P((int, int(*)(u_int, struct clockframe *), int));
70
71 volatile int cpl, ipending, astpending;
72 int imask[7];
73
74 #if 0
75 extern void Xspllower __P((void));
76
77 static __inline int splraise __P((int));
78 static __inline int spllower __P((int));
79 static __inline void splx __P((int));
80 static __inline void softintr __P((int));
81
82 /*
83 * Add a mask to cpl, and return the old value of cpl.
84 */
85 static __inline int
86 splraise(ncpl)
87 register int ncpl;
88 {
89 register int ocpl = cpl;
90
91 cpl = ocpl | ncpl;
92 return (ocpl);
93 }
94
95 /*
96 * Restore a value to cpl (unmasking interrupts). If any unmasked
97 * interrupts are pending, call Xspllower() to process them.
98 */
99 static __inline void
100 splx(ncpl)
101 register int ncpl;
102 {
103
104 cpl = ncpl;
105 if (ipending & ~ncpl)
106 Xspllower();
107 }
108
109 /*
110 * Same as splx(), but we return the old value of spl, for the
111 * benefit of some splsoftclock() callers.
112 */
113 static __inline int
114 spllower(ncpl)
115 register int ncpl;
116 {
117 register int ocpl = cpl;
118
119 cpl = ncpl;
120 if (ipending & ~ncpl)
121 Xspllower();
122 return (ocpl);
123 }
124 #endif
125
126 /*
127 * Hardware interrupt masks
128 */
129 #if 0
130 #define splbio() splraise(imask[IPL_BIO])
131 #define splnet() splraise(imask[IPL_NET])
132 #define spltty() splraise(imask[IPL_TTY])
133 #define splclock() splraise(imask[IPL_CLOCK])
134 #define splimp() splraise(imask[IPL_IMP])
135 #define splstatclock() splclock()
136
137 /*
138 * Software interrupt masks
139 *
140 * NOTE: splsoftclock() is used by hardclock() to lower the priority from
141 * clock to softclock before it calls softclock().
142 */
143 #define splsoftclock() spllower(SIR_CLOCKMASK)
144 #define splsoftnet() splraise(SIR_NETMASK)
145 #define splsofttty() splraise(SIR_TTYMASK)
146
147 /*
148 * Miscellaneous
149 */
150 #define splhigh() splraise(-1)
151 #define spl0() spllower(0)
152
153 /*
154 * Software interrupt registration
155 *
156 * We hand-code this to ensure that it's atomic.
157 */
158 static __inline void
159 softintr(mask)
160 register int mask;
161 {
162
163 __asm __volatile("orl %0,_ipending" : : "ir" (mask));
164 }
165
166 #define setsoftast() (astpending = 1)
167 #define setsoftclock() softintr(1 << SIR_CLOCK)
168 #define setsoftnet() softintr(1 << SIR_NET)
169 #define setsofttty() softintr(1 << SIR_TTY)
170 #endif
171
172 #endif /* _LOCORE */
173
174 #endif /* _ARC_INTR_H_ */
175