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intr.h revision 1.18.14.1 
      1 /*	$NetBSD: intr.h,v 1.18.14.1 2007/06/26 18:12:13 garbled Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 2000, 2001 The NetBSD Foundation, Inc.
      5  * All rights reserved.
      6  *
      7  * This code is derived from software contributed to The NetBSD Foundation
      8  * by Jason R. Thorpe.
      9  *
     10  * Redistribution and use in source and binary forms, with or without
     11  * modification, are permitted provided that the following conditions
     12  * are met:
     13  * 1. Redistributions of source code must retain the above copyright
     14  *    notice, this list of conditions and the following disclaimer.
     15  * 2. Redistributions in binary form must reproduce the above copyright
     16  *    notice, this list of conditions and the following disclaimer in the
     17  *    documentation and/or other materials provided with the distribution.
     18  * 3. All advertising materials mentioning features or use of this software
     19  *    must display the following acknowledgement:
     20  *	This product includes software developed by the NetBSD
     21  *	Foundation, Inc. and its contributors.
     22  * 4. Neither the name of The NetBSD Foundation nor the names of its
     23  *    contributors may be used to endorse or promote products derived
     24  *    from this software without specific prior written permission.
     25  *
     26  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     27  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     28  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     29  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     30  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     31  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     32  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     33  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     34  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     35  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     36  * POSSIBILITY OF SUCH DAMAGE.
     37  */
     38 
     39 #ifndef _ARC_INTR_H_
     40 #define _ARC_INTR_H_
     41 
     42 #define IPL_NONE	0	/* disable only this interrupt */
     43 #define IPL_SOFT	1	/* generic software interrupts (SI 0) */
     44 #define IPL_SOFTCLOCK	2	/* clock software interrupts (SI 0) */
     45 #define IPL_SOFTNET	3	/* network software interrupts (SI 1) */
     46 #define IPL_SOFTSERIAL	4	/* serial software interrupts (SI 1) */
     47 #define IPL_BIO		5	/* disable block I/O interrupts */
     48 #define IPL_NET		6	/* disable network interrupts */
     49 #define IPL_TTY		7	/* disable terminal interrupts */
     50 #define	IPL_LPT		IPL_TTY
     51 #define	IPL_VM		IPL_TTY
     52 #define IPL_SERIAL	7	/* disable serial hardware interrupts */
     53 #define IPL_CLOCK	8	/* disable clock interrupts */
     54 #define	IPL_STATCLOCK	IPL_CLOCK
     55 #define	IPL_SCHED	IPL_CLOCK
     56 #define IPL_HIGH	8	/* disable all interrupts */
     57 #define	IPL_LOCK	IPL_HIGH
     58 
     59 #define _IPL_N		9
     60 
     61 #define _IPL_SI0_FIRST	IPL_SOFT
     62 #define _IPL_SI0_LAST	IPL_SOFTCLOCK
     63 
     64 #define _IPL_SI1_FIRST	IPL_SOFTNET
     65 #define _IPL_SI1_LAST	IPL_SOFTSERIAL
     66 
     67 #define	SI_SOFT		0
     68 #define	SI_SOFTCLOCK	1
     69 #define	SI_SOFTNET	2
     70 #define	SI_SOFTSERIAL	3
     71 
     72 #define	SI_NQUEUES	4
     73 
     74 #define	SI_QUEUENAMES {							\
     75 	"misc",								\
     76 	"clock",							\
     77 	"net",								\
     78 	"serial",							\
     79 }
     80 
     81 /* Interrupt sharing types. */
     82 #define IST_NONE	0	/* none */
     83 #define IST_PULSE	1	/* pulsed */
     84 #define IST_EDGE	2	/* edge-triggered */
     85 #define IST_LEVEL	3	/* level-triggered */
     86 
     87 #ifdef _KERNEL
     88 #ifndef _LOCORE
     89 
     90 #include <mips/locore.h>
     91 
     92 extern const uint32_t *ipl_sr_bits;
     93 
     94 #define spl0()		(void)_spllower(0)
     95 #define splx(s)		(void)_splset(s)
     96 
     97 typedef int ipl_t;
     98 typedef struct {
     99 	ipl_t _sr;
    100 } ipl_cookie_t;
    101 
    102 static inline ipl_cookie_t
    103 makeiplcookie(ipl_t ipl)
    104 {
    105 
    106 	return (ipl_cookie_t){._sr = ipl_sr_bits[ipl]};
    107 }
    108 
    109 static inline int
    110 splraiseipl(ipl_cookie_t icookie)
    111 {
    112 
    113 	return _splraise(icookie._sr);
    114 }
    115 
    116 #include <sys/spl.h>
    117 
    118 #include <mips/softintr.h>
    119 
    120 struct clockframe;
    121 void arc_set_intr(uint32_t, uint32_t (*)(uint32_t, struct clockframe *), int);
    122 extern uint32_t cpu_int_mask;
    123 
    124 /* priority order to handle each CPU INT line specified via set_intr() */
    125 #define ARC_INTPRI_TIMER_INT	0	/* independent CPU INT for timer */
    126 #define ARC_INTPRI_JAZZ		1	/* CPU INT for JAZZ local bus */
    127 #define ARC_INTPRI_PCIISA	2	/* CPU INT for PCI/EISA/ISA */
    128 #define ARC_NINTPRI		3	/* number of total used CPU INTs */
    129 
    130 #endif /* !_LOCORE */
    131 #endif /* _KERNEL */
    132 
    133 #endif /* _ARC_INTR_H_ */
    134