intr.h revision 1.2
1 /* $NetBSD: intr.h,v 1.2 2000/01/23 21:01:56 soda Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _ARC_INTR_H_ 34 #define _ARC_INTR_H_ 35 36 #define IPL_NONE 0 /* disable only this interrupt */ 37 #define IPL_BIO 1 /* disable block I/O interrupts */ 38 #define IPL_NET 2 /* disable network interrupts */ 39 #define IPL_TTY 3 /* disable terminal interrupts */ 40 #define IPL_IMP 4 /* memory allocation */ 41 #define IPL_CLOCK 5 /* disable clock interrupts */ 42 #define IPL_STATCLOCK 6 /* disable profiling interrupts */ 43 #if 0 /* XXX */ 44 #define IPL_SERIAL 7 /* disable serial hardware interrupts */ 45 #endif 46 #define IPL_HIGH 8 /* disable all interrupts */ 47 #define NIPL 9 48 49 /* Interrupt sharing types. */ 50 #define IST_NONE 0 /* none */ 51 #define IST_PULSE 1 /* pulsed */ 52 #define IST_EDGE 2 /* edge-triggered */ 53 #define IST_LEVEL 3 /* level-triggered */ 54 55 /* Soft interrupt masks. */ 56 /* XXX - revisit here */ 57 #define SIR_CLOCK 31 58 #define SIR_NET 30 59 #define SIR_CLOCKMASK ((1 << SIR_CLOCK)) 60 #define SIR_NETMASK ((1 << SIR_NET) | SIR_CLOCKMASK) 61 #define SIR_ALLMASK (SIR_CLOCKMASK | SIR_NETMASK) 62 63 #ifdef _KERNEL 64 #ifndef _LOCORE 65 66 #include <mips/cpuregs.h> 67 68 extern int _splraise __P((int)); 69 extern int _spllower __P((int)); 70 extern int _splset __P((int)); 71 extern int _splget __P((void)); 72 extern void _splnone __P((void)); 73 extern void _setsoftintr __P((int)); 74 extern void _clrsoftintr __P((int)); 75 76 #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0) 77 #define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1) 78 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0) 79 #define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1) 80 81 #define splhigh() _splraise(MIPS_INT_MASK) 82 #define spl0() (void)_spllower(0) 83 #define splx(s) (void)_splset(s) 84 #define splbio() (_splraise(splvec.splbio)) 85 #define splnet() (_splraise(splvec.splnet)) 86 #define spltty() (_splraise(splvec.spltty)) 87 #define splimp() (_splraise(splvec.splimp)) 88 #define splpmap() (_splraise(splvec.splimp)) 89 #define splclock() (_splraise(splvec.splclock)) 90 #define splstatclock() (_splraise(splvec.splstatclock)) 91 #define spllowersoftclock() _spllower(MIPS_SOFT_INT_MASK_0) 92 #define splsoftclock() _splraise(MIPS_SOFT_INT_MASK_0) 93 #define splsoftnet() _splraise(MIPS_SOFT_INT_MASK_1) 94 95 #define spllpt() spltty() /* lpt driver */ 96 97 struct splvec { 98 int splbio; 99 int splnet; 100 int spltty; 101 int splimp; 102 int splclock; 103 int splstatclock; 104 }; 105 extern struct splvec splvec; 106 107 /* Conventionals ... */ 108 109 #define MIPS_SPLHIGH (MIPS_INT_MASK) 110 #define MIPS_SOFT_INT_MASK (MIPS_SOFT_INT_MASK_0|MIPS_SOFT_INT_MASK_1) 111 #define MIPS_INTMASK_0 (MIPS_INT_MASK_0|MIPS_SOFT_INT_MASK) 112 #define MIPS_INTMASK_0_to_1 (MIPS_INT_MASK_1|MIPS_INTMASK_0) 113 #define MIPS_INTMASK_0_to_2 (MIPS_INT_MASK_2|MIPS_INTMASK_0_to_1) 114 #define MIPS_INTMASK_0_to_3 (MIPS_INT_MASK_3|MIPS_INTMASK_0_to_2) 115 #define MIPS_INTMASK_0_to_4 (MIPS_INT_MASK_4|MIPS_INTMASK_0_to_3) 116 #define MIPS_INTMASK_0_to_5 (MIPS_INT_MASK_5|MIPS_INTMASK_0_to_4) 117 118 /* 119 * Index into intrcnt[], which is defined in locore 120 */ 121 #define SOFTCLOCK_INTR 0 122 #define SOFTNET_INTR 1 123 #define FPU_INTR 2 124 extern u_long intrcnt[]; 125 126 /* handle i/o device interrupts */ 127 extern int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned)); 128 int arc_hardware_intr __P((unsigned, unsigned, unsigned, unsigned)); 129 130 struct clockframe; 131 void set_intr __P((int, int(*)(u_int, struct clockframe *), int)); 132 133 /* XXX - revisit here */ 134 int imask[NIPL]; 135 136 #endif /* !_LOCORE */ 137 #endif /* _KERNEL */ 138 139 #endif /* _ARC_INTR_H_ */ 140
Indexes created Wed Sep 24 22:09:59 GMT 2025