intr.h revision 1.3
1 /* $NetBSD: intr.h,v 1.3 2000/04/03 11:44:20 soda Exp $ */ 2 3 /* 4 * Copyright (c) 1998 Jonathan Stone. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Jonathan Stone for 17 * the NetBSD Project. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _ARC_INTR_H_ 34 #define _ARC_INTR_H_ 35 36 #define IPL_NONE 0 /* disable only this interrupt */ 37 #define IPL_BIO 1 /* disable block I/O interrupts */ 38 #define IPL_NET 2 /* disable network interrupts */ 39 #define IPL_TTY 3 /* disable terminal interrupts */ 40 #define IPL_IMP 4 /* memory allocation */ 41 #define IPL_CLOCK 5 /* disable clock interrupts */ 42 #define IPL_STATCLOCK 6 /* disable profiling interrupts */ 43 #if 0 /* XXX */ 44 #define IPL_SERIAL 7 /* disable serial hardware interrupts */ 45 #endif 46 #define IPL_HIGH 8 /* disable all interrupts */ 47 #define NIPL 9 48 49 /* Interrupt sharing types. */ 50 #define IST_NONE 0 /* none */ 51 #define IST_PULSE 1 /* pulsed */ 52 #define IST_EDGE 2 /* edge-triggered */ 53 #define IST_LEVEL 3 /* level-triggered */ 54 55 /* Soft interrupt masks. */ 56 /* XXX - revisit here */ 57 #define SIR_CLOCK 31 58 #define SIR_NET 30 59 #define SIR_CLOCKMASK ((1 << SIR_CLOCK)) 60 #define SIR_NETMASK ((1 << SIR_NET) | SIR_CLOCKMASK) 61 #define SIR_ALLMASK (SIR_CLOCKMASK | SIR_NETMASK) 62 63 #ifdef _KERNEL 64 #ifndef _LOCORE 65 66 #include <mips/cpuregs.h> 67 68 extern int _splraise __P((int)); 69 extern int _spllower __P((int)); 70 extern int _splset __P((int)); 71 extern int _splget __P((void)); 72 extern void _splnone __P((void)); 73 extern void _setsoftintr __P((int)); 74 extern void _clrsoftintr __P((int)); 75 76 #define setsoftclock() _setsoftintr(MIPS_SOFT_INT_MASK_0) 77 #define setsoftnet() _setsoftintr(MIPS_SOFT_INT_MASK_1) 78 #define clearsoftclock() _clrsoftintr(MIPS_SOFT_INT_MASK_0) 79 #define clearsoftnet() _clrsoftintr(MIPS_SOFT_INT_MASK_1) 80 81 /* 82 * nesting interrupt masks. 83 */ 84 #define MIPS_INT_MASK_SPL_SOFT0 MIPS_SOFT_INT_MASK_0 85 #define MIPS_INT_MASK_SPL_SOFT1 (MIPS_SOFT_INT_MASK_1|MIPS_INT_MASK_SPL_SOFT0) 86 #define MIPS_INT_MASK_SPL0 (MIPS_INT_MASK_0|MIPS_INT_MASK_SPL_SOFT1) 87 #define MIPS_INT_MASK_SPL1 (MIPS_INT_MASK_1|MIPS_INT_MASK_SPL0) 88 #define MIPS_INT_MASK_SPL2 (MIPS_INT_MASK_2|MIPS_INT_MASK_SPL1) 89 #define MIPS_INT_MASK_SPL3 (MIPS_INT_MASK_3|MIPS_INT_MASK_SPL2) 90 #define MIPS_INT_MASK_SPL4 (MIPS_INT_MASK_4|MIPS_INT_MASK_SPL3) 91 #define MIPS_INT_MASK_SPL5 (MIPS_INT_MASK_5|MIPS_INT_MASK_SPL4) 92 #define MIPS_INT_MASK_SPLHIGH MIPS_INT_MASK_SPL5 93 94 #define spl0() (void)_spllower(0) 95 #define splx(s) (void)_splset(s) 96 #define splbio() (_splraise(splvec.splbio)) 97 #define splnet() (_splraise(splvec.splnet)) 98 #define spltty() (_splraise(splvec.spltty)) 99 #define splimp() (_splraise(splvec.splimp)) 100 #define splpmap() (_splraise(splvec.splimp)) 101 #define splclock() (_splraise(splvec.splclock)) 102 #define splstatclock() (_splraise(splvec.splstatclock)) 103 #define splhigh() _splraise(MIPS_INT_MASK_SPLHIGH) 104 105 #define splsoftclock() _splraise(MIPS_INT_MASK_SPL_SOFT0) 106 #define splsoftnet() _splraise(MIPS_INT_MASK_SPL_SOFT1) 107 #define spllowersoftclock() _spllower(MIPS_INT_MASK_SPL_SOFT0) 108 109 #define spllpt() spltty() /* lpt driver */ 110 111 struct splvec { 112 int splbio; 113 int splnet; 114 int spltty; 115 int splimp; 116 int splclock; 117 int splstatclock; 118 }; 119 extern struct splvec splvec; 120 121 /* 122 * Index into intrcnt[], which is defined in locore 123 */ 124 #define SOFTCLOCK_INTR 0 125 #define SOFTNET_INTR 1 126 #define FPU_INTR 2 127 extern u_long intrcnt[]; 128 129 /* handle i/o device interrupts */ 130 extern int (*mips_hardware_intr) __P((unsigned, unsigned, unsigned, unsigned)); 131 int arc_hardware_intr __P((unsigned, unsigned, unsigned, unsigned)); 132 133 struct clockframe; 134 void set_intr __P((int, int(*)(u_int, struct clockframe *), int)); 135 136 /* XXX - revisit here */ 137 int imask[NIPL]; 138 139 #endif /* !_LOCORE */ 140 #endif /* _KERNEL */ 141 142 #endif /* _ARC_INTR_H_ */ 143
Indexes created Sat Sep 27 22:09:54 GMT 2025