isabus.c revision 1.26
1 /* $NetBSD: isabus.c,v 1.26 2004/08/30 15:05:16 drochner Exp $ */ 2 /* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */ 3 /* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */ 4 5 /*- 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz and Don Ahn. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)isa.c 7.2 (Berkeley) 5/12/91 37 */ 38 /*- 39 * Copyright (c) 1995 Per Fogelstrom 40 * Copyright (c) 1993, 1994 Charles M. Hannum. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * William Jolitz and Don Ahn. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)isa.c 7.2 (Berkeley) 5/12/91 74 */ 75 /* 76 * Mach Operating System 77 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 78 * All Rights Reserved. 79 * 80 * Permission to use, copy, modify and distribute this software and its 81 * documentation is hereby granted, provided that both the copyright 82 * notice and this permission notice appear in all copies of the 83 * software, derivative works or modified versions, and any portions 84 * thereof, and that both notices appear in supporting documentation. 85 * 86 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 87 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 88 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 89 * 90 * Carnegie Mellon requests users of this software to return to 91 * 92 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 93 * School of Computer Science 94 * Carnegie Mellon University 95 * Pittsburgh PA 15213-3890 96 * 97 * any improvements or extensions that they make and grant Carnegie Mellon 98 * the rights to redistribute these changes. 99 */ 100 /* 101 Copyright 1988, 1989 by Intel Corporation, Santa Clara, California. 102 103 All Rights Reserved 104 105 Permission to use, copy, modify, and distribute this software and 106 its documentation for any purpose and without fee is hereby 107 granted, provided that the above copyright notice appears in all 108 copies and that both the copyright notice and this permission notice 109 appear in supporting documentation, and that the name of Intel 110 not be used in advertising or publicity pertaining to distribution 111 of the software without specific, written prior permission. 112 113 INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 114 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, 115 IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 116 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 117 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 118 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 119 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 120 */ 121 122 #include <sys/cdefs.h> 123 __KERNEL_RCSID(0, "$NetBSD: isabus.c,v 1.26 2004/08/30 15:05:16 drochner Exp $"); 124 125 #include <sys/param.h> 126 #include <sys/proc.h> 127 #include <sys/user.h> 128 #include <sys/systm.h> 129 #include <sys/callout.h> 130 #include <sys/time.h> 131 #include <sys/kernel.h> 132 #include <sys/device.h> 133 #include <sys/malloc.h> 134 #include <sys/extent.h> 135 136 #include <uvm/uvm_extern.h> 137 138 #include <machine/cpu.h> 139 #include <machine/pio.h> 140 #include <machine/autoconf.h> 141 #include <machine/intr.h> 142 143 #include <dev/ic/i8253reg.h> 144 #include <dev/isa/isareg.h> 145 #include <dev/isa/isavar.h> 146 #include <arc/isa/isabrvar.h> 147 #include <arc/isa/spkrreg.h> 148 149 static int beeping; 150 static struct callout sysbeep_ch = CALLOUT_INITIALIZER; 151 152 static long isa_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 153 static long isa_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 154 155 #define IRQ_SLAVE 2 156 157 /* Definition of the driver for autoconfig. */ 158 int isabrprint(void *, const char *); 159 160 extern struct arc_bus_space arc_bus_io, arc_bus_mem; 161 162 void isabr_attach_hook __P((struct device *, struct device *, 163 struct isabus_attach_args *)); 164 const struct evcnt *isabr_intr_evcnt __P((isa_chipset_tag_t, int)); 165 void *isabr_intr_establish __P((isa_chipset_tag_t, int, int, int, 166 int (*)(void *), void *)); 167 void isabr_intr_disestablish __P((isa_chipset_tag_t, void*)); 168 int isabr_iointr __P((unsigned int, struct clockframe *)); 169 void isabr_initicu __P((void)); 170 void intr_calculatemasks __P((void)); 171 int fakeintr __P((void *a)); 172 173 struct isabr_config *isabr_conf = NULL; 174 u_int32_t imask[_IPL_N]; /* XXX */ 175 176 void 177 isabrattach(sc) 178 struct isabr_softc *sc; 179 { 180 struct isabus_attach_args iba; 181 182 if (isabr_conf == NULL) 183 panic("isabr_conf isn't initialized"); 184 185 printf("\n"); 186 187 /* Initialize interrupt controller */ 188 isabr_initicu(); 189 190 /*XXX we may remove the abus part of the softc struct... */ 191 sc->sc_bus.ab_dv = (struct device *)sc; 192 sc->sc_bus.ab_type = BUS_ISABR; 193 194 sc->arc_isa_cs.ic_attach_hook = isabr_attach_hook; 195 sc->arc_isa_cs.ic_intr_evcnt = isabr_intr_evcnt; 196 sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish; 197 sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish; 198 199 arc_bus_space_init_extent(&arc_bus_mem, (caddr_t)isa_mem_ex_storage, 200 sizeof(isa_mem_ex_storage)); 201 arc_bus_space_init_extent(&arc_bus_io, (caddr_t)isa_io_ex_storage, 202 sizeof(isa_io_ex_storage)); 203 204 iba.iba_iot = &arc_bus_io; 205 iba.iba_memt = &arc_bus_mem; 206 iba.iba_dmat = &sc->sc_dmat; 207 iba.iba_ic = &sc->arc_isa_cs; 208 config_found_ia(&sc->sc_dev, "isabus", &iba, isabrprint); 209 } 210 211 int 212 isabrprint(aux, pnp) 213 void *aux; 214 const char *pnp; 215 { 216 217 if (pnp) 218 aprint_normal("isa at %s", pnp); 219 aprint_verbose(" isa_io_base 0x%lx isa_mem_base 0x%lx", 220 arc_bus_io.bs_vbase, arc_bus_mem.bs_vbase); 221 return (UNCONF); 222 } 223 224 225 /* 226 * Interrupt system driver code 227 * ============================ 228 */ 229 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 230 231 int imen; 232 int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN]; 233 struct intrhand *intrhand[ICU_LEN]; 234 235 int fakeintr(a) 236 void *a; 237 { 238 return 0; 239 } 240 241 /* 242 * Recalculate the interrupt masks from scratch. 243 * We could code special registry and deregistry versions of this function that 244 * would be faster, but the code would be nastier, and we don't expect this to 245 * happen very much anyway. 246 */ 247 void 248 intr_calculatemasks() 249 { 250 int irq, level; 251 struct intrhand *q; 252 253 /* First, figure out which levels each IRQ uses. */ 254 for (irq = 0; irq < ICU_LEN; irq++) { 255 int levels = 0; 256 for (q = intrhand[irq]; q; q = q->ih_next) 257 levels |= 1 << q->ih_level; 258 intrlevel[irq] = levels; 259 } 260 261 /* Then figure out which IRQs use each level. */ 262 for (level = 0; level < _IPL_N; level++) { 263 int irqs = 0; 264 for (irq = 0; irq < ICU_LEN; irq++) 265 if (intrlevel[irq] & (1 << level)) 266 irqs |= 1 << irq; 267 imask[level] = irqs; 268 } 269 270 imask[IPL_NONE] = 0; 271 272 imask[IPL_SOFT] |= imask[IPL_NONE]; 273 imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 274 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 275 imask[IPL_SOFTSERIAL] |= imask[IPL_SOFTNET]; 276 277 /* 278 * Enforce a hierarchy that gives slow devices a better chance at not 279 * dropping data. 280 */ 281 imask[IPL_BIO] |= imask[IPL_SOFTSERIAL]; 282 imask[IPL_NET] |= imask[IPL_BIO]; 283 imask[IPL_TTY] |= imask[IPL_NET]; 284 285 /* 286 * Since run queues may be manipulated by both the statclock and tty, 287 * network, and diskdrivers, clock > tty. 288 */ 289 imask[IPL_CLOCK] |= imask[IPL_TTY]; 290 imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 291 292 /* 293 * IPL_HIGH must block everything that can manipulate a run queue. 294 */ 295 imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 296 297 /* And eventually calculate the complete masks. */ 298 for (irq = 0; irq < ICU_LEN; irq++) { 299 int irqs = 1 << irq; 300 for (q = intrhand[irq]; q; q = q->ih_next) 301 irqs |= imask[q->ih_level]; 302 intrmask[irq] = irqs; 303 } 304 305 /* Lastly, determine which IRQs are actually in use. */ 306 { 307 int irqs = 0; 308 for (irq = 0; irq < ICU_LEN; irq++) 309 if (intrhand[irq]) 310 irqs |= 1 << irq; 311 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 312 irqs |= 1 << IRQ_SLAVE; 313 imen = ~irqs; 314 isa_outb(IO_ICU1 + 1, imen); 315 isa_outb(IO_ICU2 + 1, imen >> 8); 316 } 317 } 318 319 void 320 isabr_attach_hook(parent, self, iba) 321 struct device *parent, *self; 322 struct isabus_attach_args *iba; 323 { 324 325 /* Nothing to do. */ 326 } 327 328 const struct evcnt * 329 isabr_intr_evcnt(ic, irq) 330 isa_chipset_tag_t ic; 331 int irq; 332 { 333 334 /* XXX for now, no evcnt parent reported */ 335 return NULL; 336 } 337 338 /* 339 * Establish a ISA bus interrupt. 340 */ 341 void * 342 isabr_intr_establish(ic, irq, type, level, ih_fun, ih_arg) 343 isa_chipset_tag_t ic; 344 int irq; 345 int type; 346 int level; 347 int (*ih_fun) __P((void *)); 348 void *ih_arg; 349 { 350 struct intrhand **p, *q, *ih; 351 static struct intrhand fakehand = {NULL, fakeintr}; 352 353 /* no point in sleeping unless someone can free memory. */ 354 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 355 if (ih == NULL) 356 panic("isa_intr_establish: can't malloc handler info"); 357 358 if (!LEGAL_IRQ(irq) || type == IST_NONE) 359 panic("intr_establish: bogus irq or type"); 360 361 switch (intrtype[irq]) { 362 case IST_NONE: 363 intrtype[irq] = type; 364 break; 365 case IST_EDGE: 366 case IST_LEVEL: 367 if (type == intrtype[irq]) 368 break; 369 case IST_PULSE: 370 if (type != IST_NONE) 371 panic("intr_establish: can't share %s with %s", 372 isa_intr_typename(intrtype[irq]), 373 isa_intr_typename(type)); 374 break; 375 } 376 377 /* 378 * Figure out where to put the handler. 379 * This is O(N^2), but we want to preserve the order, and N is 380 * generally small. 381 */ 382 for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 383 ; 384 385 /* 386 * Actually install a fake handler momentarily, since we might be doing 387 * this with interrupts enabled and don't want the real routine called 388 * until masking is set up. 389 */ 390 fakehand.ih_level = level; 391 *p = &fakehand; 392 393 intr_calculatemasks(); 394 395 /* 396 * Poke the real handler in now. 397 */ 398 ih->ih_fun = ih_fun; 399 ih->ih_arg = ih_arg; 400 ih->ih_count = 0; 401 ih->ih_next = NULL; 402 ih->ih_level = level; 403 ih->ih_irq = irq; 404 ih->ih_what = ""; /* XXX - should be eliminated */ 405 *p = ih; 406 407 return (ih); 408 } 409 410 void 411 isabr_intr_disestablish(ic, arg) 412 isa_chipset_tag_t ic; 413 void *arg; 414 { 415 416 } 417 418 /* 419 * Process an interrupt from the ISA bus. 420 */ 421 int 422 isabr_iointr(mask, cf) 423 unsigned mask; 424 struct clockframe *cf; 425 { 426 struct intrhand *ih; 427 int isa_vector; 428 int o_imen; 429 430 isa_vector = (*isabr_conf->ic_intr_status)(); 431 if (isa_vector < 0) 432 return (~0); 433 434 o_imen = imen; 435 imen |= 1 << (isa_vector & (ICU_LEN - 1)); 436 if(isa_vector & 0x08) { 437 isa_inb(IO_ICU2 + 1); 438 isa_outb(IO_ICU2 + 1, imen >> 8); 439 isa_outb(IO_ICU2, 0x60 + (isa_vector & 7)); 440 isa_outb(IO_ICU1, 0x60 + IRQ_SLAVE); 441 } 442 else { 443 isa_inb(IO_ICU1 + 1); 444 isa_outb(IO_ICU1 + 1, imen); 445 isa_outb(IO_ICU1, 0x60 + isa_vector); 446 } 447 ih = intrhand[isa_vector]; 448 if(isa_vector == 0) { /* Clock */ /*XXX*/ 449 (*ih->ih_fun)(cf); 450 ih = ih->ih_next; 451 } 452 while(ih) { 453 (*ih->ih_fun)(ih->ih_arg); 454 ih = ih->ih_next; 455 } 456 imen = o_imen; 457 isa_inb(IO_ICU1 + 1); 458 isa_inb(IO_ICU2 + 1); 459 isa_outb(IO_ICU1 + 1, imen); 460 isa_outb(IO_ICU2 + 1, imen >> 8); 461 462 return(~0); /* Dont reenable */ 463 } 464 465 466 /* 467 * Initialize the Interrupt controller logic. 468 */ 469 void 470 isabr_initicu() 471 { 472 473 int i; 474 475 for (i = 0; i < ICU_LEN; i++) { 476 switch (i) { 477 case 2: 478 case 8: 479 intrtype[i] = IST_EDGE; 480 break; 481 default: 482 intrtype[i] = IST_NONE; 483 break; 484 } 485 } 486 487 isa_outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 488 isa_outb(IO_ICU1+1, 0); /* starting at this vector index */ 489 isa_outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */ 490 isa_outb(IO_ICU1+1, 1); /* 8086 mode */ 491 isa_outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 492 isa_outb(IO_ICU1, 0x68); /* special mask mode (if available) */ 493 isa_outb(IO_ICU1, 0x0a); /* Read IRR by default. */ 494 #ifdef REORDER_IRQ 495 isa_outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 496 #endif 497 498 isa_outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 499 isa_outb(IO_ICU2+1, 8); /* staring at this vector index */ 500 isa_outb(IO_ICU2+1, IRQ_SLAVE); 501 isa_outb(IO_ICU2+1, 1); /* 8086 mode */ 502 isa_outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 503 isa_outb(IO_ICU2, 0x68); /* special mask mode (if available) */ 504 isa_outb(IO_ICU2, 0x0a); /* Read IRR by default. */ 505 } 506 507 508 /* 509 * SPEAKER BEEPER... 510 */ 511 void 512 sysbeepstop(arg) 513 void *arg; 514 { 515 int s; 516 517 /* disable counter 2 */ 518 s = splhigh(); 519 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) & ~PIT_SPKR); 520 splx(s); 521 beeping = 0; 522 } 523 524 void 525 sysbeep(pitch, period) 526 int pitch, period; 527 { 528 static int last_pitch, last_period; 529 int s; 530 531 if (cold) 532 return; /* Can't beep yet. */ 533 534 if (beeping) 535 callout_stop(&sysbeep_ch); 536 if (!beeping || last_pitch != pitch) { 537 s = splhigh(); 538 isa_outb(IO_TIMER1 + TIMER_MODE, 539 TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE); 540 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256); 541 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256); 542 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) | PIT_SPKR); 543 splx(s); 544 } 545 last_pitch = pitch; 546 beeping = last_period = period; 547 callout_reset(&sysbeep_ch, period, sysbeepstop, NULL); 548 } 549 550 int 551 isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p) 552 { 553 int irq; 554 int maybe_irq = -1; 555 int shared_depth = 0; 556 mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */ 557 for (irq = 0; mask != 0; mask >>= 1, irq++) { 558 if ((mask & 1) == 0) 559 continue; 560 if (intrtype[irq] == IST_NONE) { 561 *irq_p = irq; 562 return 0; 563 } 564 /* Level interrupts can be shared */ 565 if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) { 566 struct intrhand *ih = intrhand[irq]; 567 int depth; 568 if (maybe_irq == -1) { 569 maybe_irq = irq; 570 continue; 571 } 572 for (depth = 0; ih != NULL; ih = ih->ih_next) 573 depth++; 574 if (depth < shared_depth) { 575 maybe_irq = irq; 576 shared_depth = depth; 577 } 578 } 579 } 580 if (maybe_irq != -1) { 581 *irq_p = maybe_irq; 582 return 0; 583 } 584 return 1; 585 } 586
Indexes created Tue Sep 23 23:09:58 GMT 2025