isabus.c revision 1.27
1 /* $NetBSD: isabus.c,v 1.27 2005/01/22 07:35:34 tsutsui Exp $ */ 2 /* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */ 3 /* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */ 4 5 /*- 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz and Don Ahn. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)isa.c 7.2 (Berkeley) 5/12/91 37 */ 38 /*- 39 * Copyright (c) 1995 Per Fogelstrom 40 * Copyright (c) 1993, 1994 Charles M. Hannum. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * William Jolitz and Don Ahn. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)isa.c 7.2 (Berkeley) 5/12/91 74 */ 75 /* 76 * Mach Operating System 77 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 78 * All Rights Reserved. 79 * 80 * Permission to use, copy, modify and distribute this software and its 81 * documentation is hereby granted, provided that both the copyright 82 * notice and this permission notice appear in all copies of the 83 * software, derivative works or modified versions, and any portions 84 * thereof, and that both notices appear in supporting documentation. 85 * 86 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 87 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 88 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 89 * 90 * Carnegie Mellon requests users of this software to return to 91 * 92 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 93 * School of Computer Science 94 * Carnegie Mellon University 95 * Pittsburgh PA 15213-3890 96 * 97 * any improvements or extensions that they make and grant Carnegie Mellon 98 * the rights to redistribute these changes. 99 */ 100 /* 101 Copyright 1988, 1989 by Intel Corporation, Santa Clara, California. 102 103 All Rights Reserved 104 105 Permission to use, copy, modify, and distribute this software and 106 its documentation for any purpose and without fee is hereby 107 granted, provided that the above copyright notice appears in all 108 copies and that both the copyright notice and this permission notice 109 appear in supporting documentation, and that the name of Intel 110 not be used in advertising or publicity pertaining to distribution 111 of the software without specific, written prior permission. 112 113 INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 114 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, 115 IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 116 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 117 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 118 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 119 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 120 */ 121 122 #include <sys/cdefs.h> 123 __KERNEL_RCSID(0, "$NetBSD: isabus.c,v 1.27 2005/01/22 07:35:34 tsutsui Exp $"); 124 125 #include <sys/param.h> 126 #include <sys/proc.h> 127 #include <sys/user.h> 128 #include <sys/systm.h> 129 #include <sys/callout.h> 130 #include <sys/time.h> 131 #include <sys/kernel.h> 132 #include <sys/device.h> 133 #include <sys/malloc.h> 134 #include <sys/extent.h> 135 136 #include <uvm/uvm_extern.h> 137 138 #include <machine/cpu.h> 139 #include <machine/pio.h> 140 #include <machine/autoconf.h> 141 #include <machine/intr.h> 142 143 #include <dev/ic/i8253reg.h> 144 #include <dev/isa/isareg.h> 145 #include <dev/isa/isavar.h> 146 #include <arc/isa/isabrvar.h> 147 #include <arc/isa/spkrreg.h> 148 149 static int beeping; 150 static struct callout sysbeep_ch = CALLOUT_INITIALIZER; 151 152 static long isa_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 153 static long isa_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 154 155 #define IRQ_SLAVE 2 156 157 /* Definition of the driver for autoconfig. */ 158 int isabrprint(void *, const char *); 159 160 extern struct arc_bus_space arc_bus_io, arc_bus_mem; 161 162 void isabr_attach_hook(struct device *, struct device *, 163 struct isabus_attach_args *); 164 const struct evcnt *isabr_intr_evcnt(isa_chipset_tag_t, int); 165 void *isabr_intr_establish(isa_chipset_tag_t, int, int, int, 166 int (*)(void *), void *); 167 void isabr_intr_disestablish(isa_chipset_tag_t, void*); 168 int isabr_iointr(unsigned int, struct clockframe *); 169 void isabr_initicu(void); 170 void intr_calculatemasks(void); 171 int fakeintr(void *a); 172 173 struct isabr_config *isabr_conf = NULL; 174 uint32_t imask[_IPL_N]; /* XXX */ 175 176 void 177 isabrattach(struct isabr_softc *sc) 178 { 179 struct isabus_attach_args iba; 180 181 if (isabr_conf == NULL) 182 panic("isabr_conf isn't initialized"); 183 184 printf("\n"); 185 186 /* Initialize interrupt controller */ 187 isabr_initicu(); 188 189 /*XXX we may remove the abus part of the softc struct... */ 190 sc->sc_bus.ab_dv = (struct device *)sc; 191 sc->sc_bus.ab_type = BUS_ISABR; 192 193 sc->arc_isa_cs.ic_attach_hook = isabr_attach_hook; 194 sc->arc_isa_cs.ic_intr_evcnt = isabr_intr_evcnt; 195 sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish; 196 sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish; 197 198 arc_bus_space_init_extent(&arc_bus_mem, (caddr_t)isa_mem_ex_storage, 199 sizeof(isa_mem_ex_storage)); 200 arc_bus_space_init_extent(&arc_bus_io, (caddr_t)isa_io_ex_storage, 201 sizeof(isa_io_ex_storage)); 202 203 iba.iba_iot = &arc_bus_io; 204 iba.iba_memt = &arc_bus_mem; 205 iba.iba_dmat = &sc->sc_dmat; 206 iba.iba_ic = &sc->arc_isa_cs; 207 config_found_ia(&sc->sc_dev, "isabus", &iba, isabrprint); 208 } 209 210 int 211 isabrprint(void *aux, const char *pnp) 212 { 213 214 if (pnp) 215 aprint_normal("isa at %s", pnp); 216 aprint_verbose(" isa_io_base 0x%lx isa_mem_base 0x%lx", 217 arc_bus_io.bs_vbase, arc_bus_mem.bs_vbase); 218 return (UNCONF); 219 } 220 221 222 /* 223 * Interrupt system driver code 224 * ============================ 225 */ 226 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 227 228 int imen; 229 int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN]; 230 struct intrhand *intrhand[ICU_LEN]; 231 232 int fakeintr(void *a) 233 { 234 235 return 0; 236 } 237 238 /* 239 * Recalculate the interrupt masks from scratch. 240 * We could code special registry and deregistry versions of this function that 241 * would be faster, but the code would be nastier, and we don't expect this to 242 * happen very much anyway. 243 */ 244 void 245 intr_calculatemasks(void) 246 { 247 int irq, level; 248 struct intrhand *q; 249 250 /* First, figure out which levels each IRQ uses. */ 251 for (irq = 0; irq < ICU_LEN; irq++) { 252 int levels = 0; 253 for (q = intrhand[irq]; q; q = q->ih_next) 254 levels |= 1 << q->ih_level; 255 intrlevel[irq] = levels; 256 } 257 258 /* Then figure out which IRQs use each level. */ 259 for (level = 0; level < _IPL_N; level++) { 260 int irqs = 0; 261 for (irq = 0; irq < ICU_LEN; irq++) 262 if (intrlevel[irq] & (1 << level)) 263 irqs |= 1 << irq; 264 imask[level] = irqs; 265 } 266 267 imask[IPL_NONE] = 0; 268 269 imask[IPL_SOFT] |= imask[IPL_NONE]; 270 imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 271 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 272 imask[IPL_SOFTSERIAL] |= imask[IPL_SOFTNET]; 273 274 /* 275 * Enforce a hierarchy that gives slow devices a better chance at not 276 * dropping data. 277 */ 278 imask[IPL_BIO] |= imask[IPL_SOFTSERIAL]; 279 imask[IPL_NET] |= imask[IPL_BIO]; 280 imask[IPL_TTY] |= imask[IPL_NET]; 281 282 /* 283 * Since run queues may be manipulated by both the statclock and tty, 284 * network, and diskdrivers, clock > tty. 285 */ 286 imask[IPL_CLOCK] |= imask[IPL_TTY]; 287 imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 288 289 /* 290 * IPL_HIGH must block everything that can manipulate a run queue. 291 */ 292 imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 293 294 /* And eventually calculate the complete masks. */ 295 for (irq = 0; irq < ICU_LEN; irq++) { 296 int irqs = 1 << irq; 297 for (q = intrhand[irq]; q; q = q->ih_next) 298 irqs |= imask[q->ih_level]; 299 intrmask[irq] = irqs; 300 } 301 302 /* Lastly, determine which IRQs are actually in use. */ 303 { 304 int irqs = 0; 305 for (irq = 0; irq < ICU_LEN; irq++) 306 if (intrhand[irq]) 307 irqs |= 1 << irq; 308 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 309 irqs |= 1 << IRQ_SLAVE; 310 imen = ~irqs; 311 isa_outb(IO_ICU1 + 1, imen); 312 isa_outb(IO_ICU2 + 1, imen >> 8); 313 } 314 } 315 316 void 317 isabr_attach_hook(struct device *parent, struct device *self, 318 struct isabus_attach_args *iba) 319 { 320 321 /* Nothing to do. */ 322 } 323 324 const struct evcnt * 325 isabr_intr_evcnt(isa_chipset_tag_t ic, int irq) 326 { 327 328 /* XXX for now, no evcnt parent reported */ 329 return NULL; 330 } 331 332 /* 333 * Establish a ISA bus interrupt. 334 */ 335 void * 336 isabr_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level, 337 int (*ih_fun)(void *), void *ih_arg) 338 { 339 struct intrhand **p, *q, *ih; 340 static struct intrhand fakehand = {NULL, fakeintr}; 341 342 /* no point in sleeping unless someone can free memory. */ 343 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 344 if (ih == NULL) 345 panic("isa_intr_establish: can't malloc handler info"); 346 347 if (!LEGAL_IRQ(irq) || type == IST_NONE) 348 panic("intr_establish: bogus irq or type"); 349 350 switch (intrtype[irq]) { 351 case IST_NONE: 352 intrtype[irq] = type; 353 break; 354 case IST_EDGE: 355 case IST_LEVEL: 356 if (type == intrtype[irq]) 357 break; 358 case IST_PULSE: 359 if (type != IST_NONE) 360 panic("intr_establish: can't share %s with %s", 361 isa_intr_typename(intrtype[irq]), 362 isa_intr_typename(type)); 363 break; 364 } 365 366 /* 367 * Figure out where to put the handler. 368 * This is O(N^2), but we want to preserve the order, and N is 369 * generally small. 370 */ 371 for (p = &intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 372 ; 373 374 /* 375 * Actually install a fake handler momentarily, since we might be doing 376 * this with interrupts enabled and don't want the real routine called 377 * until masking is set up. 378 */ 379 fakehand.ih_level = level; 380 *p = &fakehand; 381 382 intr_calculatemasks(); 383 384 /* 385 * Poke the real handler in now. 386 */ 387 ih->ih_fun = ih_fun; 388 ih->ih_arg = ih_arg; 389 ih->ih_count = 0; 390 ih->ih_next = NULL; 391 ih->ih_level = level; 392 ih->ih_irq = irq; 393 ih->ih_what = ""; /* XXX - should be eliminated */ 394 *p = ih; 395 396 return ih; 397 } 398 399 void 400 isabr_intr_disestablish(isa_chipset_tag_t ic, void *arg) 401 { 402 403 } 404 405 /* 406 * Process an interrupt from the ISA bus. 407 */ 408 int 409 isabr_iointr(unsigned mask, struct clockframe *cf) 410 { 411 struct intrhand *ih; 412 int isa_vector; 413 int o_imen; 414 415 isa_vector = (*isabr_conf->ic_intr_status)(); 416 if (isa_vector < 0) 417 return (~0); 418 419 o_imen = imen; 420 imen |= 1 << (isa_vector & (ICU_LEN - 1)); 421 if (isa_vector & 0x08) { 422 isa_inb(IO_ICU2 + 1); 423 isa_outb(IO_ICU2 + 1, imen >> 8); 424 isa_outb(IO_ICU2, 0x60 + (isa_vector & 7)); 425 isa_outb(IO_ICU1, 0x60 + IRQ_SLAVE); 426 } else { 427 isa_inb(IO_ICU1 + 1); 428 isa_outb(IO_ICU1 + 1, imen); 429 isa_outb(IO_ICU1, 0x60 + isa_vector); 430 } 431 ih = intrhand[isa_vector]; 432 if (isa_vector == 0) { /* Clock */ /*XXX*/ 433 (*ih->ih_fun)(cf); 434 ih = ih->ih_next; 435 } 436 while (ih) { 437 (*ih->ih_fun)(ih->ih_arg); 438 ih = ih->ih_next; 439 } 440 imen = o_imen; 441 isa_inb(IO_ICU1 + 1); 442 isa_inb(IO_ICU2 + 1); 443 isa_outb(IO_ICU1 + 1, imen); 444 isa_outb(IO_ICU2 + 1, imen >> 8); 445 446 return ~0; /* Dont reenable */ 447 } 448 449 450 /* 451 * Initialize the Interrupt controller logic. 452 */ 453 void 454 isabr_initicu(void) 455 { 456 457 int i; 458 459 for (i = 0; i < ICU_LEN; i++) { 460 switch (i) { 461 case 2: 462 case 8: 463 intrtype[i] = IST_EDGE; 464 break; 465 default: 466 intrtype[i] = IST_NONE; 467 break; 468 } 469 } 470 471 isa_outb(IO_ICU1, 0x11); /* reset; program device, four bytes */ 472 isa_outb(IO_ICU1+1, 0); /* starting at this vector index */ 473 isa_outb(IO_ICU1+1, 1 << IRQ_SLAVE); /* slave on line 2 */ 474 isa_outb(IO_ICU1+1, 1); /* 8086 mode */ 475 isa_outb(IO_ICU1+1, 0xff); /* leave interrupts masked */ 476 isa_outb(IO_ICU1, 0x68); /* special mask mode (if available) */ 477 isa_outb(IO_ICU1, 0x0a); /* Read IRR by default. */ 478 #ifdef REORDER_IRQ 479 isa_outb(IO_ICU1, 0xc0 | (3 - 1)); /* pri order 3-7, 0-2 (com2 first) */ 480 #endif 481 482 isa_outb(IO_ICU2, 0x11); /* reset; program device, four bytes */ 483 isa_outb(IO_ICU2+1, 8); /* staring at this vector index */ 484 isa_outb(IO_ICU2+1, IRQ_SLAVE); 485 isa_outb(IO_ICU2+1, 1); /* 8086 mode */ 486 isa_outb(IO_ICU2+1, 0xff); /* leave interrupts masked */ 487 isa_outb(IO_ICU2, 0x68); /* special mask mode (if available) */ 488 isa_outb(IO_ICU2, 0x0a); /* Read IRR by default. */ 489 } 490 491 492 /* 493 * SPEAKER BEEPER... 494 */ 495 void 496 sysbeepstop(void *arg) 497 { 498 int s; 499 500 /* disable counter 2 */ 501 s = splhigh(); 502 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) & ~PIT_SPKR); 503 splx(s); 504 beeping = 0; 505 } 506 507 void 508 sysbeep(int pitch, int period) 509 { 510 static int last_pitch, last_period; 511 int s; 512 513 if (cold) 514 return; /* Can't beep yet. */ 515 516 if (beeping) 517 callout_stop(&sysbeep_ch); 518 if (!beeping || last_pitch != pitch) { 519 s = splhigh(); 520 isa_outb(IO_TIMER1 + TIMER_MODE, 521 TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE); 522 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256); 523 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256); 524 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) | PIT_SPKR); 525 splx(s); 526 } 527 last_pitch = pitch; 528 beeping = last_period = period; 529 callout_reset(&sysbeep_ch, period, sysbeepstop, NULL); 530 } 531 532 int 533 isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p) 534 { 535 int irq; 536 int maybe_irq = -1; 537 int shared_depth = 0; 538 mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */ 539 for (irq = 0; mask != 0; mask >>= 1, irq++) { 540 if ((mask & 1) == 0) 541 continue; 542 if (intrtype[irq] == IST_NONE) { 543 *irq_p = irq; 544 return 0; 545 } 546 /* Level interrupts can be shared */ 547 if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) { 548 struct intrhand *ih = intrhand[irq]; 549 int depth; 550 if (maybe_irq == -1) { 551 maybe_irq = irq; 552 continue; 553 } 554 for (depth = 0; ih != NULL; ih = ih->ih_next) 555 depth++; 556 if (depth < shared_depth) { 557 maybe_irq = irq; 558 shared_depth = depth; 559 } 560 } 561 } 562 if (maybe_irq != -1) { 563 *irq_p = maybe_irq; 564 return 0; 565 } 566 return 1; 567 } 568
Indexes created Fri Sep 26 08:10:20 GMT 2025