isabus.c revision 1.39
1 /* $NetBSD: isabus.c,v 1.39 2007/07/11 19:37:22 he Exp $ */ 2 /* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */ 3 /* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */ 4 5 /*- 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz and Don Ahn. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)isa.c 7.2 (Berkeley) 5/12/91 37 */ 38 /*- 39 * Copyright (c) 1995 Per Fogelstrom 40 * Copyright (c) 1993, 1994 Charles M. Hannum. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * William Jolitz and Don Ahn. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)isa.c 7.2 (Berkeley) 5/12/91 74 */ 75 /* 76 * Mach Operating System 77 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 78 * All Rights Reserved. 79 * 80 * Permission to use, copy, modify and distribute this software and its 81 * documentation is hereby granted, provided that both the copyright 82 * notice and this permission notice appear in all copies of the 83 * software, derivative works or modified versions, and any portions 84 * thereof, and that both notices appear in supporting documentation. 85 * 86 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 87 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 88 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 89 * 90 * Carnegie Mellon requests users of this software to return to 91 * 92 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 93 * School of Computer Science 94 * Carnegie Mellon University 95 * Pittsburgh PA 15213-3890 96 * 97 * any improvements or extensions that they make and grant Carnegie Mellon 98 * the rights to redistribute these changes. 99 */ 100 /* 101 Copyright 1988, 1989 by Intel Corporation, Santa Clara, California. 102 103 All Rights Reserved 104 105 Permission to use, copy, modify, and distribute this software and 106 its documentation for any purpose and without fee is hereby 107 granted, provided that the above copyright notice appears in all 108 copies and that both the copyright notice and this permission notice 109 appear in supporting documentation, and that the name of Intel 110 not be used in advertising or publicity pertaining to distribution 111 of the software without specific, written prior permission. 112 113 INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 114 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, 115 IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 116 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 117 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 118 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 119 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 120 */ 121 122 #include <sys/cdefs.h> 123 __KERNEL_RCSID(0, "$NetBSD: isabus.c,v 1.39 2007/07/11 19:37:22 he Exp $"); 124 125 #include <sys/param.h> 126 #include <sys/proc.h> 127 #include <sys/user.h> 128 #include <sys/systm.h> 129 #include <sys/callout.h> 130 #include <sys/time.h> 131 #include <sys/kernel.h> 132 #include <sys/device.h> 133 #include <sys/malloc.h> 134 #include <sys/extent.h> 135 136 #include <uvm/uvm_extern.h> 137 138 #include <machine/cpu.h> 139 #include <machine/pio.h> 140 #include <machine/autoconf.h> 141 #include <machine/intr.h> 142 143 #include <mips/locore.h> 144 145 #include <dev/ic/i8253reg.h> 146 #include <dev/ic/i8259reg.h> 147 #include <dev/isa/isareg.h> 148 #include <dev/isa/isavar.h> 149 #include <arc/isa/isabrvar.h> 150 #include <arc/isa/spkrreg.h> 151 152 #include <arc/arc/timervar.h> 153 154 static int beeping; 155 static callout_t sysbeep_ch; 156 157 static long isa_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 158 static long isa_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 159 160 #define IRQ_SLAVE 2 161 162 /* Definition of the driver for autoconfig. */ 163 int isabrprint(void *, const char *); 164 165 extern struct arc_bus_space arc_bus_io, arc_bus_mem; 166 167 void isabr_attach_hook(struct device *, struct device *, 168 struct isabus_attach_args *); 169 const struct evcnt *isabr_intr_evcnt(isa_chipset_tag_t, int); 170 void *isabr_intr_establish(isa_chipset_tag_t, int, int, int, 171 int (*)(void *), void *); 172 void isabr_intr_disestablish(isa_chipset_tag_t, void*); 173 uint32_t isabr_iointr(uint32_t, struct clockframe *); 174 void isabr_initicu(void); 175 void intr_calculatemasks(void); 176 int fakeintr(void *a); 177 178 struct isabr_config *isabr_conf = NULL; 179 uint32_t imask[_IPL_N]; /* XXX */ 180 181 void 182 isabrattach(struct isabr_softc *sc) 183 { 184 struct isabus_attach_args iba; 185 186 callout_init(&sysbeep_ch, 0); 187 188 if (isabr_conf == NULL) 189 panic("isabr_conf isn't initialized"); 190 191 printf("\n"); 192 193 /* Initialize interrupt controller */ 194 isabr_initicu(); 195 196 sc->arc_isa_cs.ic_attach_hook = isabr_attach_hook; 197 sc->arc_isa_cs.ic_intr_evcnt = isabr_intr_evcnt; 198 sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish; 199 sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish; 200 201 arc_bus_space_init_extent(&arc_bus_mem, (void *)isa_mem_ex_storage, 202 sizeof(isa_mem_ex_storage)); 203 arc_bus_space_init_extent(&arc_bus_io, (void *)isa_io_ex_storage, 204 sizeof(isa_io_ex_storage)); 205 206 iba.iba_iot = &arc_bus_io; 207 iba.iba_memt = &arc_bus_mem; 208 iba.iba_dmat = &sc->sc_dmat; 209 iba.iba_ic = &sc->arc_isa_cs; 210 config_found_ia(&sc->sc_dev, "isabus", &iba, isabrprint); 211 } 212 213 int 214 isabrprint(void *aux, const char *pnp) 215 { 216 217 if (pnp) 218 aprint_normal("isa at %s", pnp); 219 aprint_verbose(" isa_io_base 0x%lx isa_mem_base 0x%lx", 220 arc_bus_io.bs_vbase, arc_bus_mem.bs_vbase); 221 return (UNCONF); 222 } 223 224 225 /* 226 * Interrupt system driver code 227 * ============================ 228 */ 229 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 230 231 int imen; 232 int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN]; 233 struct isa_intrhand *isa_intrhand[ICU_LEN]; 234 235 int fakeintr(void *a) 236 { 237 238 return 0; 239 } 240 241 /* 242 * Recalculate the interrupt masks from scratch. 243 * We could code special registry and deregistry versions of this function that 244 * would be faster, but the code would be nastier, and we don't expect this to 245 * happen very much anyway. 246 */ 247 void 248 intr_calculatemasks(void) 249 { 250 int irq, level; 251 struct isa_intrhand *q; 252 253 /* First, figure out which levels each IRQ uses. */ 254 for (irq = 0; irq < ICU_LEN; irq++) { 255 int levels = 0; 256 for (q = isa_intrhand[irq]; q; q = q->ih_next) 257 levels |= 1 << q->ih_level; 258 intrlevel[irq] = levels; 259 } 260 261 /* Then figure out which IRQs use each level. */ 262 for (level = 0; level < _IPL_N; level++) { 263 int irqs = 0; 264 for (irq = 0; irq < ICU_LEN; irq++) 265 if (intrlevel[irq] & (1 << level)) 266 irqs |= 1 << irq; 267 imask[level] = irqs; 268 } 269 270 imask[IPL_NONE] = 0; 271 272 imask[IPL_SOFT] |= imask[IPL_NONE]; 273 imask[IPL_SOFTCLOCK] |= imask[IPL_SOFT]; 274 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 275 imask[IPL_SOFTSERIAL] |= imask[IPL_SOFTNET]; 276 277 /* 278 * Enforce a hierarchy that gives slow devices a better chance at not 279 * dropping data. 280 */ 281 imask[IPL_BIO] |= imask[IPL_SOFTSERIAL]; 282 imask[IPL_NET] |= imask[IPL_BIO]; 283 imask[IPL_TTY] |= imask[IPL_NET]; 284 285 /* 286 * Since run queues may be manipulated by both the statclock and tty, 287 * network, and diskdrivers, clock > tty. 288 */ 289 imask[IPL_CLOCK] |= imask[IPL_TTY]; 290 imask[IPL_STATCLOCK] |= imask[IPL_CLOCK]; 291 292 /* 293 * IPL_HIGH must block everything that can manipulate a run queue. 294 */ 295 imask[IPL_HIGH] |= imask[IPL_STATCLOCK]; 296 297 /* And eventually calculate the complete masks. */ 298 for (irq = 0; irq < ICU_LEN; irq++) { 299 int irqs = 1 << irq; 300 for (q = isa_intrhand[irq]; q; q = q->ih_next) 301 irqs |= imask[q->ih_level]; 302 intrmask[irq] = irqs; 303 } 304 305 /* Lastly, determine which IRQs are actually in use. */ 306 { 307 int irqs = 0; 308 for (irq = 0; irq < ICU_LEN; irq++) 309 if (isa_intrhand[irq]) 310 irqs |= 1 << irq; 311 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 312 irqs |= 1 << IRQ_SLAVE; 313 imen = ~irqs; 314 isa_outb(IO_ICU1 + PIC_OCW1, imen); 315 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 316 } 317 } 318 319 void 320 isabr_attach_hook(struct device *parent, struct device *self, 321 struct isabus_attach_args *iba) 322 { 323 324 /* Nothing to do. */ 325 } 326 327 const struct evcnt * 328 isabr_intr_evcnt(isa_chipset_tag_t ic, int irq) 329 { 330 331 /* XXX for now, no evcnt parent reported */ 332 return NULL; 333 } 334 335 /* 336 * Establish a ISA bus interrupt. 337 */ 338 void * 339 isabr_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level, 340 int (*ih_fun)(void *), void *ih_arg) 341 { 342 struct isa_intrhand **p, *q, *ih; 343 static struct isa_intrhand fakehand = {NULL, fakeintr}; 344 345 /* no point in sleeping unless someone can free memory. */ 346 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 347 if (ih == NULL) 348 panic("isa_intr_establish: can't malloc handler info"); 349 350 if (!LEGAL_IRQ(irq) || type == IST_NONE) 351 panic("intr_establish: bogus irq or type"); 352 353 switch (intrtype[irq]) { 354 case IST_NONE: 355 intrtype[irq] = type; 356 break; 357 case IST_EDGE: 358 case IST_LEVEL: 359 if (type == intrtype[irq]) 360 break; 361 case IST_PULSE: 362 if (type != IST_NONE) 363 panic("intr_establish: can't share %s with %s", 364 isa_intr_typename(intrtype[irq]), 365 isa_intr_typename(type)); 366 break; 367 } 368 369 /* 370 * Figure out where to put the handler. 371 * This is O(N^2), but we want to preserve the order, and N is 372 * generally small. 373 */ 374 for (p = &isa_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 375 ; 376 377 /* 378 * Actually install a fake handler momentarily, since we might be doing 379 * this with interrupts enabled and don't want the real routine called 380 * until masking is set up. 381 */ 382 fakehand.ih_level = level; 383 *p = &fakehand; 384 385 intr_calculatemasks(); 386 387 /* 388 * Poke the real handler in now. 389 */ 390 ih->ih_fun = ih_fun; 391 ih->ih_arg = ih_arg; 392 ih->ih_count = 0; 393 ih->ih_next = NULL; 394 ih->ih_level = level; 395 ih->ih_irq = irq; 396 snprintf(ih->ih_evname, sizeof(ih->ih_evname), "irq %d", irq); 397 evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "isa", 398 ih->ih_evname); 399 *p = ih; 400 401 return ih; 402 } 403 404 void 405 isabr_intr_disestablish(isa_chipset_tag_t ic, void *arg) 406 { 407 408 } 409 410 /* 411 * Process an interrupt from the ISA bus. 412 */ 413 uint32_t 414 isabr_iointr(uint32_t mask, struct clockframe *cf) 415 { 416 struct isa_intrhand *ih; 417 int isa_vector; 418 int o_imen; 419 420 isa_vector = (*isabr_conf->ic_intr_status)(); 421 if (isa_vector < 0) 422 return (~0); 423 424 o_imen = imen; 425 imen |= 1 << (isa_vector & (ICU_LEN - 1)); 426 if (isa_vector & 0x08) { 427 isa_inb(IO_ICU2 + PIC_OCW1); 428 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 429 isa_outb(IO_ICU2 + PIC_OCW2, 430 OCW2_SELECT | OCW2_EOI | OCW2_SL | 431 OCW2_ILS((isa_vector & 7))); 432 isa_outb(IO_ICU1, 433 OCW2_SELECT | OCW2_EOI | OCW2_SL | IRQ_SLAVE); 434 } else { 435 isa_inb(IO_ICU1 + PIC_OCW1); 436 isa_outb(IO_ICU1 + PIC_OCW1, imen); 437 isa_outb(IO_ICU1 + PIC_OCW2, 438 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(isa_vector)); 439 } 440 ih = isa_intrhand[isa_vector]; 441 if (isa_vector == 0 && ih) { /* Clock */ /*XXX*/ 442 last_cp0_count = mips3_cp0_count_read(); 443 /* XXX: spllowerclock() not allowed */ 444 cf->sr &= ~MIPS_SR_INT_IE; 445 if ((*ih->ih_fun)(cf)) 446 ih->ih_evcnt.ev_count++; 447 ih = ih->ih_next; 448 } 449 while (ih) { 450 if ((*ih->ih_fun)(ih->ih_arg)) 451 ih->ih_evcnt.ev_count++; 452 ih = ih->ih_next; 453 } 454 imen = o_imen; 455 isa_inb(IO_ICU1 + PIC_OCW1); 456 isa_inb(IO_ICU2 + PIC_OCW1); 457 isa_outb(IO_ICU1 + PIC_OCW1, imen); 458 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 459 460 return ~MIPS_INT_MASK_2; 461 } 462 463 464 /* 465 * Initialize the Interrupt controller logic. 466 */ 467 void 468 isabr_initicu(void) 469 { 470 471 int i; 472 473 for (i = 0; i < ICU_LEN; i++) { 474 switch (i) { 475 case 2: 476 case 8: 477 intrtype[i] = IST_EDGE; 478 break; 479 default: 480 intrtype[i] = IST_NONE; 481 break; 482 } 483 } 484 485 /* reset; program device, four bytes */ 486 isa_outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 487 /* starting at this vector index */ 488 isa_outb(IO_ICU1 + PIC_ICW2, 0); 489 /* slave on line 2 */ 490 isa_outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE)); 491 /* 8086 mode */ 492 isa_outb(IO_ICU1 + PIC_ICW4, ICW4_8086); 493 494 /* leave interrupts masked */ 495 isa_outb(IO_ICU1 + PIC_OCW1, 0xff); 496 497 /* special mask mode (if available) */ 498 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 499 /* Read IRR by default. */ 500 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 501 #ifdef REORDER_IRQ 502 /* pri order 3-7, 0-2 (com2 first) */ 503 isa_outb(IO_ICU1 + PIC_OCW2, 504 OCW2_SELECT | OCW2_R | OCW2_SL OCW2_ILS(3 - 1)); 505 #endif 506 507 /* reset; program device, four bytes */ 508 isa_outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 509 /* staring at this vector index */ 510 isa_outb(IO_ICU2 + PIC_ICW2, 8); 511 /* slave connected to line 2 of master */ 512 isa_outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); 513 /* 8086 mode */ 514 isa_outb(IO_ICU2 + PIC_ICW4, ICW4_8086); 515 516 /* leave interrupts masked */ 517 isa_outb(IO_ICU2 + PIC_OCW1, 0xff); 518 519 /* special mask mode (if available) */ 520 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 521 /* Read IRR by default. */ 522 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 523 } 524 525 526 /* 527 * SPEAKER BEEPER... 528 */ 529 void 530 sysbeepstop(void *arg) 531 { 532 int s; 533 534 /* disable counter 2 */ 535 s = splhigh(); 536 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) & ~PIT_SPKR); 537 splx(s); 538 beeping = 0; 539 } 540 541 void 542 sysbeep(int pitch, int period) 543 { 544 static int last_pitch, last_period; 545 int s; 546 547 if (cold) 548 return; /* Can't beep yet. */ 549 550 if (beeping) 551 callout_stop(&sysbeep_ch); 552 if (!beeping || last_pitch != pitch) { 553 s = splhigh(); 554 isa_outb(IO_TIMER1 + TIMER_MODE, 555 TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE); 556 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256); 557 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256); 558 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) | PIT_SPKR); 559 splx(s); 560 } 561 last_pitch = pitch; 562 beeping = last_period = period; 563 callout_reset(&sysbeep_ch, period, sysbeepstop, NULL); 564 } 565 566 int 567 isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p) 568 { 569 int irq; 570 int maybe_irq = -1; 571 int shared_depth = 0; 572 mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */ 573 for (irq = 0; mask != 0; mask >>= 1, irq++) { 574 if ((mask & 1) == 0) 575 continue; 576 if (intrtype[irq] == IST_NONE) { 577 *irq_p = irq; 578 return 0; 579 } 580 /* Level interrupts can be shared */ 581 if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) { 582 struct isa_intrhand *ih = isa_intrhand[irq]; 583 int depth; 584 if (maybe_irq == -1) { 585 maybe_irq = irq; 586 continue; 587 } 588 for (depth = 0; ih != NULL; ih = ih->ih_next) 589 depth++; 590 if (depth < shared_depth) { 591 maybe_irq = irq; 592 shared_depth = depth; 593 } 594 } 595 } 596 if (maybe_irq != -1) { 597 *irq_p = maybe_irq; 598 return 0; 599 } 600 return 1; 601 } 602
Indexes created Sat Sep 27 14:09:57 GMT 2025