isabus.c revision 1.43.4.2
1 /* $NetBSD: isabus.c,v 1.43.4.2 2009/08/19 18:45:58 yamt Exp $ */ 2 /* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */ 3 /* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */ 4 5 /*- 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz and Don Ahn. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)isa.c 7.2 (Berkeley) 5/12/91 37 */ 38 /*- 39 * Copyright (c) 1995 Per Fogelstrom 40 * Copyright (c) 1993, 1994 Charles M. Hannum. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * William Jolitz and Don Ahn. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)isa.c 7.2 (Berkeley) 5/12/91 74 */ 75 /* 76 * Mach Operating System 77 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 78 * All Rights Reserved. 79 * 80 * Permission to use, copy, modify and distribute this software and its 81 * documentation is hereby granted, provided that both the copyright 82 * notice and this permission notice appear in all copies of the 83 * software, derivative works or modified versions, and any portions 84 * thereof, and that both notices appear in supporting documentation. 85 * 86 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 87 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 88 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 89 * 90 * Carnegie Mellon requests users of this software to return to 91 * 92 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 93 * School of Computer Science 94 * Carnegie Mellon University 95 * Pittsburgh PA 15213-3890 96 * 97 * any improvements or extensions that they make and grant Carnegie Mellon 98 * the rights to redistribute these changes. 99 */ 100 /* 101 Copyright 1988, 1989 by Intel Corporation, Santa Clara, California. 102 103 All Rights Reserved 104 105 Permission to use, copy, modify, and distribute this software and 106 its documentation for any purpose and without fee is hereby 107 granted, provided that the above copyright notice appears in all 108 copies and that both the copyright notice and this permission notice 109 appear in supporting documentation, and that the name of Intel 110 not be used in advertising or publicity pertaining to distribution 111 of the software without specific, written prior permission. 112 113 INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 114 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, 115 IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 116 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 117 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 118 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 119 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 120 */ 121 122 #include <sys/cdefs.h> 123 __KERNEL_RCSID(0, "$NetBSD: isabus.c,v 1.43.4.2 2009/08/19 18:45:58 yamt Exp $"); 124 125 #include <sys/param.h> 126 #include <sys/proc.h> 127 #include <sys/user.h> 128 #include <sys/systm.h> 129 #include <sys/callout.h> 130 #include <sys/time.h> 131 #include <sys/kernel.h> 132 #include <sys/device.h> 133 #include <sys/malloc.h> 134 #include <sys/extent.h> 135 136 #include <uvm/uvm_extern.h> 137 138 #include <machine/cpu.h> 139 #include <machine/pio.h> 140 #include <machine/autoconf.h> 141 #include <machine/intr.h> 142 143 #include <mips/locore.h> 144 145 #include <dev/ic/i8253reg.h> 146 #include <dev/ic/i8259reg.h> 147 #include <dev/isa/isareg.h> 148 #include <dev/isa/isavar.h> 149 #include <arc/isa/isabrvar.h> 150 #include <arc/isa/spkrreg.h> 151 152 #include <arc/arc/timervar.h> 153 154 static int beeping; 155 static callout_t sysbeep_ch; 156 157 static long isa_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 158 static long isa_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 159 160 #define IRQ_SLAVE 2 161 162 /* Definition of the driver for autoconfig. */ 163 static int isabrprint(void *, const char *); 164 165 extern struct arc_bus_space arc_bus_io, arc_bus_mem; 166 167 static void isabr_attach_hook(device_t , device_t, 168 struct isabus_attach_args *); 169 static void isabr_detach_hook(isa_chipset_tag_t, device_t); 170 static const struct evcnt *isabr_intr_evcnt(isa_chipset_tag_t, int); 171 static void *isabr_intr_establish(isa_chipset_tag_t, int, int, int, 172 int (*)(void *), void *); 173 static void isabr_intr_disestablish(isa_chipset_tag_t, void*); 174 static void isabr_initicu(void); 175 static void intr_calculatemasks(void); 176 static int fakeintr(void *a); 177 178 struct isabr_config *isabr_conf = NULL; 179 uint32_t imask[_IPL_N]; /* XXX */ 180 181 void 182 isabrattach(struct isabr_softc *sc) 183 { 184 struct isabus_attach_args iba; 185 186 callout_init(&sysbeep_ch, 0); 187 188 if (isabr_conf == NULL) 189 panic("isabr_conf isn't initialized"); 190 191 aprint_normal("\n"); 192 193 /* Initialize interrupt controller */ 194 isabr_initicu(); 195 196 sc->arc_isa_cs.ic_attach_hook = isabr_attach_hook; 197 sc->arc_isa_cs.ic_detach_hook = isabr_detach_hook; 198 sc->arc_isa_cs.ic_intr_evcnt = isabr_intr_evcnt; 199 sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish; 200 sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish; 201 202 arc_bus_space_init_extent(&arc_bus_mem, (void *)isa_mem_ex_storage, 203 sizeof(isa_mem_ex_storage)); 204 arc_bus_space_init_extent(&arc_bus_io, (void *)isa_io_ex_storage, 205 sizeof(isa_io_ex_storage)); 206 207 iba.iba_iot = &arc_bus_io; 208 iba.iba_memt = &arc_bus_mem; 209 iba.iba_dmat = &sc->sc_dmat; 210 iba.iba_ic = &sc->arc_isa_cs; 211 config_found_ia(sc->sc_dev, "isabus", &iba, isabrprint); 212 } 213 214 static int 215 isabrprint(void *aux, const char *pnp) 216 { 217 218 if (pnp) 219 aprint_normal("isa at %s", pnp); 220 aprint_verbose(" isa_io_base 0x%lx isa_mem_base 0x%lx", 221 arc_bus_io.bs_vbase, arc_bus_mem.bs_vbase); 222 return UNCONF; 223 } 224 225 226 /* 227 * Interrupt system driver code 228 * ============================ 229 */ 230 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 231 232 int imen; 233 int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN]; 234 struct isa_intrhand *isa_intrhand[ICU_LEN]; 235 236 static int 237 fakeintr(void *a) 238 { 239 240 return 0; 241 } 242 243 /* 244 * Recalculate the interrupt masks from scratch. 245 * We could code special registry and deregistry versions of this function that 246 * would be faster, but the code would be nastier, and we don't expect this to 247 * happen very much anyway. 248 */ 249 static void 250 intr_calculatemasks(void) 251 { 252 int irq, level; 253 struct isa_intrhand *q; 254 255 /* First, figure out which levels each IRQ uses. */ 256 for (irq = 0; irq < ICU_LEN; irq++) { 257 int levels = 0; 258 for (q = isa_intrhand[irq]; q; q = q->ih_next) 259 levels |= 1 << q->ih_level; 260 intrlevel[irq] = levels; 261 } 262 263 /* Then figure out which IRQs use each level. */ 264 for (level = 0; level < _IPL_N; level++) { 265 int irqs = 0; 266 for (irq = 0; irq < ICU_LEN; irq++) 267 if (intrlevel[irq] & (1 << level)) 268 irqs |= 1 << irq; 269 imask[level] = irqs; 270 } 271 272 imask[IPL_NONE] = 0; 273 274 imask[IPL_SOFTCLOCK] |= imask[IPL_NONE]; 275 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 276 277 /* 278 * Enforce a hierarchy that gives slow devices a better chance at not 279 * dropping data. 280 */ 281 imask[IPL_VM] |= imask[IPL_SOFTNET]; 282 283 /* 284 * Since run queues may be manipulated by both the statclock and tty, 285 * network, and diskdrivers, clock > tty. 286 */ 287 imask[IPL_SCHED] |= imask[IPL_VM]; 288 289 /* And eventually calculate the complete masks. */ 290 for (irq = 0; irq < ICU_LEN; irq++) { 291 int irqs = 1 << irq; 292 for (q = isa_intrhand[irq]; q; q = q->ih_next) 293 irqs |= imask[q->ih_level]; 294 intrmask[irq] = irqs; 295 } 296 297 /* Lastly, determine which IRQs are actually in use. */ 298 { 299 int irqs = 0; 300 for (irq = 0; irq < ICU_LEN; irq++) 301 if (isa_intrhand[irq]) 302 irqs |= 1 << irq; 303 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 304 irqs |= 1 << IRQ_SLAVE; 305 imen = ~irqs; 306 isa_outb(IO_ICU1 + PIC_OCW1, imen); 307 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 308 } 309 } 310 311 static void 312 isabr_attach_hook(struct device *parent, struct device *self, 313 struct isabus_attach_args *iba) 314 { 315 316 /* Nothing to do. */ 317 } 318 319 static void 320 isabr_detach_hook(isa_chipset_tag_t ic, device_t self) 321 { 322 323 /* Nothing to do. */ 324 } 325 326 static const struct evcnt * 327 isabr_intr_evcnt(isa_chipset_tag_t ic, int irq) 328 { 329 330 /* XXX for now, no evcnt parent reported */ 331 return NULL; 332 } 333 334 /* 335 * Establish a ISA bus interrupt. 336 */ 337 static void * 338 isabr_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level, 339 int (*ih_fun)(void *), void *ih_arg) 340 { 341 struct isa_intrhand **p, *q, *ih; 342 static struct isa_intrhand fakehand = {NULL, fakeintr}; 343 344 /* no point in sleeping unless someone can free memory. */ 345 ih = malloc(sizeof *ih, M_DEVBUF, cold ? M_NOWAIT : M_WAITOK); 346 if (ih == NULL) 347 panic("isa_intr_establish: can't malloc handler info"); 348 349 if (!LEGAL_IRQ(irq) || type == IST_NONE) 350 panic("intr_establish: bogus irq or type"); 351 352 switch (intrtype[irq]) { 353 case IST_NONE: 354 intrtype[irq] = type; 355 break; 356 case IST_EDGE: 357 case IST_LEVEL: 358 if (type == intrtype[irq]) 359 break; 360 case IST_PULSE: 361 if (type != IST_NONE) 362 panic("intr_establish: can't share %s with %s", 363 isa_intr_typename(intrtype[irq]), 364 isa_intr_typename(type)); 365 break; 366 } 367 368 /* 369 * Figure out where to put the handler. 370 * This is O(N^2), but we want to preserve the order, and N is 371 * generally small. 372 */ 373 for (p = &isa_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 374 ; 375 376 /* 377 * Actually install a fake handler momentarily, since we might be doing 378 * this with interrupts enabled and don't want the real routine called 379 * until masking is set up. 380 */ 381 fakehand.ih_level = level; 382 *p = &fakehand; 383 384 intr_calculatemasks(); 385 386 /* 387 * Poke the real handler in now. 388 */ 389 ih->ih_fun = ih_fun; 390 ih->ih_arg = ih_arg; 391 ih->ih_count = 0; 392 ih->ih_next = NULL; 393 ih->ih_level = level; 394 ih->ih_irq = irq; 395 snprintf(ih->ih_evname, sizeof(ih->ih_evname), "irq %d", irq); 396 evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "isa", 397 ih->ih_evname); 398 *p = ih; 399 400 return ih; 401 } 402 403 static void 404 isabr_intr_disestablish(isa_chipset_tag_t ic, void *arg) 405 { 406 407 } 408 409 /* 410 * Process an interrupt from the ISA bus. 411 */ 412 uint32_t 413 isabr_iointr(uint32_t mask, struct clockframe *cf) 414 { 415 struct isa_intrhand *ih; 416 int isa_vector; 417 int o_imen; 418 419 isa_vector = (*isabr_conf->ic_intr_status)(); 420 if (isa_vector < 0) 421 return 0; 422 423 o_imen = imen; 424 imen |= 1 << (isa_vector & (ICU_LEN - 1)); 425 if (isa_vector & 0x08) { 426 isa_inb(IO_ICU2 + PIC_OCW1); 427 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 428 isa_outb(IO_ICU2 + PIC_OCW2, 429 OCW2_SELECT | OCW2_EOI | OCW2_SL | 430 OCW2_ILS((isa_vector & 7))); 431 isa_outb(IO_ICU1, 432 OCW2_SELECT | OCW2_EOI | OCW2_SL | IRQ_SLAVE); 433 } else { 434 isa_inb(IO_ICU1 + PIC_OCW1); 435 isa_outb(IO_ICU1 + PIC_OCW1, imen); 436 isa_outb(IO_ICU1 + PIC_OCW2, 437 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(isa_vector)); 438 } 439 ih = isa_intrhand[isa_vector]; 440 if (isa_vector == 0 && ih) { /* Clock */ /*XXX*/ 441 last_cp0_count = mips3_cp0_count_read(); 442 /* XXX: spllowerclock() not allowed */ 443 cf->sr &= ~MIPS_SR_INT_IE; 444 if ((*ih->ih_fun)(cf)) 445 ih->ih_evcnt.ev_count++; 446 ih = ih->ih_next; 447 } 448 while (ih) { 449 if ((*ih->ih_fun)(ih->ih_arg)) 450 ih->ih_evcnt.ev_count++; 451 ih = ih->ih_next; 452 } 453 imen = o_imen; 454 isa_inb(IO_ICU1 + PIC_OCW1); 455 isa_inb(IO_ICU2 + PIC_OCW1); 456 isa_outb(IO_ICU1 + PIC_OCW1, imen); 457 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 458 459 return MIPS_INT_MASK_2; 460 } 461 462 463 /* 464 * Initialize the Interrupt controller logic. 465 */ 466 static void 467 isabr_initicu(void) 468 { 469 470 int i; 471 472 for (i = 0; i < ICU_LEN; i++) { 473 switch (i) { 474 case 2: 475 case 8: 476 intrtype[i] = IST_EDGE; 477 break; 478 default: 479 intrtype[i] = IST_NONE; 480 break; 481 } 482 } 483 484 /* reset; program device, four bytes */ 485 isa_outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 486 /* starting at this vector index */ 487 isa_outb(IO_ICU1 + PIC_ICW2, 0); 488 /* slave on line 2 */ 489 isa_outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE)); 490 /* 8086 mode */ 491 isa_outb(IO_ICU1 + PIC_ICW4, ICW4_8086); 492 493 /* leave interrupts masked */ 494 isa_outb(IO_ICU1 + PIC_OCW1, 0xff); 495 496 /* special mask mode (if available) */ 497 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 498 /* Read IRR by default. */ 499 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 500 #ifdef REORDER_IRQ 501 /* pri order 3-7, 0-2 (com2 first) */ 502 isa_outb(IO_ICU1 + PIC_OCW2, 503 OCW2_SELECT | OCW2_R | OCW2_SL OCW2_ILS(3 - 1)); 504 #endif 505 506 /* reset; program device, four bytes */ 507 isa_outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 508 /* staring at this vector index */ 509 isa_outb(IO_ICU2 + PIC_ICW2, 8); 510 /* slave connected to line 2 of master */ 511 isa_outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); 512 /* 8086 mode */ 513 isa_outb(IO_ICU2 + PIC_ICW4, ICW4_8086); 514 515 /* leave interrupts masked */ 516 isa_outb(IO_ICU2 + PIC_OCW1, 0xff); 517 518 /* special mask mode (if available) */ 519 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 520 /* Read IRR by default. */ 521 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 522 } 523 524 525 /* 526 * SPEAKER BEEPER... 527 */ 528 void 529 sysbeepstop(void *arg) 530 { 531 int s; 532 533 /* disable counter 2 */ 534 s = splhigh(); 535 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) & ~PIT_SPKR); 536 splx(s); 537 beeping = 0; 538 } 539 540 void 541 sysbeep(int pitch, int period) 542 { 543 static int last_pitch, last_period; 544 int s; 545 546 if (cold) 547 return; /* Can't beep yet. */ 548 549 if (beeping) 550 callout_stop(&sysbeep_ch); 551 if (!beeping || last_pitch != pitch) { 552 s = splhigh(); 553 isa_outb(IO_TIMER1 + TIMER_MODE, 554 TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE); 555 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256); 556 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256); 557 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) | PIT_SPKR); 558 splx(s); 559 } 560 last_pitch = pitch; 561 beeping = last_period = period; 562 callout_reset(&sysbeep_ch, period, sysbeepstop, NULL); 563 } 564 565 int 566 isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p) 567 { 568 int irq; 569 int maybe_irq = -1; 570 int shared_depth = 0; 571 mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */ 572 for (irq = 0; mask != 0; mask >>= 1, irq++) { 573 if ((mask & 1) == 0) 574 continue; 575 if (intrtype[irq] == IST_NONE) { 576 *irq_p = irq; 577 return 0; 578 } 579 /* Level interrupts can be shared */ 580 if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) { 581 struct isa_intrhand *ih = isa_intrhand[irq]; 582 int depth; 583 if (maybe_irq == -1) { 584 maybe_irq = irq; 585 continue; 586 } 587 for (depth = 0; ih != NULL; ih = ih->ih_next) 588 depth++; 589 if (depth < shared_depth) { 590 maybe_irq = irq; 591 shared_depth = depth; 592 } 593 } 594 } 595 if (maybe_irq != -1) { 596 *irq_p = maybe_irq; 597 return 0; 598 } 599 return 1; 600 } 601
Indexes created Wed Oct 15 16:09:53 GMT 2025