isabus.c revision 1.52
1 /* $NetBSD: isabus.c,v 1.52 2021/04/24 23:36:25 thorpej Exp $ */ 2 /* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */ 3 /* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */ 4 5 /*- 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz and Don Ahn. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)isa.c 7.2 (Berkeley) 5/12/91 37 */ 38 /*- 39 * Copyright (c) 1995 Per Fogelstrom 40 * Copyright (c) 1993, 1994 Charles M. Hannum. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * William Jolitz and Don Ahn. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)isa.c 7.2 (Berkeley) 5/12/91 74 */ 75 /* 76 * Mach Operating System 77 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 78 * All Rights Reserved. 79 * 80 * Permission to use, copy, modify and distribute this software and its 81 * documentation is hereby granted, provided that both the copyright 82 * notice and this permission notice appear in all copies of the 83 * software, derivative works or modified versions, and any portions 84 * thereof, and that both notices appear in supporting documentation. 85 * 86 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 87 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 88 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 89 * 90 * Carnegie Mellon requests users of this software to return to 91 * 92 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 93 * School of Computer Science 94 * Carnegie Mellon University 95 * Pittsburgh PA 15213-3890 96 * 97 * any improvements or extensions that they make and grant Carnegie Mellon 98 * the rights to redistribute these changes. 99 */ 100 /* 101 Copyright 1988, 1989 by Intel Corporation, Santa Clara, California. 102 103 All Rights Reserved 104 105 Permission to use, copy, modify, and distribute this software and 106 its documentation for any purpose and without fee is hereby 107 granted, provided that the above copyright notice appears in all 108 copies and that both the copyright notice and this permission notice 109 appear in supporting documentation, and that the name of Intel 110 not be used in advertising or publicity pertaining to distribution 111 of the software without specific, written prior permission. 112 113 INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 114 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, 115 IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 116 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 117 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 118 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 119 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 120 */ 121 122 #include <sys/cdefs.h> 123 __KERNEL_RCSID(0, "$NetBSD: isabus.c,v 1.52 2021/04/24 23:36:25 thorpej Exp $"); 124 125 #include <sys/param.h> 126 #include <sys/proc.h> 127 #include <sys/systm.h> 128 #include <sys/callout.h> 129 #include <sys/time.h> 130 #include <sys/kernel.h> 131 #include <sys/device.h> 132 #include <sys/kmem.h> 133 #include <sys/extent.h> 134 135 #include <uvm/uvm_extern.h> 136 137 #include <machine/cpu.h> 138 #include <machine/pio.h> 139 #include <machine/autoconf.h> 140 #include <machine/intr.h> 141 142 #include <mips/locore.h> 143 144 #include <dev/ic/i8253reg.h> 145 #include <dev/ic/i8259reg.h> 146 #include <dev/isa/isareg.h> 147 #include <dev/isa/isavar.h> 148 #include <arc/isa/isabrvar.h> 149 #include <arc/isa/spkrreg.h> 150 151 #include <arc/arc/timervar.h> 152 153 static int beeping; 154 static callout_t sysbeep_ch; 155 156 static long isa_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 157 static long isa_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 158 159 #define IRQ_SLAVE 2 160 161 /* Definition of the driver for autoconfig. */ 162 static int isabrprint(void *, const char *); 163 164 extern struct arc_bus_space arc_bus_io, arc_bus_mem; 165 166 static void isabr_attach_hook(device_t , device_t, 167 struct isabus_attach_args *); 168 static void isabr_detach_hook(isa_chipset_tag_t, device_t); 169 static const struct evcnt *isabr_intr_evcnt(isa_chipset_tag_t, int); 170 static void *isabr_intr_establish(isa_chipset_tag_t, int, int, int, 171 int (*)(void *), void *); 172 static void isabr_intr_disestablish(isa_chipset_tag_t, void*); 173 static void isabr_initicu(void); 174 static void intr_calculatemasks(void); 175 static int fakeintr(void *a); 176 177 struct isabr_config *isabr_conf = NULL; 178 uint32_t imask[_IPL_N]; /* XXX */ 179 180 void 181 isabrattach(struct isabr_softc *sc) 182 { 183 struct isabus_attach_args iba; 184 185 callout_init(&sysbeep_ch, 0); 186 187 if (isabr_conf == NULL) 188 panic("isabr_conf isn't initialized"); 189 190 aprint_normal("\n"); 191 192 /* Initialize interrupt controller */ 193 isabr_initicu(); 194 195 sc->arc_isa_cs.ic_attach_hook = isabr_attach_hook; 196 sc->arc_isa_cs.ic_detach_hook = isabr_detach_hook; 197 sc->arc_isa_cs.ic_intr_evcnt = isabr_intr_evcnt; 198 sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish; 199 sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish; 200 201 arc_bus_space_init_extent(&arc_bus_mem, (void *)isa_mem_ex_storage, 202 sizeof(isa_mem_ex_storage)); 203 arc_bus_space_init_extent(&arc_bus_io, (void *)isa_io_ex_storage, 204 sizeof(isa_io_ex_storage)); 205 206 iba.iba_iot = &arc_bus_io; 207 iba.iba_memt = &arc_bus_mem; 208 iba.iba_dmat = &sc->sc_dmat; 209 iba.iba_ic = &sc->arc_isa_cs; 210 config_found(sc->sc_dev, &iba, isabrprint, 211 CFARG_IATTR, "isabus", 212 CFARG_EOL); 213 } 214 215 static int 216 isabrprint(void *aux, const char *pnp) 217 { 218 219 if (pnp) 220 aprint_normal("isa at %s", pnp); 221 aprint_verbose(" isa_io_base 0x%"PRIxVADDR" isa_mem_base 0x%"PRIxVADDR, 222 arc_bus_io.bs_vbase, arc_bus_mem.bs_vbase); 223 return UNCONF; 224 } 225 226 227 /* 228 * Interrupt system driver code 229 * ============================ 230 */ 231 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 232 233 int imen; 234 int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN]; 235 struct isa_intrhand *isa_intrhand[ICU_LEN]; 236 237 static int 238 fakeintr(void *a) 239 { 240 241 return 0; 242 } 243 244 /* 245 * Recalculate the interrupt masks from scratch. 246 * We could code special registry and deregistry versions of this function that 247 * would be faster, but the code would be nastier, and we don't expect this to 248 * happen very much anyway. 249 */ 250 static void 251 intr_calculatemasks(void) 252 { 253 int irq, level; 254 struct isa_intrhand *q; 255 256 /* First, figure out which levels each IRQ uses. */ 257 for (irq = 0; irq < ICU_LEN; irq++) { 258 int levels = 0; 259 for (q = isa_intrhand[irq]; q; q = q->ih_next) 260 levels |= 1 << q->ih_level; 261 intrlevel[irq] = levels; 262 } 263 264 /* Then figure out which IRQs use each level. */ 265 for (level = 0; level < _IPL_N; level++) { 266 int irqs = 0; 267 for (irq = 0; irq < ICU_LEN; irq++) 268 if (intrlevel[irq] & (1 << level)) 269 irqs |= 1 << irq; 270 imask[level] = irqs; 271 } 272 273 imask[IPL_NONE] = 0; 274 275 imask[IPL_SOFTCLOCK] |= imask[IPL_NONE]; 276 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 277 278 /* 279 * Enforce a hierarchy that gives slow devices a better chance at not 280 * dropping data. 281 */ 282 imask[IPL_VM] |= imask[IPL_SOFTNET]; 283 284 /* 285 * Since run queues may be manipulated by both the statclock and tty, 286 * network, and diskdrivers, clock > tty. 287 */ 288 imask[IPL_SCHED] |= imask[IPL_VM]; 289 290 /* And eventually calculate the complete masks. */ 291 for (irq = 0; irq < ICU_LEN; irq++) { 292 int irqs = 1 << irq; 293 for (q = isa_intrhand[irq]; q; q = q->ih_next) 294 irqs |= imask[q->ih_level]; 295 intrmask[irq] = irqs; 296 } 297 298 /* Lastly, determine which IRQs are actually in use. */ 299 { 300 int irqs = 0; 301 for (irq = 0; irq < ICU_LEN; irq++) 302 if (isa_intrhand[irq]) 303 irqs |= 1 << irq; 304 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 305 irqs |= 1 << IRQ_SLAVE; 306 imen = ~irqs; 307 isa_outb(IO_ICU1 + PIC_OCW1, imen); 308 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 309 } 310 } 311 312 static void 313 isabr_attach_hook(device_t parent, device_t self, 314 struct isabus_attach_args *iba) 315 { 316 317 /* Nothing to do. */ 318 } 319 320 static void 321 isabr_detach_hook(isa_chipset_tag_t ic, device_t self) 322 { 323 324 /* Nothing to do. */ 325 } 326 327 static const struct evcnt * 328 isabr_intr_evcnt(isa_chipset_tag_t ic, int irq) 329 { 330 331 /* XXX for now, no evcnt parent reported */ 332 return NULL; 333 } 334 335 /* 336 * Establish a ISA bus interrupt. 337 */ 338 static void * 339 isabr_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level, 340 int (*ih_fun)(void *), void *ih_arg) 341 { 342 struct isa_intrhand **p, *q, *ih; 343 static struct isa_intrhand fakehand = {NULL, fakeintr}; 344 345 ih = kmem_alloc(sizeof *ih, KM_SLEEP); 346 347 if (!LEGAL_IRQ(irq) || type == IST_NONE) 348 panic("intr_establish: bogus irq or type"); 349 350 switch (intrtype[irq]) { 351 case IST_NONE: 352 intrtype[irq] = type; 353 break; 354 case IST_EDGE: 355 case IST_LEVEL: 356 if (type == intrtype[irq]) 357 break; 358 case IST_PULSE: 359 if (type != IST_NONE) 360 panic("intr_establish: can't share %s with %s", 361 isa_intr_typename(intrtype[irq]), 362 isa_intr_typename(type)); 363 break; 364 } 365 366 /* 367 * Figure out where to put the handler. 368 * This is O(N^2), but we want to preserve the order, and N is 369 * generally small. 370 */ 371 for (p = &isa_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 372 ; 373 374 /* 375 * Actually install a fake handler momentarily, since we might be doing 376 * this with interrupts enabled and don't want the real routine called 377 * until masking is set up. 378 */ 379 fakehand.ih_level = level; 380 *p = &fakehand; 381 382 intr_calculatemasks(); 383 384 /* 385 * Poke the real handler in now. 386 */ 387 ih->ih_fun = ih_fun; 388 ih->ih_arg = ih_arg; 389 ih->ih_count = 0; 390 ih->ih_next = NULL; 391 ih->ih_level = level; 392 ih->ih_irq = irq; 393 snprintf(ih->ih_evname, sizeof(ih->ih_evname), "irq %d", irq); 394 evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "isa", 395 ih->ih_evname); 396 *p = ih; 397 398 return ih; 399 } 400 401 static void 402 isabr_intr_disestablish(isa_chipset_tag_t ic, void *arg) 403 { 404 405 } 406 407 /* 408 * Process an interrupt from the ISA bus. 409 */ 410 uint32_t 411 isabr_iointr(uint32_t mask, struct clockframe *cf) 412 { 413 struct isa_intrhand *ih; 414 int isa_vector; 415 int o_imen; 416 417 isa_vector = (*isabr_conf->ic_intr_status)(); 418 if (isa_vector < 0) 419 return 0; 420 421 o_imen = imen; 422 imen |= 1 << (isa_vector & (ICU_LEN - 1)); 423 if (isa_vector & 0x08) { 424 isa_inb(IO_ICU2 + PIC_OCW1); 425 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 426 isa_outb(IO_ICU2 + PIC_OCW2, 427 OCW2_SELECT | OCW2_EOI | OCW2_SL | 428 OCW2_ILS((isa_vector & 7))); 429 isa_outb(IO_ICU1, 430 OCW2_SELECT | OCW2_EOI | OCW2_SL | IRQ_SLAVE); 431 } else { 432 isa_inb(IO_ICU1 + PIC_OCW1); 433 isa_outb(IO_ICU1 + PIC_OCW1, imen); 434 isa_outb(IO_ICU1 + PIC_OCW2, 435 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(isa_vector)); 436 } 437 ih = isa_intrhand[isa_vector]; 438 if (isa_vector == 0 && ih) { /* Clock */ /*XXX*/ 439 last_cp0_count = mips3_cp0_count_read(); 440 /* XXX: spllowerclock() not allowed */ 441 cf->sr &= ~MIPS_SR_INT_IE; 442 if ((*ih->ih_fun)(cf)) 443 ih->ih_evcnt.ev_count++; 444 ih = ih->ih_next; 445 } 446 while (ih) { 447 if ((*ih->ih_fun)(ih->ih_arg)) 448 ih->ih_evcnt.ev_count++; 449 ih = ih->ih_next; 450 } 451 imen = o_imen; 452 isa_inb(IO_ICU1 + PIC_OCW1); 453 isa_inb(IO_ICU2 + PIC_OCW1); 454 isa_outb(IO_ICU1 + PIC_OCW1, imen); 455 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 456 457 return MIPS_INT_MASK_2; 458 } 459 460 461 /* 462 * Initialize the Interrupt controller logic. 463 */ 464 static void 465 isabr_initicu(void) 466 { 467 468 int i; 469 470 for (i = 0; i < ICU_LEN; i++) { 471 switch (i) { 472 case 2: 473 case 8: 474 intrtype[i] = IST_EDGE; 475 break; 476 default: 477 intrtype[i] = IST_NONE; 478 break; 479 } 480 } 481 482 /* reset; program device, four bytes */ 483 isa_outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 484 /* starting at this vector index */ 485 isa_outb(IO_ICU1 + PIC_ICW2, 0); 486 /* slave on line 2 */ 487 isa_outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE)); 488 /* 8086 mode */ 489 isa_outb(IO_ICU1 + PIC_ICW4, ICW4_8086); 490 491 /* leave interrupts masked */ 492 isa_outb(IO_ICU1 + PIC_OCW1, 0xff); 493 494 /* special mask mode (if available) */ 495 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 496 /* Read IRR by default. */ 497 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 498 #ifdef REORDER_IRQ 499 /* pri order 3-7, 0-2 (com2 first) */ 500 isa_outb(IO_ICU1 + PIC_OCW2, 501 OCW2_SELECT | OCW2_R | OCW2_SL OCW2_ILS(3 - 1)); 502 #endif 503 504 /* reset; program device, four bytes */ 505 isa_outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 506 /* staring at this vector index */ 507 isa_outb(IO_ICU2 + PIC_ICW2, 8); 508 /* slave connected to line 2 of master */ 509 isa_outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); 510 /* 8086 mode */ 511 isa_outb(IO_ICU2 + PIC_ICW4, ICW4_8086); 512 513 /* leave interrupts masked */ 514 isa_outb(IO_ICU2 + PIC_OCW1, 0xff); 515 516 /* special mask mode (if available) */ 517 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 518 /* Read IRR by default. */ 519 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 520 } 521 522 523 /* 524 * SPEAKER BEEPER... 525 */ 526 void 527 sysbeepstop(void *arg) 528 { 529 int s; 530 531 /* disable counter 2 */ 532 s = splhigh(); 533 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) & ~PIT_SPKR); 534 splx(s); 535 beeping = 0; 536 } 537 538 void 539 sysbeep(int pitch, int period) 540 { 541 static int last_pitch, last_period; 542 int s; 543 544 if (cold) 545 return; /* Can't beep yet. */ 546 547 if (beeping) 548 callout_stop(&sysbeep_ch); 549 if (!beeping || last_pitch != pitch) { 550 s = splhigh(); 551 isa_outb(IO_TIMER1 + TIMER_MODE, 552 TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE); 553 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256); 554 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256); 555 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) | PIT_SPKR); 556 splx(s); 557 } 558 last_pitch = pitch; 559 beeping = last_period = period; 560 callout_reset(&sysbeep_ch, period, sysbeepstop, NULL); 561 } 562 563 int 564 isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p) 565 { 566 int irq; 567 int maybe_irq = -1; 568 int shared_depth = 0; 569 mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */ 570 for (irq = 0; mask != 0; mask >>= 1, irq++) { 571 if ((mask & 1) == 0) 572 continue; 573 if (intrtype[irq] == IST_NONE) { 574 *irq_p = irq; 575 return 0; 576 } 577 /* Level interrupts can be shared */ 578 if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) { 579 struct isa_intrhand *ih = isa_intrhand[irq]; 580 int depth; 581 if (maybe_irq == -1) { 582 maybe_irq = irq; 583 continue; 584 } 585 for (depth = 0; ih != NULL; ih = ih->ih_next) 586 depth++; 587 if (depth < shared_depth) { 588 maybe_irq = irq; 589 shared_depth = depth; 590 } 591 } 592 } 593 if (maybe_irq != -1) { 594 *irq_p = maybe_irq; 595 return 0; 596 } 597 return 1; 598 } 599
Indexes created Tue Sep 23 20:09:58 GMT 2025