isabus.c revision 1.53
1 /* $NetBSD: isabus.c,v 1.53 2021/08/07 16:18:42 thorpej Exp $ */ 2 /* $OpenBSD: isabus.c,v 1.15 1998/03/16 09:38:46 pefo Exp $ */ 3 /* NetBSD: isa.c,v 1.33 1995/06/28 04:30:51 cgd Exp */ 4 5 /*- 6 * Copyright (c) 1990 The Regents of the University of California. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to Berkeley by 10 * William Jolitz and Don Ahn. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * @(#)isa.c 7.2 (Berkeley) 5/12/91 37 */ 38 /*- 39 * Copyright (c) 1995 Per Fogelstrom 40 * Copyright (c) 1993, 1994 Charles M. Hannum. 41 * 42 * This code is derived from software contributed to Berkeley by 43 * William Jolitz and Don Ahn. 44 * 45 * Redistribution and use in source and binary forms, with or without 46 * modification, are permitted provided that the following conditions 47 * are met: 48 * 1. Redistributions of source code must retain the above copyright 49 * notice, this list of conditions and the following disclaimer. 50 * 2. Redistributions in binary form must reproduce the above copyright 51 * notice, this list of conditions and the following disclaimer in the 52 * documentation and/or other materials provided with the distribution. 53 * 3. All advertising materials mentioning features or use of this software 54 * must display the following acknowledgement: 55 * This product includes software developed by the University of 56 * California, Berkeley and its contributors. 57 * 4. Neither the name of the University nor the names of its contributors 58 * may be used to endorse or promote products derived from this software 59 * without specific prior written permission. 60 * 61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 71 * SUCH DAMAGE. 72 * 73 * @(#)isa.c 7.2 (Berkeley) 5/12/91 74 */ 75 /* 76 * Mach Operating System 77 * Copyright (c) 1991,1990,1989 Carnegie Mellon University 78 * All Rights Reserved. 79 * 80 * Permission to use, copy, modify and distribute this software and its 81 * documentation is hereby granted, provided that both the copyright 82 * notice and this permission notice appear in all copies of the 83 * software, derivative works or modified versions, and any portions 84 * thereof, and that both notices appear in supporting documentation. 85 * 86 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 87 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND FOR 88 * ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 89 * 90 * Carnegie Mellon requests users of this software to return to 91 * 92 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 93 * School of Computer Science 94 * Carnegie Mellon University 95 * Pittsburgh PA 15213-3890 96 * 97 * any improvements or extensions that they make and grant Carnegie Mellon 98 * the rights to redistribute these changes. 99 */ 100 /* 101 Copyright 1988, 1989 by Intel Corporation, Santa Clara, California. 102 103 All Rights Reserved 104 105 Permission to use, copy, modify, and distribute this software and 106 its documentation for any purpose and without fee is hereby 107 granted, provided that the above copyright notice appears in all 108 copies and that both the copyright notice and this permission notice 109 appear in supporting documentation, and that the name of Intel 110 not be used in advertising or publicity pertaining to distribution 111 of the software without specific, written prior permission. 112 113 INTEL DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE 114 INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, 115 IN NO EVENT SHALL INTEL BE LIABLE FOR ANY SPECIAL, INDIRECT, OR 116 CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM 117 LOSS OF USE, DATA OR PROFITS, WHETHER IN ACTION OF CONTRACT, 118 NEGLIGENCE, OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION 119 WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 120 */ 121 122 #include <sys/cdefs.h> 123 __KERNEL_RCSID(0, "$NetBSD: isabus.c,v 1.53 2021/08/07 16:18:42 thorpej Exp $"); 124 125 #include <sys/param.h> 126 #include <sys/proc.h> 127 #include <sys/systm.h> 128 #include <sys/callout.h> 129 #include <sys/time.h> 130 #include <sys/kernel.h> 131 #include <sys/device.h> 132 #include <sys/kmem.h> 133 #include <sys/extent.h> 134 135 #include <uvm/uvm_extern.h> 136 137 #include <machine/cpu.h> 138 #include <machine/pio.h> 139 #include <machine/autoconf.h> 140 #include <machine/intr.h> 141 142 #include <mips/locore.h> 143 144 #include <dev/ic/i8253reg.h> 145 #include <dev/ic/i8259reg.h> 146 #include <dev/isa/isareg.h> 147 #include <dev/isa/isavar.h> 148 #include <arc/isa/isabrvar.h> 149 #include <arc/isa/spkrreg.h> 150 151 #include <arc/arc/timervar.h> 152 153 static int beeping; 154 static callout_t sysbeep_ch; 155 156 static long isa_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 157 static long isa_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(16) / sizeof(long)]; 158 159 #define IRQ_SLAVE 2 160 161 /* Definition of the driver for autoconfig. */ 162 static int isabrprint(void *, const char *); 163 164 extern struct arc_bus_space arc_bus_io, arc_bus_mem; 165 166 static void isabr_attach_hook(device_t , device_t, 167 struct isabus_attach_args *); 168 static void isabr_detach_hook(isa_chipset_tag_t, device_t); 169 static const struct evcnt *isabr_intr_evcnt(isa_chipset_tag_t, int); 170 static void *isabr_intr_establish(isa_chipset_tag_t, int, int, int, 171 int (*)(void *), void *); 172 static void isabr_intr_disestablish(isa_chipset_tag_t, void*); 173 static void isabr_initicu(void); 174 static void intr_calculatemasks(void); 175 static int fakeintr(void *a); 176 177 struct isabr_config *isabr_conf = NULL; 178 uint32_t imask[_IPL_N]; /* XXX */ 179 180 void 181 isabrattach(struct isabr_softc *sc) 182 { 183 struct isabus_attach_args iba; 184 185 callout_init(&sysbeep_ch, 0); 186 187 if (isabr_conf == NULL) 188 panic("isabr_conf isn't initialized"); 189 190 aprint_normal("\n"); 191 192 /* Initialize interrupt controller */ 193 isabr_initicu(); 194 195 sc->arc_isa_cs.ic_attach_hook = isabr_attach_hook; 196 sc->arc_isa_cs.ic_detach_hook = isabr_detach_hook; 197 sc->arc_isa_cs.ic_intr_evcnt = isabr_intr_evcnt; 198 sc->arc_isa_cs.ic_intr_establish = isabr_intr_establish; 199 sc->arc_isa_cs.ic_intr_disestablish = isabr_intr_disestablish; 200 201 arc_bus_space_init_extent(&arc_bus_mem, (void *)isa_mem_ex_storage, 202 sizeof(isa_mem_ex_storage)); 203 arc_bus_space_init_extent(&arc_bus_io, (void *)isa_io_ex_storage, 204 sizeof(isa_io_ex_storage)); 205 206 iba.iba_iot = &arc_bus_io; 207 iba.iba_memt = &arc_bus_mem; 208 iba.iba_dmat = &sc->sc_dmat; 209 iba.iba_ic = &sc->arc_isa_cs; 210 config_found(sc->sc_dev, &iba, isabrprint, 211 CFARGS(.iattr = "isabus")); 212 } 213 214 static int 215 isabrprint(void *aux, const char *pnp) 216 { 217 218 if (pnp) 219 aprint_normal("isa at %s", pnp); 220 aprint_verbose(" isa_io_base 0x%"PRIxVADDR" isa_mem_base 0x%"PRIxVADDR, 221 arc_bus_io.bs_vbase, arc_bus_mem.bs_vbase); 222 return UNCONF; 223 } 224 225 226 /* 227 * Interrupt system driver code 228 * ============================ 229 */ 230 #define LEGAL_IRQ(x) ((x) >= 0 && (x) < ICU_LEN && (x) != 2) 231 232 int imen; 233 int intrtype[ICU_LEN], intrmask[ICU_LEN], intrlevel[ICU_LEN]; 234 struct isa_intrhand *isa_intrhand[ICU_LEN]; 235 236 static int 237 fakeintr(void *a) 238 { 239 240 return 0; 241 } 242 243 /* 244 * Recalculate the interrupt masks from scratch. 245 * We could code special registry and deregistry versions of this function that 246 * would be faster, but the code would be nastier, and we don't expect this to 247 * happen very much anyway. 248 */ 249 static void 250 intr_calculatemasks(void) 251 { 252 int irq, level; 253 struct isa_intrhand *q; 254 255 /* First, figure out which levels each IRQ uses. */ 256 for (irq = 0; irq < ICU_LEN; irq++) { 257 int levels = 0; 258 for (q = isa_intrhand[irq]; q; q = q->ih_next) 259 levels |= 1 << q->ih_level; 260 intrlevel[irq] = levels; 261 } 262 263 /* Then figure out which IRQs use each level. */ 264 for (level = 0; level < _IPL_N; level++) { 265 int irqs = 0; 266 for (irq = 0; irq < ICU_LEN; irq++) 267 if (intrlevel[irq] & (1 << level)) 268 irqs |= 1 << irq; 269 imask[level] = irqs; 270 } 271 272 imask[IPL_NONE] = 0; 273 274 imask[IPL_SOFTCLOCK] |= imask[IPL_NONE]; 275 imask[IPL_SOFTNET] |= imask[IPL_SOFTCLOCK]; 276 277 /* 278 * Enforce a hierarchy that gives slow devices a better chance at not 279 * dropping data. 280 */ 281 imask[IPL_VM] |= imask[IPL_SOFTNET]; 282 283 /* 284 * Since run queues may be manipulated by both the statclock and tty, 285 * network, and diskdrivers, clock > tty. 286 */ 287 imask[IPL_SCHED] |= imask[IPL_VM]; 288 289 /* And eventually calculate the complete masks. */ 290 for (irq = 0; irq < ICU_LEN; irq++) { 291 int irqs = 1 << irq; 292 for (q = isa_intrhand[irq]; q; q = q->ih_next) 293 irqs |= imask[q->ih_level]; 294 intrmask[irq] = irqs; 295 } 296 297 /* Lastly, determine which IRQs are actually in use. */ 298 { 299 int irqs = 0; 300 for (irq = 0; irq < ICU_LEN; irq++) 301 if (isa_intrhand[irq]) 302 irqs |= 1 << irq; 303 if (irqs >= 0x100) /* any IRQs >= 8 in use */ 304 irqs |= 1 << IRQ_SLAVE; 305 imen = ~irqs; 306 isa_outb(IO_ICU1 + PIC_OCW1, imen); 307 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 308 } 309 } 310 311 static void 312 isabr_attach_hook(device_t parent, device_t self, 313 struct isabus_attach_args *iba) 314 { 315 316 /* Nothing to do. */ 317 } 318 319 static void 320 isabr_detach_hook(isa_chipset_tag_t ic, device_t self) 321 { 322 323 /* Nothing to do. */ 324 } 325 326 static const struct evcnt * 327 isabr_intr_evcnt(isa_chipset_tag_t ic, int irq) 328 { 329 330 /* XXX for now, no evcnt parent reported */ 331 return NULL; 332 } 333 334 /* 335 * Establish a ISA bus interrupt. 336 */ 337 static void * 338 isabr_intr_establish(isa_chipset_tag_t ic, int irq, int type, int level, 339 int (*ih_fun)(void *), void *ih_arg) 340 { 341 struct isa_intrhand **p, *q, *ih; 342 static struct isa_intrhand fakehand = {NULL, fakeintr}; 343 344 ih = kmem_alloc(sizeof *ih, KM_SLEEP); 345 346 if (!LEGAL_IRQ(irq) || type == IST_NONE) 347 panic("intr_establish: bogus irq or type"); 348 349 switch (intrtype[irq]) { 350 case IST_NONE: 351 intrtype[irq] = type; 352 break; 353 case IST_EDGE: 354 case IST_LEVEL: 355 if (type == intrtype[irq]) 356 break; 357 case IST_PULSE: 358 if (type != IST_NONE) 359 panic("intr_establish: can't share %s with %s", 360 isa_intr_typename(intrtype[irq]), 361 isa_intr_typename(type)); 362 break; 363 } 364 365 /* 366 * Figure out where to put the handler. 367 * This is O(N^2), but we want to preserve the order, and N is 368 * generally small. 369 */ 370 for (p = &isa_intrhand[irq]; (q = *p) != NULL; p = &q->ih_next) 371 ; 372 373 /* 374 * Actually install a fake handler momentarily, since we might be doing 375 * this with interrupts enabled and don't want the real routine called 376 * until masking is set up. 377 */ 378 fakehand.ih_level = level; 379 *p = &fakehand; 380 381 intr_calculatemasks(); 382 383 /* 384 * Poke the real handler in now. 385 */ 386 ih->ih_fun = ih_fun; 387 ih->ih_arg = ih_arg; 388 ih->ih_count = 0; 389 ih->ih_next = NULL; 390 ih->ih_level = level; 391 ih->ih_irq = irq; 392 snprintf(ih->ih_evname, sizeof(ih->ih_evname), "irq %d", irq); 393 evcnt_attach_dynamic(&ih->ih_evcnt, EVCNT_TYPE_INTR, NULL, "isa", 394 ih->ih_evname); 395 *p = ih; 396 397 return ih; 398 } 399 400 static void 401 isabr_intr_disestablish(isa_chipset_tag_t ic, void *arg) 402 { 403 404 } 405 406 /* 407 * Process an interrupt from the ISA bus. 408 */ 409 uint32_t 410 isabr_iointr(uint32_t mask, struct clockframe *cf) 411 { 412 struct isa_intrhand *ih; 413 int isa_vector; 414 int o_imen; 415 416 isa_vector = (*isabr_conf->ic_intr_status)(); 417 if (isa_vector < 0) 418 return 0; 419 420 o_imen = imen; 421 imen |= 1 << (isa_vector & (ICU_LEN - 1)); 422 if (isa_vector & 0x08) { 423 isa_inb(IO_ICU2 + PIC_OCW1); 424 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 425 isa_outb(IO_ICU2 + PIC_OCW2, 426 OCW2_SELECT | OCW2_EOI | OCW2_SL | 427 OCW2_ILS((isa_vector & 7))); 428 isa_outb(IO_ICU1, 429 OCW2_SELECT | OCW2_EOI | OCW2_SL | IRQ_SLAVE); 430 } else { 431 isa_inb(IO_ICU1 + PIC_OCW1); 432 isa_outb(IO_ICU1 + PIC_OCW1, imen); 433 isa_outb(IO_ICU1 + PIC_OCW2, 434 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(isa_vector)); 435 } 436 ih = isa_intrhand[isa_vector]; 437 if (isa_vector == 0 && ih) { /* Clock */ /*XXX*/ 438 last_cp0_count = mips3_cp0_count_read(); 439 /* XXX: spllowerclock() not allowed */ 440 cf->sr &= ~MIPS_SR_INT_IE; 441 if ((*ih->ih_fun)(cf)) 442 ih->ih_evcnt.ev_count++; 443 ih = ih->ih_next; 444 } 445 while (ih) { 446 if ((*ih->ih_fun)(ih->ih_arg)) 447 ih->ih_evcnt.ev_count++; 448 ih = ih->ih_next; 449 } 450 imen = o_imen; 451 isa_inb(IO_ICU1 + PIC_OCW1); 452 isa_inb(IO_ICU2 + PIC_OCW1); 453 isa_outb(IO_ICU1 + PIC_OCW1, imen); 454 isa_outb(IO_ICU2 + PIC_OCW1, imen >> 8); 455 456 return MIPS_INT_MASK_2; 457 } 458 459 460 /* 461 * Initialize the Interrupt controller logic. 462 */ 463 static void 464 isabr_initicu(void) 465 { 466 467 int i; 468 469 for (i = 0; i < ICU_LEN; i++) { 470 switch (i) { 471 case 2: 472 case 8: 473 intrtype[i] = IST_EDGE; 474 break; 475 default: 476 intrtype[i] = IST_NONE; 477 break; 478 } 479 } 480 481 /* reset; program device, four bytes */ 482 isa_outb(IO_ICU1 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 483 /* starting at this vector index */ 484 isa_outb(IO_ICU1 + PIC_ICW2, 0); 485 /* slave on line 2 */ 486 isa_outb(IO_ICU1 + PIC_ICW3, ICW3_CASCADE(IRQ_SLAVE)); 487 /* 8086 mode */ 488 isa_outb(IO_ICU1 + PIC_ICW4, ICW4_8086); 489 490 /* leave interrupts masked */ 491 isa_outb(IO_ICU1 + PIC_OCW1, 0xff); 492 493 /* special mask mode (if available) */ 494 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 495 /* Read IRR by default. */ 496 isa_outb(IO_ICU1 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 497 #ifdef REORDER_IRQ 498 /* pri order 3-7, 0-2 (com2 first) */ 499 isa_outb(IO_ICU1 + PIC_OCW2, 500 OCW2_SELECT | OCW2_R | OCW2_SL OCW2_ILS(3 - 1)); 501 #endif 502 503 /* reset; program device, four bytes */ 504 isa_outb(IO_ICU2 + PIC_ICW1, ICW1_SELECT | ICW1_IC4); 505 /* staring at this vector index */ 506 isa_outb(IO_ICU2 + PIC_ICW2, 8); 507 /* slave connected to line 2 of master */ 508 isa_outb(IO_ICU2 + PIC_ICW3, ICW3_SIC(IRQ_SLAVE)); 509 /* 8086 mode */ 510 isa_outb(IO_ICU2 + PIC_ICW4, ICW4_8086); 511 512 /* leave interrupts masked */ 513 isa_outb(IO_ICU2 + PIC_OCW1, 0xff); 514 515 /* special mask mode (if available) */ 516 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_SSMM | OCW3_SMM); 517 /* Read IRR by default. */ 518 isa_outb(IO_ICU2 + PIC_OCW3, OCW3_SELECT | OCW3_RR); 519 } 520 521 522 /* 523 * SPEAKER BEEPER... 524 */ 525 void 526 sysbeepstop(void *arg) 527 { 528 int s; 529 530 /* disable counter 2 */ 531 s = splhigh(); 532 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) & ~PIT_SPKR); 533 splx(s); 534 beeping = 0; 535 } 536 537 void 538 sysbeep(int pitch, int period) 539 { 540 static int last_pitch, last_period; 541 int s; 542 543 if (cold) 544 return; /* Can't beep yet. */ 545 546 if (beeping) 547 callout_stop(&sysbeep_ch); 548 if (!beeping || last_pitch != pitch) { 549 s = splhigh(); 550 isa_outb(IO_TIMER1 + TIMER_MODE, 551 TIMER_SEL2 | TIMER_16BIT | TIMER_SQWAVE); 552 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) % 256); 553 isa_outb(IO_TIMER1 + TIMER_CNTR2, TIMER_DIV(pitch) / 256); 554 isa_outb(PITAUX_PORT, isa_inb(PITAUX_PORT) | PIT_SPKR); 555 splx(s); 556 } 557 last_pitch = pitch; 558 beeping = last_period = period; 559 callout_reset(&sysbeep_ch, period, sysbeepstop, NULL); 560 } 561 562 int 563 isa_intr_alloc(isa_chipset_tag_t c, int mask, int type, int *irq_p) 564 { 565 int irq; 566 int maybe_irq = -1; 567 int shared_depth = 0; 568 mask &= 0x8b28; /* choose from 3, 5, 8, 9, 11, 15 XXX */ 569 for (irq = 0; mask != 0; mask >>= 1, irq++) { 570 if ((mask & 1) == 0) 571 continue; 572 if (intrtype[irq] == IST_NONE) { 573 *irq_p = irq; 574 return 0; 575 } 576 /* Level interrupts can be shared */ 577 if (type == IST_LEVEL && intrtype[irq] == IST_LEVEL) { 578 struct isa_intrhand *ih = isa_intrhand[irq]; 579 int depth; 580 if (maybe_irq == -1) { 581 maybe_irq = irq; 582 continue; 583 } 584 for (depth = 0; ih != NULL; ih = ih->ih_next) 585 depth++; 586 if (depth < shared_depth) { 587 maybe_irq = irq; 588 shared_depth = depth; 589 } 590 } 591 } 592 if (maybe_irq != -1) { 593 *irq_p = maybe_irq; 594 return 0; 595 } 596 return 1; 597 } 598
Indexes created Fri Sep 26 08:10:20 GMT 2025