asc.c revision 1.14
1 /* $NetBSD: asc.c,v 1.14 2005/01/22 07:32:05 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Izumi Tsutsui. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: asc.c,v 1.14 2005/01/22 07:32:05 tsutsui Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/buf.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/bus.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <arc/jazz/jazziovar.h> 48 #include <arc/jazz/dma.h> 49 #include <arc/jazz/pica.h> 50 51 #include <dev/ic/ncr53c9xreg.h> 52 #include <dev/ic/ncr53c9xvar.h> 53 54 #define ASC_NPORTS 0x10 55 #define ASC_ID_53CF94 0xa2 /* XXX should be in MI ncr53c9xreg.h? */ 56 57 struct asc_softc { 58 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 59 60 bus_space_tag_t sc_iot; /* bus space tag */ 61 bus_space_handle_t sc_ioh; /* bus space handle */ 62 bus_space_handle_t sc_dmaioh; /* bus space handle for DMAC */ 63 64 bus_dma_tag_t sc_dmat; /* DMA tag */ 65 bus_dmamap_t sc_dmamap; /* DMA map for transfers */ 66 67 int sc_active; /* DMA state */ 68 int sc_datain; /* DMA Data Direction */ 69 size_t sc_dmasize; /* DMA size */ 70 char **sc_dmaaddr; /* DMA address */ 71 size_t *sc_dmalen; /* DMA length */ 72 }; 73 74 /* 75 * Autoconfiguration data for config. 76 */ 77 int asc_match(struct device *, struct cfdata *, void *); 78 void asc_attach(struct device *, struct device *, void *); 79 80 CFATTACH_DECL(asc, sizeof(struct asc_softc), 81 asc_match, asc_attach, NULL, NULL); 82 83 /* 84 * Functions and the switch for the MI code. 85 */ 86 u_char asc_read_reg(struct ncr53c9x_softc *, int); 87 void asc_write_reg(struct ncr53c9x_softc *, int, u_char); 88 int asc_dma_isintr(struct ncr53c9x_softc *); 89 void asc_dma_reset(struct ncr53c9x_softc *); 90 int asc_dma_intr(struct ncr53c9x_softc *); 91 int asc_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, size_t *); 92 void asc_dma_go(struct ncr53c9x_softc *); 93 void asc_dma_stop(struct ncr53c9x_softc *); 94 int asc_dma_isactive(struct ncr53c9x_softc *); 95 96 struct ncr53c9x_glue asc_glue = { 97 asc_read_reg, 98 asc_write_reg, 99 asc_dma_isintr, 100 asc_dma_reset, 101 asc_dma_intr, 102 asc_dma_setup, 103 asc_dma_go, 104 asc_dma_stop, 105 asc_dma_isactive, 106 NULL /* gl_clear_latched_intr */ 107 }; 108 109 /* 110 * Match driver based on name 111 */ 112 int 113 asc_match(parent, match, aux) 114 struct device *parent; 115 struct cfdata *match; 116 void *aux; 117 { 118 struct jazzio_attach_args *ja = aux; 119 120 if (strcmp(ja->ja_name, "ESP216") != 0) 121 return 0; 122 return 1; 123 } 124 125 void 126 asc_attach(parent, self, aux) 127 struct device *parent; 128 struct device *self; 129 void *aux; 130 { 131 struct jazzio_attach_args *ja = aux; 132 struct asc_softc *asc = (void *)self; 133 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 134 bus_space_tag_t iot; 135 136 #if 0 137 /* Need info from platform dependent config?? */ 138 if (asc_conf == NULL) 139 panic("asc_conf isn't initialized"); 140 #endif 141 142 sc->sc_glue = &asc_glue; 143 144 asc->sc_iot = iot = ja->ja_bust; 145 asc->sc_dmat = ja->ja_dmat; 146 147 if (bus_space_map(iot, ja->ja_addr, ASC_NPORTS, 0, &asc->sc_ioh)) { 148 printf(": unable to map I/O space\n"); 149 return; 150 } 151 152 if (bus_space_map(iot, R4030_SYS_DMA0_REGS, R4030_DMA_RANGE, 153 0, &asc->sc_dmaioh)) { 154 printf(": unable to map DMA I/O space\n"); 155 goto out1; 156 } 157 158 if (bus_dmamap_create(asc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 159 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &asc->sc_dmamap)) { 160 printf(": unable to create DMA map\n"); 161 goto out2; 162 } 163 164 /* 165 * XXX More of this should be in ncr53c9x_attach(), but 166 * XXX should we really poke around the chip that much in 167 * XXX the MI code? Think about this more... 168 */ 169 170 /* 171 * Set up static configuration info. 172 */ 173 sc->sc_id = 7; /* XXX should be taken from ARC BIOS */ 174 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 175 176 /* identify 53CF9x-2 or not */ 177 asc_write_reg(sc, NCR_CMD, NCRCMD_RSTCHIP); 178 DELAY(25); 179 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 180 DELAY(25); 181 asc_write_reg(sc, NCR_CFG2, NCRCFG2_FE); 182 DELAY(25); 183 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 184 DELAY(25); 185 if (asc_read_reg(sc, NCR_TCH) == ASC_ID_53CF94) { 186 /* XXX should be have NCR_VARIANT_NCR53CF94? */ 187 sc->sc_rev = NCR_VARIANT_NCR53C94; 188 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 189 sc->sc_cfg3 = NCRF9XCFG3_IDM | NCRF9XCFG3_FCLK; 190 sc->sc_features = NCR_F_FASTSCSI; 191 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 192 sc->sc_freq = 40; /* MHz */ 193 sc->sc_maxxfer = 16 * 1024 * 1024; 194 } else { 195 sc->sc_rev = NCR_VARIANT_NCR53C94; 196 sc->sc_freq = 25; /* MHz */ 197 sc->sc_maxxfer = 64 * 1024; 198 } 199 200 /* 201 * XXX minsync and maxxfer _should_ be set up in MI code, 202 * XXX but it appears to have some dependency on what sort 203 * XXX of DMA we're hooked up to, etc. 204 */ 205 206 /* 207 * This is the value used to start sync negotiations 208 * Note that the NCR register "SYNCTP" is programmed 209 * in "clocks per byte", and has a minimum value of 4. 210 * The SCSI period used in negotiation is one-fourth 211 * of the time (in nanoseconds) needed to transfer one byte. 212 * Since the chip's clock is given in MHz, we have the following 213 * formula: 4 * period = (1000 / freq) * 4 214 */ 215 sc->sc_minsync = 1000 / sc->sc_freq; 216 217 /* establish interrupt */ 218 jazzio_intr_establish(ja->ja_intr, ncr53c9x_intr, asc); 219 220 /* Do the common parts of attachment. */ 221 sc->sc_adapter.adapt_minphys = minphys; 222 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 223 ncr53c9x_attach(sc); 224 225 /* Turn on target selection using the `DMA' method */ 226 sc->sc_features |= NCR_F_DMASELECT; 227 return; 228 229 out2: 230 bus_space_unmap(iot, asc->sc_dmaioh, R4030_DMA_RANGE); 231 out1: 232 bus_space_unmap(iot, asc->sc_ioh, ASC_NPORTS); 233 } 234 235 /* 236 * Glue functions. 237 */ 238 239 u_char 240 asc_read_reg(sc, reg) 241 struct ncr53c9x_softc *sc; 242 int reg; 243 { 244 struct asc_softc *asc = (struct asc_softc *)sc; 245 246 return bus_space_read_1(asc->sc_iot, asc->sc_ioh, reg); 247 } 248 249 void 250 asc_write_reg(sc, reg, val) 251 struct ncr53c9x_softc *sc; 252 int reg; 253 u_char val; 254 { 255 struct asc_softc *asc = (struct asc_softc *)sc; 256 257 bus_space_write_1(asc->sc_iot, asc->sc_ioh, reg, val); 258 } 259 260 int 261 asc_dma_isintr(sc) 262 struct ncr53c9x_softc *sc; 263 { 264 265 return asc_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 266 } 267 268 void 269 asc_dma_reset(sc) 270 struct ncr53c9x_softc *sc; 271 { 272 struct asc_softc *asc = (struct asc_softc *)sc; 273 274 /* halt DMA */ 275 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 276 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 277 } 278 279 int 280 asc_dma_intr(sc) 281 struct ncr53c9x_softc *sc; 282 { 283 struct asc_softc *asc = (struct asc_softc *)sc; 284 int datain, resid, trans; 285 286 datain = asc->sc_datain; 287 288 #ifdef DIAGNOSTIC 289 /* This is an "assertion" :) */ 290 if (asc->sc_active == 0) 291 panic("asc_dma_intr: DMA wasn't active"); 292 #endif 293 294 /* DMA has stopped */ 295 296 asc->sc_active = 0; 297 298 if (asc->sc_dmasize == 0) { 299 /* A "Transfer Pad" operation complete */ 300 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 301 NCR_READ_REG(sc, NCR_TCL) | 302 (NCR_READ_REG(sc, NCR_TCM) << 8), 303 NCR_READ_REG(sc, NCR_TCL), 304 NCR_READ_REG(sc, NCR_TCM))); 305 306 return 0; 307 } 308 309 resid = 0; 310 311 /* 312 * If a transfer onto the SCSI bus gets interrupted by the device 313 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 314 * as residual since the ESP counter registers get decremented as 315 * bytes are clocked into the FIFO. 316 */ 317 if (!datain && 318 (resid = (asc_read_reg(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 319 NCR_DMA(("asc_dma_intr: empty asc FIFO of %d ", resid)); 320 } 321 322 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 323 /* 324 * `Terminal count' is off, so read the residue 325 * out of the ASC counter registers. 326 */ 327 resid += (NCR_READ_REG(sc, NCR_TCL) | 328 (NCR_READ_REG(sc, NCR_TCM) << 8) | 329 ((sc->sc_cfg2 & NCRCFG2_FE) 330 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 331 332 if (resid == 0 && asc->sc_dmasize == 65536 && 333 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 334 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 335 resid = 65536; 336 } 337 338 /* halt DMA */ 339 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_COUNT, 0); 340 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 341 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 342 343 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 344 0, asc->sc_dmamap->dm_mapsize, 345 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 346 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 347 348 trans = asc->sc_dmasize - resid; 349 350 if (trans < 0) { /* transfered < 0 ? */ 351 #if 0 352 /* 353 * This situation can happen in perfectly normal operation 354 * if the ESP is reselected while using DMA to select 355 * another target. As such, don't print the warning. 356 */ 357 printf("%s: xfer (%d) > req (%d)\n", 358 sc->sc_dev.dv_xname, trans, asc->sc_dmasize); 359 #endif 360 trans = asc->sc_dmasize; 361 } 362 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 363 NCR_READ_REG(sc, NCR_TCL), 364 NCR_READ_REG(sc, NCR_TCM), 365 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 366 trans, resid)); 367 368 *asc->sc_dmalen -= trans; 369 *asc->sc_dmaaddr += trans; 370 371 return 0; 372 } 373 374 int 375 asc_dma_setup(sc, addr, len, datain, dmasize) 376 struct ncr53c9x_softc *sc; 377 caddr_t *addr; 378 size_t *len; 379 int datain; 380 size_t *dmasize; 381 { 382 struct asc_softc *asc = (struct asc_softc *)sc; 383 384 /* halt DMA */ 385 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 386 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 387 388 asc->sc_dmaaddr = addr; 389 asc->sc_dmalen = len; 390 asc->sc_dmasize = *dmasize; 391 asc->sc_datain = datain; 392 393 /* 394 * No need to set up DMA in `Transfer Pad' operation. 395 */ 396 if (*dmasize == 0) 397 return 0; 398 399 bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, *len, NULL, 400 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 401 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 402 (datain ? BUS_DMA_READ : BUS_DMA_WRITE)); 403 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 404 0, asc->sc_dmamap->dm_mapsize, 405 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 406 407 return 0; 408 } 409 410 void 411 asc_dma_go(sc) 412 struct ncr53c9x_softc *sc; 413 { 414 struct asc_softc *asc = (struct asc_softc *)sc; 415 416 /* No DMA transfer in Transfer Pad operation */ 417 if (asc->sc_dmasize == 0) 418 return; 419 420 /* load transfer parameters */ 421 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 422 R4030_DMA_ADDR, asc->sc_dmamap->dm_segs[0].ds_addr); 423 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 424 R4030_DMA_COUNT, asc->sc_dmamap->dm_segs[0].ds_len); 425 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 426 R4030_DMA_MODE, R4030_DMA_MODE_160NS | R4030_DMA_MODE_16); 427 428 /* start DMA */ 429 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 430 R4030_DMA_ENAB, R4030_DMA_ENAB_RUN | 431 (asc->sc_datain ? R4030_DMA_ENAB_READ : R4030_DMA_ENAB_WRITE)); 432 433 asc->sc_active = 1; 434 } 435 436 void 437 asc_dma_stop(sc) 438 struct ncr53c9x_softc *sc; 439 { 440 struct asc_softc *asc = (struct asc_softc *)sc; 441 442 /* halt DMA */ 443 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 444 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 445 446 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 447 448 asc->sc_active = 0; 449 } 450 451 int 452 asc_dma_isactive(sc) 453 struct ncr53c9x_softc *sc; 454 { 455 struct asc_softc *asc = (struct asc_softc *)sc; 456 457 return asc->sc_active; 458 } 459
Indexes created Thu Oct 02 14:10:14 GMT 2025