asc.c revision 1.15
1 /* $NetBSD: asc.c,v 1.15 2005/01/22 07:35:34 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Izumi Tsutsui. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: asc.c,v 1.15 2005/01/22 07:35:34 tsutsui Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/buf.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/bus.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <arc/jazz/jazziovar.h> 48 #include <arc/jazz/dma.h> 49 #include <arc/jazz/pica.h> 50 51 #include <dev/ic/ncr53c9xreg.h> 52 #include <dev/ic/ncr53c9xvar.h> 53 54 #define ASC_NPORTS 0x10 55 #define ASC_ID_53CF94 0xa2 /* XXX should be in MI ncr53c9xreg.h? */ 56 57 struct asc_softc { 58 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 59 60 bus_space_tag_t sc_iot; /* bus space tag */ 61 bus_space_handle_t sc_ioh; /* bus space handle */ 62 bus_space_handle_t sc_dmaioh; /* bus space handle for DMAC */ 63 64 bus_dma_tag_t sc_dmat; /* DMA tag */ 65 bus_dmamap_t sc_dmamap; /* DMA map for transfers */ 66 67 int sc_active; /* DMA state */ 68 int sc_datain; /* DMA Data Direction */ 69 size_t sc_dmasize; /* DMA size */ 70 char **sc_dmaaddr; /* DMA address */ 71 size_t *sc_dmalen; /* DMA length */ 72 }; 73 74 /* 75 * Autoconfiguration data for config. 76 */ 77 int asc_match(struct device *, struct cfdata *, void *); 78 void asc_attach(struct device *, struct device *, void *); 79 80 CFATTACH_DECL(asc, sizeof(struct asc_softc), 81 asc_match, asc_attach, NULL, NULL); 82 83 /* 84 * Functions and the switch for the MI code. 85 */ 86 u_char asc_read_reg(struct ncr53c9x_softc *, int); 87 void asc_write_reg(struct ncr53c9x_softc *, int, u_char); 88 int asc_dma_isintr(struct ncr53c9x_softc *); 89 void asc_dma_reset(struct ncr53c9x_softc *); 90 int asc_dma_intr(struct ncr53c9x_softc *); 91 int asc_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, size_t *); 92 void asc_dma_go(struct ncr53c9x_softc *); 93 void asc_dma_stop(struct ncr53c9x_softc *); 94 int asc_dma_isactive(struct ncr53c9x_softc *); 95 96 struct ncr53c9x_glue asc_glue = { 97 asc_read_reg, 98 asc_write_reg, 99 asc_dma_isintr, 100 asc_dma_reset, 101 asc_dma_intr, 102 asc_dma_setup, 103 asc_dma_go, 104 asc_dma_stop, 105 asc_dma_isactive, 106 NULL /* gl_clear_latched_intr */ 107 }; 108 109 /* 110 * Match driver based on name 111 */ 112 int 113 asc_match(struct device *parent, struct cfdata *match, void *aux) 114 { 115 struct jazzio_attach_args *ja = aux; 116 117 if (strcmp(ja->ja_name, "ESP216") != 0) 118 return 0; 119 return 1; 120 } 121 122 void 123 asc_attach(struct device *parent, struct device *self, void *aux) 124 { 125 struct jazzio_attach_args *ja = aux; 126 struct asc_softc *asc = (void *)self; 127 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 128 bus_space_tag_t iot; 129 130 #if 0 131 /* Need info from platform dependent config?? */ 132 if (asc_conf == NULL) 133 panic("asc_conf isn't initialized"); 134 #endif 135 136 sc->sc_glue = &asc_glue; 137 138 asc->sc_iot = iot = ja->ja_bust; 139 asc->sc_dmat = ja->ja_dmat; 140 141 if (bus_space_map(iot, ja->ja_addr, ASC_NPORTS, 0, &asc->sc_ioh)) { 142 printf(": unable to map I/O space\n"); 143 return; 144 } 145 146 if (bus_space_map(iot, R4030_SYS_DMA0_REGS, R4030_DMA_RANGE, 147 0, &asc->sc_dmaioh)) { 148 printf(": unable to map DMA I/O space\n"); 149 goto out1; 150 } 151 152 if (bus_dmamap_create(asc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 153 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &asc->sc_dmamap)) { 154 printf(": unable to create DMA map\n"); 155 goto out2; 156 } 157 158 /* 159 * XXX More of this should be in ncr53c9x_attach(), but 160 * XXX should we really poke around the chip that much in 161 * XXX the MI code? Think about this more... 162 */ 163 164 /* 165 * Set up static configuration info. 166 */ 167 sc->sc_id = 7; /* XXX should be taken from ARC BIOS */ 168 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 169 170 /* identify 53CF9x-2 or not */ 171 asc_write_reg(sc, NCR_CMD, NCRCMD_RSTCHIP); 172 DELAY(25); 173 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 174 DELAY(25); 175 asc_write_reg(sc, NCR_CFG2, NCRCFG2_FE); 176 DELAY(25); 177 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 178 DELAY(25); 179 if (asc_read_reg(sc, NCR_TCH) == ASC_ID_53CF94) { 180 /* XXX should be have NCR_VARIANT_NCR53CF94? */ 181 sc->sc_rev = NCR_VARIANT_NCR53C94; 182 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 183 sc->sc_cfg3 = NCRF9XCFG3_IDM | NCRF9XCFG3_FCLK; 184 sc->sc_features = NCR_F_FASTSCSI; 185 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 186 sc->sc_freq = 40; /* MHz */ 187 sc->sc_maxxfer = 16 * 1024 * 1024; 188 } else { 189 sc->sc_rev = NCR_VARIANT_NCR53C94; 190 sc->sc_freq = 25; /* MHz */ 191 sc->sc_maxxfer = 64 * 1024; 192 } 193 194 /* 195 * XXX minsync and maxxfer _should_ be set up in MI code, 196 * XXX but it appears to have some dependency on what sort 197 * XXX of DMA we're hooked up to, etc. 198 */ 199 200 /* 201 * This is the value used to start sync negotiations 202 * Note that the NCR register "SYNCTP" is programmed 203 * in "clocks per byte", and has a minimum value of 4. 204 * The SCSI period used in negotiation is one-fourth 205 * of the time (in nanoseconds) needed to transfer one byte. 206 * Since the chip's clock is given in MHz, we have the following 207 * formula: 4 * period = (1000 / freq) * 4 208 */ 209 sc->sc_minsync = 1000 / sc->sc_freq; 210 211 /* establish interrupt */ 212 jazzio_intr_establish(ja->ja_intr, ncr53c9x_intr, asc); 213 214 /* Do the common parts of attachment. */ 215 sc->sc_adapter.adapt_minphys = minphys; 216 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 217 ncr53c9x_attach(sc); 218 219 /* Turn on target selection using the `DMA' method */ 220 sc->sc_features |= NCR_F_DMASELECT; 221 return; 222 223 out2: 224 bus_space_unmap(iot, asc->sc_dmaioh, R4030_DMA_RANGE); 225 out1: 226 bus_space_unmap(iot, asc->sc_ioh, ASC_NPORTS); 227 } 228 229 /* 230 * Glue functions. 231 */ 232 233 u_char 234 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 235 { 236 struct asc_softc *asc = (struct asc_softc *)sc; 237 238 return bus_space_read_1(asc->sc_iot, asc->sc_ioh, reg); 239 } 240 241 void 242 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 243 { 244 struct asc_softc *asc = (struct asc_softc *)sc; 245 246 bus_space_write_1(asc->sc_iot, asc->sc_ioh, reg, val); 247 } 248 249 int 250 asc_dma_isintr(struct ncr53c9x_softc *sc) 251 { 252 253 return asc_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 254 } 255 256 void 257 asc_dma_reset(struct ncr53c9x_softc *sc) 258 { 259 struct asc_softc *asc = (struct asc_softc *)sc; 260 261 /* halt DMA */ 262 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 263 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 264 } 265 266 int 267 asc_dma_intr(struct ncr53c9x_softc *sc) 268 { 269 struct asc_softc *asc = (struct asc_softc *)sc; 270 int datain, resid, trans; 271 272 datain = asc->sc_datain; 273 274 #ifdef DIAGNOSTIC 275 /* This is an "assertion" :) */ 276 if (asc->sc_active == 0) 277 panic("asc_dma_intr: DMA wasn't active"); 278 #endif 279 280 /* DMA has stopped */ 281 282 asc->sc_active = 0; 283 284 if (asc->sc_dmasize == 0) { 285 /* A "Transfer Pad" operation complete */ 286 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 287 NCR_READ_REG(sc, NCR_TCL) | 288 (NCR_READ_REG(sc, NCR_TCM) << 8), 289 NCR_READ_REG(sc, NCR_TCL), 290 NCR_READ_REG(sc, NCR_TCM))); 291 292 return 0; 293 } 294 295 resid = 0; 296 297 /* 298 * If a transfer onto the SCSI bus gets interrupted by the device 299 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 300 * as residual since the ESP counter registers get decremented as 301 * bytes are clocked into the FIFO. 302 */ 303 if (!datain && 304 (resid = (asc_read_reg(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 305 NCR_DMA(("asc_dma_intr: empty asc FIFO of %d ", resid)); 306 } 307 308 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 309 /* 310 * `Terminal count' is off, so read the residue 311 * out of the ASC counter registers. 312 */ 313 resid += (NCR_READ_REG(sc, NCR_TCL) | 314 (NCR_READ_REG(sc, NCR_TCM) << 8) | 315 ((sc->sc_cfg2 & NCRCFG2_FE) 316 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 317 318 if (resid == 0 && asc->sc_dmasize == 65536 && 319 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 320 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 321 resid = 65536; 322 } 323 324 /* halt DMA */ 325 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_COUNT, 0); 326 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 327 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 328 329 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 330 0, asc->sc_dmamap->dm_mapsize, 331 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 332 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 333 334 trans = asc->sc_dmasize - resid; 335 336 if (trans < 0) { /* transfered < 0 ? */ 337 #if 0 338 /* 339 * This situation can happen in perfectly normal operation 340 * if the ESP is reselected while using DMA to select 341 * another target. As such, don't print the warning. 342 */ 343 printf("%s: xfer (%d) > req (%d)\n", 344 sc->sc_dev.dv_xname, trans, asc->sc_dmasize); 345 #endif 346 trans = asc->sc_dmasize; 347 } 348 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 349 NCR_READ_REG(sc, NCR_TCL), 350 NCR_READ_REG(sc, NCR_TCM), 351 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 352 trans, resid)); 353 354 *asc->sc_dmalen -= trans; 355 *asc->sc_dmaaddr += trans; 356 357 return 0; 358 } 359 360 int 361 asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 362 int datain, size_t *dmasize) 363 { 364 struct asc_softc *asc = (struct asc_softc *)sc; 365 366 /* halt DMA */ 367 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 368 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 369 370 asc->sc_dmaaddr = addr; 371 asc->sc_dmalen = len; 372 asc->sc_dmasize = *dmasize; 373 asc->sc_datain = datain; 374 375 /* 376 * No need to set up DMA in `Transfer Pad' operation. 377 */ 378 if (*dmasize == 0) 379 return 0; 380 381 bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, *len, NULL, 382 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 383 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 384 (datain ? BUS_DMA_READ : BUS_DMA_WRITE)); 385 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 386 0, asc->sc_dmamap->dm_mapsize, 387 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 388 389 return 0; 390 } 391 392 void 393 asc_dma_go(struct ncr53c9x_softc *sc) 394 { 395 struct asc_softc *asc = (struct asc_softc *)sc; 396 397 /* No DMA transfer in Transfer Pad operation */ 398 if (asc->sc_dmasize == 0) 399 return; 400 401 /* load transfer parameters */ 402 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 403 R4030_DMA_ADDR, asc->sc_dmamap->dm_segs[0].ds_addr); 404 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 405 R4030_DMA_COUNT, asc->sc_dmamap->dm_segs[0].ds_len); 406 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 407 R4030_DMA_MODE, R4030_DMA_MODE_160NS | R4030_DMA_MODE_16); 408 409 /* start DMA */ 410 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 411 R4030_DMA_ENAB, R4030_DMA_ENAB_RUN | 412 (asc->sc_datain ? R4030_DMA_ENAB_READ : R4030_DMA_ENAB_WRITE)); 413 414 asc->sc_active = 1; 415 } 416 417 void 418 asc_dma_stop(struct ncr53c9x_softc *sc) 419 { 420 struct asc_softc *asc = (struct asc_softc *)sc; 421 422 /* halt DMA */ 423 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 424 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 425 426 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 427 428 asc->sc_active = 0; 429 } 430 431 int 432 asc_dma_isactive(struct ncr53c9x_softc *sc) 433 { 434 struct asc_softc *asc = (struct asc_softc *)sc; 435 436 return asc->sc_active; 437 } 438
Indexes created Thu Oct 02 14:10:14 GMT 2025