asc.c revision 1.16
1 /* $NetBSD: asc.c,v 1.16 2005/11/06 11:09:17 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Izumi Tsutsui. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: asc.c,v 1.16 2005/11/06 11:09:17 tsutsui Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/buf.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/bus.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <arc/jazz/jazziovar.h> 48 #include <arc/jazz/dma.h> 49 #include <arc/jazz/pica.h> 50 51 #include <dev/ic/ncr53c9xreg.h> 52 #include <dev/ic/ncr53c9xvar.h> 53 54 #define ASC_NPORTS 0x10 55 #define ASC_ID_53CF94 0xa2 /* XXX should be in MI ncr53c9xreg.h? */ 56 57 struct asc_softc { 58 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 59 60 bus_space_tag_t sc_iot; /* bus space tag */ 61 bus_space_handle_t sc_ioh; /* bus space handle */ 62 bus_space_handle_t sc_dmaioh; /* bus space handle for DMAC */ 63 64 bus_dma_tag_t sc_dmat; /* DMA tag */ 65 bus_dmamap_t sc_dmamap; /* DMA map for transfers */ 66 67 int sc_active; /* DMA state */ 68 int sc_datain; /* DMA Data Direction */ 69 size_t sc_dmasize; /* DMA size */ 70 char **sc_dmaaddr; /* DMA address */ 71 size_t *sc_dmalen; /* DMA length */ 72 }; 73 74 /* 75 * Autoconfiguration data for config. 76 */ 77 int asc_match(struct device *, struct cfdata *, void *); 78 void asc_attach(struct device *, struct device *, void *); 79 80 CFATTACH_DECL(asc, sizeof(struct asc_softc), 81 asc_match, asc_attach, NULL, NULL); 82 83 static void asc_minphys(struct buf *); 84 85 /* 86 * Functions and the switch for the MI code. 87 */ 88 u_char asc_read_reg(struct ncr53c9x_softc *, int); 89 void asc_write_reg(struct ncr53c9x_softc *, int, u_char); 90 int asc_dma_isintr(struct ncr53c9x_softc *); 91 void asc_dma_reset(struct ncr53c9x_softc *); 92 int asc_dma_intr(struct ncr53c9x_softc *); 93 int asc_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, size_t *); 94 void asc_dma_go(struct ncr53c9x_softc *); 95 void asc_dma_stop(struct ncr53c9x_softc *); 96 int asc_dma_isactive(struct ncr53c9x_softc *); 97 98 struct ncr53c9x_glue asc_glue = { 99 asc_read_reg, 100 asc_write_reg, 101 asc_dma_isintr, 102 asc_dma_reset, 103 asc_dma_intr, 104 asc_dma_setup, 105 asc_dma_go, 106 asc_dma_stop, 107 asc_dma_isactive, 108 NULL /* gl_clear_latched_intr */ 109 }; 110 111 /* 112 * Match driver based on name 113 */ 114 int 115 asc_match(struct device *parent, struct cfdata *match, void *aux) 116 { 117 struct jazzio_attach_args *ja = aux; 118 119 if (strcmp(ja->ja_name, "ESP216") != 0) 120 return 0; 121 return 1; 122 } 123 124 void 125 asc_attach(struct device *parent, struct device *self, void *aux) 126 { 127 struct jazzio_attach_args *ja = aux; 128 struct asc_softc *asc = (void *)self; 129 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 130 bus_space_tag_t iot; 131 132 #if 0 133 /* Need info from platform dependent config?? */ 134 if (asc_conf == NULL) 135 panic("asc_conf isn't initialized"); 136 #endif 137 138 sc->sc_glue = &asc_glue; 139 140 asc->sc_iot = iot = ja->ja_bust; 141 asc->sc_dmat = ja->ja_dmat; 142 143 if (bus_space_map(iot, ja->ja_addr, ASC_NPORTS, 0, &asc->sc_ioh)) { 144 printf(": unable to map I/O space\n"); 145 return; 146 } 147 148 if (bus_space_map(iot, R4030_SYS_DMA0_REGS, R4030_DMA_RANGE, 149 0, &asc->sc_dmaioh)) { 150 printf(": unable to map DMA I/O space\n"); 151 goto out1; 152 } 153 154 if (bus_dmamap_create(asc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 155 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &asc->sc_dmamap)) { 156 printf(": unable to create DMA map\n"); 157 goto out2; 158 } 159 160 /* 161 * XXX More of this should be in ncr53c9x_attach(), but 162 * XXX should we really poke around the chip that much in 163 * XXX the MI code? Think about this more... 164 */ 165 166 /* 167 * Set up static configuration info. 168 */ 169 sc->sc_id = 7; /* XXX should be taken from ARC BIOS */ 170 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 171 172 /* identify 53CF9x-2 or not */ 173 asc_write_reg(sc, NCR_CMD, NCRCMD_RSTCHIP); 174 DELAY(25); 175 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 176 DELAY(25); 177 asc_write_reg(sc, NCR_CFG2, NCRCFG2_FE); 178 DELAY(25); 179 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 180 DELAY(25); 181 if (asc_read_reg(sc, NCR_TCH) == ASC_ID_53CF94) { 182 /* XXX should be have NCR_VARIANT_NCR53CF94? */ 183 sc->sc_rev = NCR_VARIANT_NCR53C94; 184 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 185 sc->sc_cfg3 = NCRF9XCFG3_IDM | NCRF9XCFG3_FCLK; 186 sc->sc_features = NCR_F_FASTSCSI; 187 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 188 sc->sc_freq = 40; /* MHz */ 189 sc->sc_maxxfer = 16 * 1024 * 1024; 190 } else { 191 sc->sc_rev = NCR_VARIANT_NCR53C94; 192 sc->sc_freq = 25; /* MHz */ 193 sc->sc_maxxfer = 64 * 1024; 194 } 195 196 /* 197 * XXX minsync and maxxfer _should_ be set up in MI code, 198 * XXX but it appears to have some dependency on what sort 199 * XXX of DMA we're hooked up to, etc. 200 */ 201 202 /* 203 * This is the value used to start sync negotiations 204 * Note that the NCR register "SYNCTP" is programmed 205 * in "clocks per byte", and has a minimum value of 4. 206 * The SCSI period used in negotiation is one-fourth 207 * of the time (in nanoseconds) needed to transfer one byte. 208 * Since the chip's clock is given in MHz, we have the following 209 * formula: 4 * period = (1000 / freq) * 4 210 */ 211 sc->sc_minsync = 1000 / sc->sc_freq; 212 213 /* establish interrupt */ 214 jazzio_intr_establish(ja->ja_intr, ncr53c9x_intr, asc); 215 216 /* Do the common parts of attachment. */ 217 sc->sc_adapter.adapt_minphys = asc_minphys; 218 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 219 ncr53c9x_attach(sc); 220 221 #if 0 222 /* Turn on target selection using the `DMA' method */ 223 sc->sc_features |= NCR_F_DMASELECT; 224 #endif 225 return; 226 227 out2: 228 bus_space_unmap(iot, asc->sc_dmaioh, R4030_DMA_RANGE); 229 out1: 230 bus_space_unmap(iot, asc->sc_ioh, ASC_NPORTS); 231 } 232 233 234 static void 235 asc_minphys(struct buf *bp) 236 { 237 238 #define ASC_MAX_XFER (32 * 1024) /* XXX can't xfer 64kbytes? */ 239 240 if (bp->b_bcount > ASC_MAX_XFER) 241 bp->b_bcount = ASC_MAX_XFER; 242 minphys(bp); 243 } 244 245 /* 246 * Glue functions. 247 */ 248 249 u_char 250 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 251 { 252 struct asc_softc *asc = (struct asc_softc *)sc; 253 254 return bus_space_read_1(asc->sc_iot, asc->sc_ioh, reg); 255 } 256 257 void 258 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 259 { 260 struct asc_softc *asc = (struct asc_softc *)sc; 261 262 bus_space_write_1(asc->sc_iot, asc->sc_ioh, reg, val); 263 } 264 265 int 266 asc_dma_isintr(struct ncr53c9x_softc *sc) 267 { 268 269 return asc_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 270 } 271 272 void 273 asc_dma_reset(struct ncr53c9x_softc *sc) 274 { 275 struct asc_softc *asc = (struct asc_softc *)sc; 276 277 /* halt DMA */ 278 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 279 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 280 } 281 282 int 283 asc_dma_intr(struct ncr53c9x_softc *sc) 284 { 285 struct asc_softc *asc = (struct asc_softc *)sc; 286 int datain, resid, trans; 287 288 datain = asc->sc_datain; 289 290 #ifdef DIAGNOSTIC 291 /* This is an "assertion" :) */ 292 if (asc->sc_active == 0) 293 panic("asc_dma_intr: DMA wasn't active"); 294 #endif 295 296 /* DMA has stopped */ 297 298 asc->sc_active = 0; 299 300 if (asc->sc_dmasize == 0) { 301 /* A "Transfer Pad" operation complete */ 302 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 303 NCR_READ_REG(sc, NCR_TCL) | 304 (NCR_READ_REG(sc, NCR_TCM) << 8), 305 NCR_READ_REG(sc, NCR_TCL), 306 NCR_READ_REG(sc, NCR_TCM))); 307 308 return 0; 309 } 310 311 resid = 0; 312 313 /* 314 * If a transfer onto the SCSI bus gets interrupted by the device 315 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 316 * as residual since the ESP counter registers get decremented as 317 * bytes are clocked into the FIFO. 318 */ 319 if (!datain && 320 (resid = (asc_read_reg(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 321 NCR_DMA(("asc_dma_intr: empty asc FIFO of %d ", resid)); 322 } 323 324 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 325 /* 326 * `Terminal count' is off, so read the residue 327 * out of the ASC counter registers. 328 */ 329 resid += (NCR_READ_REG(sc, NCR_TCL) | 330 (NCR_READ_REG(sc, NCR_TCM) << 8) | 331 ((sc->sc_cfg2 & NCRCFG2_FE) 332 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 333 334 if (resid == 0 && asc->sc_dmasize == 65536 && 335 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 336 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 337 resid = 65536; 338 } 339 340 /* halt DMA */ 341 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_COUNT, 0); 342 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 343 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 344 345 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 346 0, asc->sc_dmamap->dm_mapsize, 347 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 348 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 349 350 trans = asc->sc_dmasize - resid; 351 352 if (trans < 0) { /* transfered < 0 ? */ 353 #if 0 354 /* 355 * This situation can happen in perfectly normal operation 356 * if the ESP is reselected while using DMA to select 357 * another target. As such, don't print the warning. 358 */ 359 printf("%s: xfer (%d) > req (%d)\n", 360 sc->sc_dev.dv_xname, trans, asc->sc_dmasize); 361 #endif 362 trans = asc->sc_dmasize; 363 } 364 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 365 NCR_READ_REG(sc, NCR_TCL), 366 NCR_READ_REG(sc, NCR_TCM), 367 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 368 trans, resid)); 369 370 *asc->sc_dmalen -= trans; 371 *asc->sc_dmaaddr += trans; 372 373 return 0; 374 } 375 376 int 377 asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 378 int datain, size_t *dmasize) 379 { 380 struct asc_softc *asc = (struct asc_softc *)sc; 381 382 /* halt DMA */ 383 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 384 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 385 386 asc->sc_dmaaddr = addr; 387 asc->sc_dmalen = len; 388 asc->sc_dmasize = *dmasize; 389 asc->sc_datain = datain; 390 391 /* 392 * No need to set up DMA in `Transfer Pad' operation. 393 */ 394 if (*dmasize == 0) 395 return 0; 396 397 bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, *len, NULL, 398 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 399 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 400 (datain ? BUS_DMA_READ : BUS_DMA_WRITE)); 401 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 402 0, asc->sc_dmamap->dm_mapsize, 403 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 404 405 /* load transfer parameters */ 406 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 407 R4030_DMA_ADDR, asc->sc_dmamap->dm_segs[0].ds_addr); 408 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 409 R4030_DMA_COUNT, asc->sc_dmamap->dm_segs[0].ds_len); 410 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 411 R4030_DMA_MODE, R4030_DMA_MODE_160NS | R4030_DMA_MODE_16); 412 413 /* start DMA */ 414 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 415 R4030_DMA_ENAB, R4030_DMA_ENAB_RUN | 416 (asc->sc_datain ? R4030_DMA_ENAB_READ : R4030_DMA_ENAB_WRITE)); 417 418 return 0; 419 } 420 421 void 422 asc_dma_go(struct ncr53c9x_softc *sc) 423 { 424 struct asc_softc *asc = (struct asc_softc *)sc; 425 426 /* No DMA transfer in Transfer Pad operation */ 427 if (asc->sc_dmasize == 0) 428 return; 429 430 asc->sc_active = 1; 431 } 432 433 void 434 asc_dma_stop(struct ncr53c9x_softc *sc) 435 { 436 struct asc_softc *asc = (struct asc_softc *)sc; 437 438 /* halt DMA */ 439 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 440 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 441 442 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 443 444 asc->sc_active = 0; 445 } 446 447 int 448 asc_dma_isactive(struct ncr53c9x_softc *sc) 449 { 450 struct asc_softc *asc = (struct asc_softc *)sc; 451 452 return asc->sc_active; 453 } 454
Indexes created Thu Oct 02 14:10:14 GMT 2025