asc.c revision 1.18
1 /* $NetBSD: asc.c,v 1.18 2006/04/15 12:41:45 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Izumi Tsutsui. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: asc.c,v 1.18 2006/04/15 12:41:45 tsutsui Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/buf.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/bus.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <arc/jazz/jazziovar.h> 48 #include <arc/jazz/dma.h> 49 #include <arc/jazz/pica.h> 50 51 #include <dev/ic/ncr53c9xreg.h> 52 #include <dev/ic/ncr53c9xvar.h> 53 54 #define ASC_NPORTS 0x10 55 #define ASC_ID_53CF94 0xa2 /* XXX should be in MI ncr53c9xreg.h? */ 56 #define ASC_ID_FAS216 0x12 /* XXX should be in MI ncr53c9xreg.h? */ 57 58 struct asc_softc { 59 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 60 61 bus_space_tag_t sc_iot; /* bus space tag */ 62 bus_space_handle_t sc_ioh; /* bus space handle */ 63 bus_space_handle_t sc_dmaioh; /* bus space handle for DMAC */ 64 65 bus_dma_tag_t sc_dmat; /* DMA tag */ 66 bus_dmamap_t sc_dmamap; /* DMA map for transfers */ 67 68 int sc_active; /* DMA state */ 69 int sc_datain; /* DMA Data Direction */ 70 size_t sc_dmasize; /* DMA size */ 71 char **sc_dmaaddr; /* DMA address */ 72 size_t *sc_dmalen; /* DMA length */ 73 }; 74 75 /* 76 * Autoconfiguration data for config. 77 */ 78 int asc_match(struct device *, struct cfdata *, void *); 79 void asc_attach(struct device *, struct device *, void *); 80 81 CFATTACH_DECL(asc, sizeof(struct asc_softc), 82 asc_match, asc_attach, NULL, NULL); 83 84 static void asc_minphys(struct buf *); 85 86 /* 87 * Functions and the switch for the MI code. 88 */ 89 u_char asc_read_reg(struct ncr53c9x_softc *, int); 90 void asc_write_reg(struct ncr53c9x_softc *, int, u_char); 91 int asc_dma_isintr(struct ncr53c9x_softc *); 92 void asc_dma_reset(struct ncr53c9x_softc *); 93 int asc_dma_intr(struct ncr53c9x_softc *); 94 int asc_dma_setup(struct ncr53c9x_softc *, caddr_t *, size_t *, int, size_t *); 95 void asc_dma_go(struct ncr53c9x_softc *); 96 void asc_dma_stop(struct ncr53c9x_softc *); 97 int asc_dma_isactive(struct ncr53c9x_softc *); 98 99 struct ncr53c9x_glue asc_glue = { 100 asc_read_reg, 101 asc_write_reg, 102 asc_dma_isintr, 103 asc_dma_reset, 104 asc_dma_intr, 105 asc_dma_setup, 106 asc_dma_go, 107 asc_dma_stop, 108 asc_dma_isactive, 109 NULL /* gl_clear_latched_intr */ 110 }; 111 112 /* 113 * Match driver based on name 114 */ 115 int 116 asc_match(struct device *parent, struct cfdata *match, void *aux) 117 { 118 struct jazzio_attach_args *ja = aux; 119 120 if (strcmp(ja->ja_name, "ESP216") != 0) 121 return 0; 122 return 1; 123 } 124 125 void 126 asc_attach(struct device *parent, struct device *self, void *aux) 127 { 128 struct jazzio_attach_args *ja = aux; 129 struct asc_softc *asc = (void *)self; 130 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 131 bus_space_tag_t iot; 132 uint8_t asc_id; 133 134 #if 0 135 /* Need info from platform dependent config?? */ 136 if (asc_conf == NULL) 137 panic("asc_conf isn't initialized"); 138 #endif 139 140 sc->sc_glue = &asc_glue; 141 142 asc->sc_iot = iot = ja->ja_bust; 143 asc->sc_dmat = ja->ja_dmat; 144 145 if (bus_space_map(iot, ja->ja_addr, ASC_NPORTS, 0, &asc->sc_ioh)) { 146 printf(": unable to map I/O space\n"); 147 return; 148 } 149 150 if (bus_space_map(iot, R4030_SYS_DMA0_REGS, R4030_DMA_RANGE, 151 0, &asc->sc_dmaioh)) { 152 printf(": unable to map DMA I/O space\n"); 153 goto out1; 154 } 155 156 if (bus_dmamap_create(asc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 157 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &asc->sc_dmamap)) { 158 printf(": unable to create DMA map\n"); 159 goto out2; 160 } 161 162 /* 163 * XXX More of this should be in ncr53c9x_attach(), but 164 * XXX should we really poke around the chip that much in 165 * XXX the MI code? Think about this more... 166 */ 167 168 /* 169 * Set up static configuration info. 170 */ 171 sc->sc_id = 7; /* XXX should be taken from ARC BIOS */ 172 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 173 174 /* identify 53CF9x-2 or not */ 175 asc_write_reg(sc, NCR_CMD, NCRCMD_RSTCHIP); 176 DELAY(25); 177 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 178 DELAY(25); 179 asc_write_reg(sc, NCR_CFG2, NCRCFG2_FE); 180 DELAY(25); 181 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 182 DELAY(25); 183 asc_id = asc_read_reg(sc, NCR_TCH); 184 if (asc_id == ASC_ID_53CF94 || asc_id == ASC_ID_FAS216) { 185 /* XXX should be have NCR_VARIANT_NCR53CF94? */ 186 sc->sc_rev = NCR_VARIANT_NCR53C94; 187 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 188 sc->sc_cfg3 = NCRF9XCFG3_IDM | NCRF9XCFG3_FCLK; 189 sc->sc_features = NCR_F_FASTSCSI; 190 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 191 sc->sc_freq = 40; /* MHz */ 192 sc->sc_maxxfer = 16 * 1024 * 1024; 193 } else { 194 sc->sc_rev = NCR_VARIANT_NCR53C94; 195 sc->sc_freq = 25; /* MHz */ 196 sc->sc_maxxfer = 64 * 1024; 197 } 198 199 /* 200 * XXX minsync and maxxfer _should_ be set up in MI code, 201 * XXX but it appears to have some dependency on what sort 202 * XXX of DMA we're hooked up to, etc. 203 */ 204 205 /* 206 * This is the value used to start sync negotiations 207 * Note that the NCR register "SYNCTP" is programmed 208 * in "clocks per byte", and has a minimum value of 4. 209 * The SCSI period used in negotiation is one-fourth 210 * of the time (in nanoseconds) needed to transfer one byte. 211 * Since the chip's clock is given in MHz, we have the following 212 * formula: 4 * period = (1000 / freq) * 4 213 */ 214 sc->sc_minsync = 1000 / sc->sc_freq; 215 216 /* establish interrupt */ 217 jazzio_intr_establish(ja->ja_intr, ncr53c9x_intr, asc); 218 219 /* Do the common parts of attachment. */ 220 sc->sc_adapter.adapt_minphys = asc_minphys; 221 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 222 ncr53c9x_attach(sc); 223 224 #if 0 225 /* Turn on target selection using the `DMA' method */ 226 sc->sc_features |= NCR_F_DMASELECT; 227 #endif 228 return; 229 230 out2: 231 bus_space_unmap(iot, asc->sc_dmaioh, R4030_DMA_RANGE); 232 out1: 233 bus_space_unmap(iot, asc->sc_ioh, ASC_NPORTS); 234 } 235 236 237 static void 238 asc_minphys(struct buf *bp) 239 { 240 241 #define ASC_MAX_XFER (32 * 1024) /* XXX can't xfer 64kbytes? */ 242 243 if (bp->b_bcount > ASC_MAX_XFER) 244 bp->b_bcount = ASC_MAX_XFER; 245 minphys(bp); 246 } 247 248 /* 249 * Glue functions. 250 */ 251 252 u_char 253 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 254 { 255 struct asc_softc *asc = (struct asc_softc *)sc; 256 257 return bus_space_read_1(asc->sc_iot, asc->sc_ioh, reg); 258 } 259 260 void 261 asc_write_reg(struct ncr53c9x_softc *sc, int reg, u_char val) 262 { 263 struct asc_softc *asc = (struct asc_softc *)sc; 264 265 bus_space_write_1(asc->sc_iot, asc->sc_ioh, reg, val); 266 } 267 268 int 269 asc_dma_isintr(struct ncr53c9x_softc *sc) 270 { 271 272 return asc_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 273 } 274 275 void 276 asc_dma_reset(struct ncr53c9x_softc *sc) 277 { 278 struct asc_softc *asc = (struct asc_softc *)sc; 279 280 /* halt DMA */ 281 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 282 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 283 } 284 285 int 286 asc_dma_intr(struct ncr53c9x_softc *sc) 287 { 288 struct asc_softc *asc = (struct asc_softc *)sc; 289 int datain, resid, trans; 290 291 datain = asc->sc_datain; 292 293 #ifdef DIAGNOSTIC 294 /* This is an "assertion" :) */ 295 if (asc->sc_active == 0) 296 panic("asc_dma_intr: DMA wasn't active"); 297 #endif 298 299 /* DMA has stopped */ 300 301 asc->sc_active = 0; 302 303 if (asc->sc_dmasize == 0) { 304 /* A "Transfer Pad" operation complete */ 305 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 306 NCR_READ_REG(sc, NCR_TCL) | 307 (NCR_READ_REG(sc, NCR_TCM) << 8), 308 NCR_READ_REG(sc, NCR_TCL), 309 NCR_READ_REG(sc, NCR_TCM))); 310 311 return 0; 312 } 313 314 resid = 0; 315 316 /* 317 * If a transfer onto the SCSI bus gets interrupted by the device 318 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 319 * as residual since the ESP counter registers get decremented as 320 * bytes are clocked into the FIFO. 321 */ 322 if (!datain && 323 (resid = (asc_read_reg(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 324 NCR_DMA(("asc_dma_intr: empty asc FIFO of %d ", resid)); 325 } 326 327 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 328 /* 329 * `Terminal count' is off, so read the residue 330 * out of the ASC counter registers. 331 */ 332 resid += (NCR_READ_REG(sc, NCR_TCL) | 333 (NCR_READ_REG(sc, NCR_TCM) << 8) | 334 ((sc->sc_cfg2 & NCRCFG2_FE) 335 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 336 337 if (resid == 0 && asc->sc_dmasize == 65536 && 338 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 339 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 340 resid = 65536; 341 } 342 343 /* halt DMA */ 344 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_COUNT, 0); 345 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 346 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 347 348 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 349 0, asc->sc_dmamap->dm_mapsize, 350 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 351 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 352 353 trans = asc->sc_dmasize - resid; 354 355 if (trans < 0) { /* transfered < 0 ? */ 356 #if 0 357 /* 358 * This situation can happen in perfectly normal operation 359 * if the ESP is reselected while using DMA to select 360 * another target. As such, don't print the warning. 361 */ 362 printf("%s: xfer (%d) > req (%d)\n", 363 sc->sc_dev.dv_xname, trans, asc->sc_dmasize); 364 #endif 365 trans = asc->sc_dmasize; 366 } 367 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 368 NCR_READ_REG(sc, NCR_TCL), 369 NCR_READ_REG(sc, NCR_TCM), 370 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 371 trans, resid)); 372 373 *asc->sc_dmalen -= trans; 374 *asc->sc_dmaaddr += trans; 375 376 return 0; 377 } 378 379 int 380 asc_dma_setup(struct ncr53c9x_softc *sc, caddr_t *addr, size_t *len, 381 int datain, size_t *dmasize) 382 { 383 struct asc_softc *asc = (struct asc_softc *)sc; 384 385 /* halt DMA */ 386 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 387 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 388 389 asc->sc_dmaaddr = addr; 390 asc->sc_dmalen = len; 391 asc->sc_dmasize = *dmasize; 392 asc->sc_datain = datain; 393 394 /* 395 * No need to set up DMA in `Transfer Pad' operation. 396 */ 397 if (*dmasize == 0) 398 return 0; 399 400 bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, *len, NULL, 401 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 402 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 403 (datain ? BUS_DMA_READ : BUS_DMA_WRITE)); 404 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 405 0, asc->sc_dmamap->dm_mapsize, 406 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 407 408 /* load transfer parameters */ 409 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 410 R4030_DMA_ADDR, asc->sc_dmamap->dm_segs[0].ds_addr); 411 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 412 R4030_DMA_COUNT, asc->sc_dmamap->dm_segs[0].ds_len); 413 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 414 R4030_DMA_MODE, R4030_DMA_MODE_160NS | R4030_DMA_MODE_16); 415 416 /* start DMA */ 417 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 418 R4030_DMA_ENAB, R4030_DMA_ENAB_RUN | 419 (asc->sc_datain ? R4030_DMA_ENAB_READ : R4030_DMA_ENAB_WRITE)); 420 421 return 0; 422 } 423 424 void 425 asc_dma_go(struct ncr53c9x_softc *sc) 426 { 427 struct asc_softc *asc = (struct asc_softc *)sc; 428 429 /* No DMA transfer in Transfer Pad operation */ 430 if (asc->sc_dmasize == 0) 431 return; 432 433 asc->sc_active = 1; 434 } 435 436 void 437 asc_dma_stop(struct ncr53c9x_softc *sc) 438 { 439 struct asc_softc *asc = (struct asc_softc *)sc; 440 441 /* halt DMA */ 442 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 443 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 444 445 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 446 447 asc->sc_active = 0; 448 } 449 450 int 451 asc_dma_isactive(struct ncr53c9x_softc *sc) 452 { 453 struct asc_softc *asc = (struct asc_softc *)sc; 454 455 return asc->sc_active; 456 } 457
Indexes created Thu Oct 02 14:10:14 GMT 2025