asc.c revision 1.22
1 /* $NetBSD: asc.c,v 1.22 2008/04/13 04:55:52 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 2003 Izumi Tsutsui. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30 #include <sys/cdefs.h> 31 __KERNEL_RCSID(0, "$NetBSD: asc.c,v 1.22 2008/04/13 04:55:52 tsutsui Exp $"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/device.h> 36 #include <sys/buf.h> 37 38 #include <machine/autoconf.h> 39 #include <machine/bus.h> 40 41 #include <uvm/uvm_extern.h> 42 43 #include <dev/scsipi/scsipi_all.h> 44 #include <dev/scsipi/scsi_all.h> 45 #include <dev/scsipi/scsiconf.h> 46 47 #include <arc/jazz/jazziovar.h> 48 #include <arc/jazz/dma.h> 49 #include <arc/jazz/pica.h> 50 51 #include <dev/ic/ncr53c9xreg.h> 52 #include <dev/ic/ncr53c9xvar.h> 53 54 #define ASC_NPORTS 0x10 55 #define ASC_ID_53CF94 0xa2 /* XXX should be in MI ncr53c9xreg.h? */ 56 #define ASC_ID_FAS216 0x12 /* XXX should be in MI ncr53c9xreg.h? */ 57 58 struct asc_softc { 59 struct ncr53c9x_softc sc_ncr53c9x; /* glue to MI code */ 60 61 bus_space_tag_t sc_iot; /* bus space tag */ 62 bus_space_handle_t sc_ioh; /* bus space handle */ 63 bus_space_handle_t sc_dmaioh; /* bus space handle for DMAC */ 64 65 bus_dma_tag_t sc_dmat; /* DMA tag */ 66 bus_dmamap_t sc_dmamap; /* DMA map for transfers */ 67 68 int sc_active; /* DMA state */ 69 int sc_datain; /* DMA Data Direction */ 70 size_t sc_dmasize; /* DMA size */ 71 uint8_t **sc_dmaaddr; /* DMA address */ 72 size_t *sc_dmalen; /* DMA length */ 73 }; 74 75 /* 76 * Autoconfiguration data for config. 77 */ 78 int asc_match(device_t, cfdata_t, void *); 79 void asc_attach(device_t, device_t, void *); 80 81 CFATTACH_DECL_NEW(asc, sizeof(struct asc_softc), 82 asc_match, asc_attach, NULL, NULL); 83 84 static void asc_minphys(struct buf *); 85 86 /* 87 * Functions and the switch for the MI code. 88 */ 89 uint8_t asc_read_reg(struct ncr53c9x_softc *, int); 90 void asc_write_reg(struct ncr53c9x_softc *, int, uint8_t); 91 int asc_dma_isintr(struct ncr53c9x_softc *); 92 void asc_dma_reset(struct ncr53c9x_softc *); 93 int asc_dma_intr(struct ncr53c9x_softc *); 94 int asc_dma_setup(struct ncr53c9x_softc *, uint8_t **, size_t *, int, size_t *); 95 void asc_dma_go(struct ncr53c9x_softc *); 96 void asc_dma_stop(struct ncr53c9x_softc *); 97 int asc_dma_isactive(struct ncr53c9x_softc *); 98 99 struct ncr53c9x_glue asc_glue = { 100 asc_read_reg, 101 asc_write_reg, 102 asc_dma_isintr, 103 asc_dma_reset, 104 asc_dma_intr, 105 asc_dma_setup, 106 asc_dma_go, 107 asc_dma_stop, 108 asc_dma_isactive, 109 NULL /* gl_clear_latched_intr */ 110 }; 111 112 /* 113 * Match driver based on name 114 */ 115 int 116 asc_match(device_t parent, cfdata_t cf, void *aux) 117 { 118 struct jazzio_attach_args *ja = aux; 119 120 if (strcmp(ja->ja_name, "ESP216") != 0) 121 return 0; 122 return 1; 123 } 124 125 void 126 asc_attach(device_t parent, device_t self, void *aux) 127 { 128 struct asc_softc *asc = device_private(self); 129 struct ncr53c9x_softc *sc = &asc->sc_ncr53c9x; 130 struct jazzio_attach_args *ja = aux; 131 bus_space_tag_t iot; 132 uint8_t asc_id; 133 134 #if 0 135 /* Need info from platform dependent config?? */ 136 if (asc_conf == NULL) 137 panic("asc_conf isn't initialized"); 138 #endif 139 140 sc->sc_dev = self; 141 sc->sc_glue = &asc_glue; 142 143 asc->sc_iot = iot = ja->ja_bust; 144 asc->sc_dmat = ja->ja_dmat; 145 146 if (bus_space_map(iot, ja->ja_addr, ASC_NPORTS, 0, &asc->sc_ioh)) { 147 aprint_error(": unable to map I/O space\n"); 148 return; 149 } 150 151 if (bus_space_map(iot, R4030_SYS_DMA0_REGS, R4030_DMA_RANGE, 152 0, &asc->sc_dmaioh)) { 153 aprint_error(": unable to map DMA I/O space\n"); 154 goto out1; 155 } 156 157 if (bus_dmamap_create(asc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 158 BUS_DMA_ALLOCNOW | BUS_DMA_NOWAIT, &asc->sc_dmamap)) { 159 aprint_error(": unable to create DMA map\n"); 160 goto out2; 161 } 162 163 /* 164 * XXX More of this should be in ncr53c9x_attach(), but 165 * XXX should we really poke around the chip that much in 166 * XXX the MI code? Think about this more... 167 */ 168 169 /* 170 * Set up static configuration info. 171 */ 172 sc->sc_id = 7; /* XXX should be taken from ARC BIOS */ 173 sc->sc_cfg1 = sc->sc_id | NCRCFG1_PARENB; 174 175 /* identify 53CF9x-2 or not */ 176 asc_write_reg(sc, NCR_CMD, NCRCMD_RSTCHIP); 177 DELAY(25); 178 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 179 DELAY(25); 180 asc_write_reg(sc, NCR_CFG2, NCRCFG2_FE); 181 DELAY(25); 182 asc_write_reg(sc, NCR_CMD, NCRCMD_DMA | NCRCMD_NOP); 183 DELAY(25); 184 asc_id = asc_read_reg(sc, NCR_TCH); 185 if (asc_id == ASC_ID_53CF94 || asc_id == ASC_ID_FAS216) { 186 /* XXX should be have NCR_VARIANT_NCR53CF94? */ 187 sc->sc_rev = NCR_VARIANT_NCR53C94; 188 sc->sc_cfg2 = NCRCFG2_SCSI2 | NCRCFG2_FE; 189 sc->sc_cfg3 = NCRF9XCFG3_IDM | NCRF9XCFG3_FCLK; 190 sc->sc_features = NCR_F_FASTSCSI; 191 sc->sc_cfg3_fscsi = NCRF9XCFG3_FSCSI; 192 sc->sc_freq = 40; /* MHz */ 193 sc->sc_maxxfer = 16 * 1024 * 1024; 194 } else { 195 sc->sc_rev = NCR_VARIANT_NCR53C94; 196 sc->sc_freq = 25; /* MHz */ 197 sc->sc_maxxfer = 64 * 1024; 198 } 199 200 /* 201 * XXX minsync and maxxfer _should_ be set up in MI code, 202 * XXX but it appears to have some dependency on what sort 203 * XXX of DMA we're hooked up to, etc. 204 */ 205 206 /* 207 * This is the value used to start sync negotiations 208 * Note that the NCR register "SYNCTP" is programmed 209 * in "clocks per byte", and has a minimum value of 4. 210 * The SCSI period used in negotiation is one-fourth 211 * of the time (in nanoseconds) needed to transfer one byte. 212 * Since the chip's clock is given in MHz, we have the following 213 * formula: 4 * period = (1000 / freq) * 4 214 */ 215 sc->sc_minsync = 1000 / sc->sc_freq; 216 217 /* establish interrupt */ 218 jazzio_intr_establish(ja->ja_intr, ncr53c9x_intr, asc); 219 220 /* Do the common parts of attachment. */ 221 sc->sc_adapter.adapt_minphys = asc_minphys; 222 sc->sc_adapter.adapt_request = ncr53c9x_scsipi_request; 223 ncr53c9x_attach(sc); 224 225 #if 0 226 /* Turn on target selection using the `DMA' method */ 227 sc->sc_features |= NCR_F_DMASELECT; 228 #endif 229 return; 230 231 out2: 232 bus_space_unmap(iot, asc->sc_dmaioh, R4030_DMA_RANGE); 233 out1: 234 bus_space_unmap(iot, asc->sc_ioh, ASC_NPORTS); 235 } 236 237 238 static void 239 asc_minphys(struct buf *bp) 240 { 241 242 #define ASC_MAX_XFER (32 * 1024) /* XXX can't xfer 64kbytes? */ 243 244 if (bp->b_bcount > ASC_MAX_XFER) 245 bp->b_bcount = ASC_MAX_XFER; 246 minphys(bp); 247 } 248 249 /* 250 * Glue functions. 251 */ 252 253 uint8_t 254 asc_read_reg(struct ncr53c9x_softc *sc, int reg) 255 { 256 struct asc_softc *asc = (struct asc_softc *)sc; 257 258 return bus_space_read_1(asc->sc_iot, asc->sc_ioh, reg); 259 } 260 261 void 262 asc_write_reg(struct ncr53c9x_softc *sc, int reg, uint8_t val) 263 { 264 struct asc_softc *asc = (struct asc_softc *)sc; 265 266 bus_space_write_1(asc->sc_iot, asc->sc_ioh, reg, val); 267 } 268 269 int 270 asc_dma_isintr(struct ncr53c9x_softc *sc) 271 { 272 273 return asc_read_reg(sc, NCR_STAT) & NCRSTAT_INT; 274 } 275 276 void 277 asc_dma_reset(struct ncr53c9x_softc *sc) 278 { 279 struct asc_softc *asc = (struct asc_softc *)sc; 280 281 /* halt DMA */ 282 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 283 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 284 } 285 286 int 287 asc_dma_intr(struct ncr53c9x_softc *sc) 288 { 289 struct asc_softc *asc = (struct asc_softc *)sc; 290 int datain, resid, trans; 291 292 datain = asc->sc_datain; 293 294 #ifdef DIAGNOSTIC 295 /* This is an "assertion" :) */ 296 if (asc->sc_active == 0) 297 panic("%s: DMA wasn't active", __func__); 298 #endif 299 300 /* DMA has stopped */ 301 302 asc->sc_active = 0; 303 304 if (asc->sc_dmasize == 0) { 305 /* A "Transfer Pad" operation complete */ 306 NCR_DMA(("dmaintr: discarded %d bytes (tcl=%d, tcm=%d)\n", 307 NCR_READ_REG(sc, NCR_TCL) | 308 (NCR_READ_REG(sc, NCR_TCM) << 8), 309 NCR_READ_REG(sc, NCR_TCL), 310 NCR_READ_REG(sc, NCR_TCM))); 311 312 return 0; 313 } 314 315 resid = 0; 316 317 /* 318 * If a transfer onto the SCSI bus gets interrupted by the device 319 * (e.g. for a SAVEPOINTER message), the data in the FIFO counts 320 * as residual since the ESP counter registers get decremented as 321 * bytes are clocked into the FIFO. 322 */ 323 if (!datain && 324 (resid = (asc_read_reg(sc, NCR_FFLAG) & NCRFIFO_FF)) != 0) { 325 NCR_DMA(("asc_dma_intr: empty asc FIFO of %d ", resid)); 326 } 327 328 if ((sc->sc_espstat & NCRSTAT_TC) == 0) { 329 /* 330 * `Terminal count' is off, so read the residue 331 * out of the ASC counter registers. 332 */ 333 resid += (NCR_READ_REG(sc, NCR_TCL) | 334 (NCR_READ_REG(sc, NCR_TCM) << 8) | 335 ((sc->sc_cfg2 & NCRCFG2_FE) 336 ? (NCR_READ_REG(sc, NCR_TCH) << 16) : 0)); 337 338 if (resid == 0 && asc->sc_dmasize == 65536 && 339 (sc->sc_cfg2 & NCRCFG2_FE) == 0) 340 /* A transfer of 64K is encoded as `TCL=TCM=0' */ 341 resid = 65536; 342 } 343 344 /* halt DMA */ 345 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_COUNT, 0); 346 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 347 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 348 349 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 350 0, asc->sc_dmamap->dm_mapsize, 351 datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 352 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 353 354 trans = asc->sc_dmasize - resid; 355 356 if (trans < 0) { /* transfered < 0 ? */ 357 #if 0 358 /* 359 * This situation can happen in perfectly normal operation 360 * if the ESP is reselected while using DMA to select 361 * another target. As such, don't print the warning. 362 */ 363 printf("%s: xfer (%d) > req (%d)\n", 364 sc->sc_dev.dv_xname, trans, asc->sc_dmasize); 365 #endif 366 trans = asc->sc_dmasize; 367 } 368 NCR_DMA(("dmaintr: tcl=%d, tcm=%d, tch=%d; trans=%d, resid=%d\n", 369 NCR_READ_REG(sc, NCR_TCL), 370 NCR_READ_REG(sc, NCR_TCM), 371 (sc->sc_cfg2 & NCRCFG2_FE) ? NCR_READ_REG(sc, NCR_TCH) : 0, 372 trans, resid)); 373 374 *asc->sc_dmalen -= trans; 375 *asc->sc_dmaaddr += trans; 376 377 return 0; 378 } 379 380 int 381 asc_dma_setup(struct ncr53c9x_softc *sc, uint8_t **addr, size_t *len, 382 int datain, size_t *dmasize) 383 { 384 struct asc_softc *asc = (struct asc_softc *)sc; 385 386 /* halt DMA */ 387 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 388 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 389 390 asc->sc_dmaaddr = addr; 391 asc->sc_dmalen = len; 392 asc->sc_dmasize = *dmasize; 393 asc->sc_datain = datain; 394 395 /* 396 * No need to set up DMA in `Transfer Pad' operation. 397 */ 398 if (*dmasize == 0) 399 return 0; 400 401 bus_dmamap_load(asc->sc_dmat, asc->sc_dmamap, *addr, *len, NULL, 402 ((sc->sc_nexus->xs->xs_control & XS_CTL_NOSLEEP) ? 403 BUS_DMA_NOWAIT : BUS_DMA_WAITOK) | BUS_DMA_STREAMING | 404 (datain ? BUS_DMA_READ : BUS_DMA_WRITE)); 405 bus_dmamap_sync(asc->sc_dmat, asc->sc_dmamap, 406 0, asc->sc_dmamap->dm_mapsize, 407 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 408 409 /* load transfer parameters */ 410 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 411 R4030_DMA_ADDR, asc->sc_dmamap->dm_segs[0].ds_addr); 412 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 413 R4030_DMA_COUNT, asc->sc_dmamap->dm_segs[0].ds_len); 414 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 415 R4030_DMA_MODE, R4030_DMA_MODE_160NS | R4030_DMA_MODE_16); 416 417 /* start DMA */ 418 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, 419 R4030_DMA_ENAB, R4030_DMA_ENAB_RUN | 420 (asc->sc_datain ? R4030_DMA_ENAB_READ : R4030_DMA_ENAB_WRITE)); 421 422 return 0; 423 } 424 425 void 426 asc_dma_go(struct ncr53c9x_softc *sc) 427 { 428 struct asc_softc *asc = (struct asc_softc *)sc; 429 430 /* No DMA transfer in Transfer Pad operation */ 431 if (asc->sc_dmasize == 0) 432 return; 433 434 asc->sc_active = 1; 435 } 436 437 void 438 asc_dma_stop(struct ncr53c9x_softc *sc) 439 { 440 struct asc_softc *asc = (struct asc_softc *)sc; 441 442 /* halt DMA */ 443 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_ENAB, 0); 444 bus_space_write_4(asc->sc_iot, asc->sc_dmaioh, R4030_DMA_MODE, 0); 445 446 bus_dmamap_unload(asc->sc_dmat, asc->sc_dmamap); 447 448 asc->sc_active = 0; 449 } 450 451 int 452 asc_dma_isactive(struct ncr53c9x_softc *sc) 453 { 454 struct asc_softc *asc = (struct asc_softc *)sc; 455 456 return asc->sc_active; 457 } 458
Indexes created Thu Oct 02 14:10:14 GMT 2025