dma.h revision 1.2.6.2
1 1.2.6.2 tsutsui /* $NetBSD: dma.h,v 1.2.6.2 2001/07/24 16:26:54 tsutsui Exp $ */ 2 1.2.6.2 tsutsui /* $OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $ */ 3 1.2.6.2 tsutsui 4 1.2.6.2 tsutsui /* 5 1.2.6.2 tsutsui * Copyright (c) 1996 Per Fogelstrom 6 1.2.6.2 tsutsui * All rights reserved. 7 1.2.6.2 tsutsui * 8 1.2.6.2 tsutsui * Redistribution and use in source and binary forms, with or without 9 1.2.6.2 tsutsui * modification, are permitted provided that the following conditions 10 1.2.6.2 tsutsui * are met: 11 1.2.6.2 tsutsui * 1. Redistributions of source code must retain the above copyright 12 1.2.6.2 tsutsui * notice, this list of conditions and the following disclaimer. 13 1.2.6.2 tsutsui * 2. Redistributions in binary form must reproduce the above copyright 14 1.2.6.2 tsutsui * notice, this list of conditions and the following disclaimer in the 15 1.2.6.2 tsutsui * documentation and/or other materials provided with the distribution. 16 1.2.6.2 tsutsui * 3. All advertising materials mentioning features or use of this software 17 1.2.6.2 tsutsui * must display the following acknowledgement: 18 1.2.6.2 tsutsui * This product includes software developed by Per Fogelstrom. 19 1.2.6.2 tsutsui * 4. The name of the author may not be used to endorse or promote products 20 1.2.6.2 tsutsui * derived from this software without specific prior written permission 21 1.2.6.2 tsutsui * 22 1.2.6.2 tsutsui * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 1.2.6.2 tsutsui * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 1.2.6.2 tsutsui * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 1.2.6.2 tsutsui * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 1.2.6.2 tsutsui * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 1.2.6.2 tsutsui * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 1.2.6.2 tsutsui * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 1.2.6.2 tsutsui * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 1.2.6.2 tsutsui * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 1.2.6.2 tsutsui * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 1.2.6.2 tsutsui */ 33 1.2.6.2 tsutsui 34 1.2.6.2 tsutsui /* 35 1.2.6.2 tsutsui * Hardware dma registers. 36 1.2.6.2 tsutsui */ 37 1.2.6.2 tsutsui typedef volatile struct { 38 1.2.6.2 tsutsui int32_t dma_mode; 39 1.2.6.2 tsutsui int32_t pad1; 40 1.2.6.2 tsutsui int32_t dma_enab; 41 1.2.6.2 tsutsui int32_t pad2; 42 1.2.6.2 tsutsui int32_t dma_count; 43 1.2.6.2 tsutsui int32_t pad3; 44 1.2.6.2 tsutsui int32_t dma_addr; 45 1.2.6.2 tsutsui int32_t pad4; 46 1.2.6.2 tsutsui } DmaReg, *pDmaReg; 47 1.2.6.2 tsutsui 48 1.2.6.2 tsutsui #define R4030_DMA_MODE_40NS 0x00 /* Device dma timing */ 49 1.2.6.2 tsutsui #define R4030_DMA_MODE_80NS 0x01 /* Device dma timing */ 50 1.2.6.2 tsutsui #define R4030_DMA_MODE_120NS 0x02 /* Device dma timing */ 51 1.2.6.2 tsutsui #define R4030_DMA_MODE_160NS 0x03 /* Device dma timing */ 52 1.2.6.2 tsutsui #define R4030_DMA_MODE_200NS 0x04 /* Device dma timing */ 53 1.2.6.2 tsutsui #define R4030_DMA_MODE_240NS 0x05 /* Device dma timing */ 54 1.2.6.2 tsutsui #define R4030_DMA_MODE_280NS 0x06 /* Device dma timing */ 55 1.2.6.2 tsutsui #define R4030_DMA_MODE_320NS 0x07 /* Device dma timing */ 56 1.2.6.2 tsutsui #define R4030_DMA_MODE_8 0x08 /* Device 8 bit */ 57 1.2.6.2 tsutsui #define R4030_DMA_MODE_16 0x10 /* Device 16 bit */ 58 1.2.6.2 tsutsui #define R4030_DMA_MODE_32 0x18 /* Device 32 bit */ 59 1.2.6.2 tsutsui #define R4030_DMA_MODE_INT 0x20 /* Interrupt when done */ 60 1.2.6.2 tsutsui #define R4030_DMA_MODE_BURST 0x40 /* Burst mode (Rev 2 only) */ 61 1.2.6.2 tsutsui #define R4030_DMA_MODE_FAST 0x80 /* Fast dma cycle (Rev 2 only) */ 62 1.2.6.2 tsutsui #define R4030_DMA_MODE 0xff /* Mode register bits */ 63 1.2.6.2 tsutsui #define DMA_DIR_WRITE 0x100 /* Software direction status */ 64 1.2.6.2 tsutsui #define DMA_DIR_READ 0x000 /* Software direction status */ 65 1.2.6.2 tsutsui 66 1.2.6.2 tsutsui #define R4030_DMA_ENAB_RUN 0x01 /* Enable dma */ 67 1.2.6.2 tsutsui #define R4030_DMA_ENAB_READ 0x00 /* Read from device */ 68 1.2.6.2 tsutsui #define R4030_DMA_ENAB_WRITE 0x02 /* Write to device */ 69 1.2.6.2 tsutsui #define R4030_DMA_ENAB_TC_IE 0x100 /* Terminal count int enable */ 70 1.2.6.2 tsutsui #define R4030_DMA_ENAB_ME_IE 0x200 /* Memory error int enable */ 71 1.2.6.2 tsutsui #define R4030_DMA_ENAB_TL_IE 0x400 /* Translation limit int enable */ 72 1.2.6.2 tsutsui 73 1.2.6.2 tsutsui #define R4030_DMA_COUNT_MASK 0x000fffff /* Byte count mask */ 74 1.2.6.2 tsutsui 75 1.2.6.2 tsutsui /* 76 1.2.6.2 tsutsui * Structure used to control dma. 77 1.2.6.2 tsutsui */ 78 1.2.6.2 tsutsui 79 1.2.6.2 tsutsui typedef struct dma_softc { 80 1.2.6.2 tsutsui struct device sc_dev; /* use as a device */ 81 1.2.6.2 tsutsui struct esp_softc *sc_esp; 82 1.2.6.2 tsutsui bus_addr_t dma_va; /* Viritual address for transfer */ 83 1.2.6.2 tsutsui int mode; /* Mode register value and direction */ 84 1.2.6.2 tsutsui jazz_dma_pte_t *pte_base; /* Pointer to dma tlb array */ 85 1.2.6.2 tsutsui int pte_size; /* Size of pte allocated pte array */ 86 1.2.6.2 tsutsui pDmaReg dma_reg; /* Pointer to dma registers */ 87 1.2.6.2 tsutsui int sc_active; /* Active flag */ 88 1.2.6.2 tsutsui void (*reset)(struct dma_softc *); /* Reset routine pointer */ 89 1.2.6.2 tsutsui void (*enintr)(struct dma_softc *); /* Int enab routine pointer */ 90 1.2.6.2 tsutsui void (*map)(struct dma_softc *, char *, size_t, int); 91 1.2.6.2 tsutsui /* Map a dma viritual area */ 92 1.2.6.2 tsutsui void (*start)(struct dma_softc *, caddr_t, size_t, int); 93 1.2.6.2 tsutsui /* Start routine pointer */ 94 1.2.6.2 tsutsui int (*isintr)(struct dma_softc *); /* Int check routine pointer */ 95 1.2.6.2 tsutsui int (*intr)(struct dma_softc *); /* Interrupt routine pointer */ 96 1.2.6.2 tsutsui void (*end)(struct dma_softc *); /* Interrupt routine pointer */ 97 1.2.6.2 tsutsui } dma_softc_t; 98 1.2.6.2 tsutsui 99 1.2.6.2 tsutsui #define DMA_TO_DEV 0 100 1.2.6.2 tsutsui #define DMA_FROM_DEV 1 101 1.2.6.2 tsutsui 102 1.2.6.2 tsutsui #define DMA_RESET(r) ((r->reset)(r)) 103 1.2.6.2 tsutsui #define DMA_START(a, b, c, d) ((a->start)(a, b, c, d)) 104 1.2.6.2 tsutsui #define DMA_MAP(a, b, c, d) ((a->map)(a, b, c, d)) 105 1.2.6.2 tsutsui #define DMA_INTR(r) ((r->intr)(r)) 106 1.2.6.2 tsutsui #define DMA_DRAIN(r) 107 1.2.6.2 tsutsui #define DMA_END(r) ((r->end)(r)) 108 1.2.6.2 tsutsui 109 1.2.6.2 tsutsui void picaDmaInit __P((void)); 110 1.2.6.2 tsutsui void picaDmaTLBAlloc __P((dma_softc_t *)); 111 1.2.6.2 tsutsui void picaDmaTLBFree __P((dma_softc_t *)); 112 1.2.6.2 tsutsui void picaDmaMap __P((struct dma_softc *, char *, size_t, int)); 113 1.2.6.2 tsutsui void picaDmaStart __P((struct dma_softc *, char *, size_t, int)); 114 1.2.6.2 tsutsui void picaDmaFlush __P((struct dma_softc *, char *, size_t, int)); 115 1.2.6.2 tsutsui void asc_dma_init __P((struct dma_softc *)); 116 1.2.6.2 tsutsui void fdc_dma_init __P((struct dma_softc *)); 117
Indexes created Sun Oct 26 17:10:13 GMT 2025