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dma.h revision 1.1 
      1 /*	$NetBSD: dma.h,v 1.1 2000/12/24 09:25:28 ur Exp $	*/
      2 /*	$OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $	*/
      3 
      4 /*
      5  * Copyright (c) 1996 Per Fogelstrom
      6  * All rights reserved.
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  * 3. All advertising materials mentioning features or use of this software
     17  *    must display the following acknowledgement:
     18  *      This product includes software developed by Per Fogelstrom.
     19  * 4. The name of the author may not be used to endorse or promote products
     20  *    derived from this software without specific prior written permission
     21  *
     22  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     23  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     24  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     25  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     27  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     28  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     29  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     30  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     31  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     32  */
     33 
     34 /*
     35  *  Hardware dma registers.
     36  */
     37 typedef volatile struct {
     38 	int32_t		dma_mode;
     39 	int32_t		pad1;
     40 	int32_t		dma_enab;
     41 	int32_t		pad2;
     42 	int32_t		dma_count;
     43 	int32_t		pad3;
     44 	int32_t		dma_addr;
     45 	int32_t		pad4;
     46 } DmaReg, *pDmaReg;
     47 
     48 #define	R4030_DMA_MODE_40NS	0x00	/* Device dma timing */
     49 #define	R4030_DMA_MODE_80NS	0x01	/* Device dma timing */
     50 #define	R4030_DMA_MODE_120NS	0x02	/* Device dma timing */
     51 #define	R4030_DMA_MODE_160NS	0x03	/* Device dma timing */
     52 #define	R4030_DMA_MODE_200NS	0x04	/* Device dma timing */
     53 #define	R4030_DMA_MODE_240NS	0x05	/* Device dma timing */
     54 #define	R4030_DMA_MODE_280NS	0x06	/* Device dma timing */
     55 #define	R4030_DMA_MODE_320NS	0x07	/* Device dma timing */
     56 #define	R4030_DMA_MODE_8		0x08	/* Device 8 bit  */
     57 #define	R4030_DMA_MODE_16	0x10	/* Device 16 bit */
     58 #define	R4030_DMA_MODE_32	0x18	/* Device 32 bit */
     59 #define	R4030_DMA_MODE_INT	0x20	/* Interrupt when done */
     60 #define	R4030_DMA_MODE_BURST	0x40	/* Burst mode (Rev 2 only) */
     61 #define R4030_DMA_MODE_FAST	0x80	/* Fast dma cycle (Rev 2 only) */
     62 #define R4030_DMA_MODE		0xff	/* Mode register bits */
     63 #define DMA_DIR_WRITE		0x100	/* Software direction status */
     64 #define DMA_DIR_READ		0x000	/* Software direction status */
     65 
     66 #define	R4030_DMA_ENAB_RUN	0x01	/* Enable dma */
     67 #define	R4030_DMA_ENAB_READ	0x00	/* Read from device */
     68 #define	R4030_DMA_ENAB_WRITE	0x02	/* Write to device */
     69 #define	R4030_DMA_ENAB_TC_IE	0x100	/* Terminal count int enable */
     70 #define	R4030_DMA_ENAB_ME_IE	0x200	/* Memory error int enable */
     71 #define	R4030_DMA_ENAB_TL_IE	0x400	/* Translation limit int enable */
     72 
     73 #define	R4030_DMA_COUNT_MASK	0x000fffff /* Byte count mask */
     74 
     75 /*
     76  *  Structure used to control dma.
     77  */
     78 
     79 typedef struct dma_softc {
     80 	struct device	sc_dev;		/* use as a device */
     81 	struct esp_softc *sc_esp;
     82 	bus_addr_t	dma_va;		/* Viritual address for transfer */
     83 	int		mode;		/* Mode register value and direction */
     84 	jazz_dma_pte_t	*pte_base;	/* Pointer to dma tlb array */
     85 	int		pte_size;	/* Size of pte allocated pte array */
     86 	pDmaReg		dma_reg;	/* Pointer to dma registers */
     87 	int		sc_active;	/* Active flag */
     88 	void (*reset)(struct dma_softc *);	/* Reset routine pointer */
     89 	void (*enintr)(struct dma_softc *);	/* Int enab routine pointer */
     90 	void (*map)(struct dma_softc *, char *, size_t, int);
     91 						/* Map a dma viritual area */
     92 	void (*start)(struct dma_softc *, caddr_t, size_t, int);
     93 						/* Start routine pointer */
     94 	int (*isintr)(struct dma_softc *);	/* Int check routine pointer */
     95 	int (*intr)(struct dma_softc *);	/* Interrupt routine pointer */
     96 	void (*end)(struct dma_softc *);	/* Interrupt routine pointer */
     97 } dma_softc_t;
     98 
     99 #define	DMA_TO_DEV	0
    100 #define	DMA_FROM_DEV	1
    101 
    102 #define	DMA_RESET(r)		((r->reset)(r))
    103 #define	DMA_START(a, b, c, d)	((a->start)(a, b, c, d))
    104 #define	DMA_MAP(a, b, c, d)	((a->map)(a, b, c, d))
    105 #define	DMA_INTR(r)		((r->intr)(r))
    106 #define	DMA_DRAIN(r)
    107 #define	DMA_END(r)		((r->end)(r))
    108 
    109 void picaDmaInit __P((void));
    110 void picaDmaTLBAlloc __P((dma_softc_t *));
    111 void picaDmaTLBFree __P((dma_softc_t *));
    112 void picaDmaMap __P((struct dma_softc *, char *, size_t, int));
    113 void picaDmaStart __P((struct dma_softc *, char *, size_t, int));
    114 void picaDmaFlush __P((struct dma_softc *, char *, size_t, int));
    115 void asc_dma_init __P((struct dma_softc *));
    116 void fdc_dma_init __P((struct dma_softc *));
    117 void sn_dma_init __P((struct dma_softc *, int));
    118