dma.h revision 1.4
1 /* $NetBSD: dma.h,v 1.4 2003/02/10 15:19:44 tsutsui Exp $ */ 2 /* $OpenBSD: dma.h,v 1.3 1997/04/19 17:19:51 pefo Exp $ */ 3 4 /* 5 * Copyright (c) 1996 Per Fogelstrom 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Per Fogelstrom. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 /* 35 * Hardware dma registers. 36 */ 37 typedef volatile struct { 38 int32_t dma_mode; 39 int32_t pad1; 40 int32_t dma_enab; 41 int32_t pad2; 42 int32_t dma_count; 43 int32_t pad3; 44 int32_t dma_addr; 45 int32_t pad4; 46 } DmaReg, *pDmaReg; 47 48 #define R4030_DMA_MODE 0x00 49 #define R4030_DMA_MODE_40NS 0x00 /* Device dma timing */ 50 #define R4030_DMA_MODE_80NS 0x01 /* Device dma timing */ 51 #define R4030_DMA_MODE_120NS 0x02 /* Device dma timing */ 52 #define R4030_DMA_MODE_160NS 0x03 /* Device dma timing */ 53 #define R4030_DMA_MODE_200NS 0x04 /* Device dma timing */ 54 #define R4030_DMA_MODE_240NS 0x05 /* Device dma timing */ 55 #define R4030_DMA_MODE_280NS 0x06 /* Device dma timing */ 56 #define R4030_DMA_MODE_320NS 0x07 /* Device dma timing */ 57 #define R4030_DMA_MODE_8 0x08 /* Device 8 bit */ 58 #define R4030_DMA_MODE_16 0x10 /* Device 16 bit */ 59 #define R4030_DMA_MODE_32 0x18 /* Device 32 bit */ 60 #define R4030_DMA_MODE_INT 0x20 /* Interrupt when done */ 61 #define R4030_DMA_MODE_BURST 0x40 /* Burst mode (Rev 2 only) */ 62 #define R4030_DMA_MODE_FAST 0x80 /* Fast dma cycle (Rev 2 only) */ 63 #define R4030_DMA_MODE_MASK 0xff /* Mode register bits */ 64 #define DMA_DIR_WRITE 0x100 /* Software direction status */ 65 #define DMA_DIR_READ 0x000 /* Software direction status */ 66 67 #define R4030_DMA_ENAB 0x08 68 #define R4030_DMA_ENAB_RUN 0x0001 /* Enable dma */ 69 #define R4030_DMA_ENAB_READ 0x0000 /* Read from device */ 70 #define R4030_DMA_ENAB_WRITE 0x0002 /* Write to device */ 71 #define R4030_DMA_ENAB_TC_IE 0x0100 /* Terminal count int enable */ 72 #define R4030_DMA_ENAB_ME_IE 0x0200 /* Memory error int enable */ 73 #define R4030_DMA_ENAB_TL_IE 0x0400 /* Translation limit int enable */ 74 75 #define R4030_DMA_COUNT 0x10 76 #define R4030_DMA_COUNT_MASK 0x000fffff /* Byte count mask */ 77 78 #define R4030_DMA_ADDR 0x18 79 80 #define R4030_DMA_RANGE 0x20 81 82 /* 83 * Structure used to control dma. 84 */ 85 86 typedef struct dma_softc { 87 struct device sc_dev; /* use as a device */ 88 struct esp_softc *sc_esp; 89 bus_addr_t dma_va; /* Viritual address for transfer */ 90 int mode; /* Mode register value and direction */ 91 jazz_dma_pte_t *pte_base; /* Pointer to dma tlb array */ 92 int pte_size; /* Size of pte allocated pte array */ 93 pDmaReg dma_reg; /* Pointer to dma registers */ 94 int sc_active; /* Active flag */ 95 void (*reset)(struct dma_softc *); /* Reset routine pointer */ 96 void (*enintr)(struct dma_softc *); /* Int enab routine pointer */ 97 void (*map)(struct dma_softc *, char *, size_t, int); 98 /* Map a dma viritual area */ 99 void (*start)(struct dma_softc *, caddr_t, size_t, int); 100 /* Start routine pointer */ 101 int (*isintr)(struct dma_softc *); /* Int check routine pointer */ 102 int (*intr)(struct dma_softc *); /* Interrupt routine pointer */ 103 void (*end)(struct dma_softc *); /* Interrupt routine pointer */ 104 } dma_softc_t; 105 106 #define DMA_TO_DEV 0 107 #define DMA_FROM_DEV 1 108 109 #define DMA_RESET(r) ((r->reset)(r)) 110 #define DMA_START(a, b, c, d) ((a->start)(a, b, c, d)) 111 #define DMA_MAP(a, b, c, d) ((a->map)(a, b, c, d)) 112 #define DMA_INTR(r) ((r->intr)(r)) 113 #define DMA_DRAIN(r) 114 #define DMA_END(r) ((r->end)(r)) 115 116 void picaDmaTLBAlloc __P((dma_softc_t *)); 117 void picaDmaTLBFree __P((dma_softc_t *)); 118 void picaDmaMap __P((struct dma_softc *, char *, size_t, int)); 119 void picaDmaStart __P((struct dma_softc *, char *, size_t, int)); 120 void picaDmaFlush __P((struct dma_softc *, char *, size_t, int)); 121 void asc_dma_init __P((struct dma_softc *)); 122
Indexes created Thu Oct 02 14:10:14 GMT 2025