fdc_jazzio.c revision 1.7
1 /* $NetBSD: fdc_jazzio.c,v 1.7 2003/05/03 18:10:45 wiz Exp $ */ 2 /* $OpenBSD: fd.c,v 1.6 1998/10/03 21:18:57 millert Exp $ */ 3 /* NetBSD: fd.c,v 1.78 1995/07/04 07:23:09 mycroft Exp */ 4 5 /*- 6 * Copyright (c) 1998 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Charles M. Hannum. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /*- 42 * Copyright (c) 1990 The Regents of the University of California. 43 * All rights reserved. 44 * 45 * This code is derived from software contributed to Berkeley by 46 * Don Ahn. 47 * 48 * Redistribution and use in source and binary forms, with or without 49 * modification, are permitted provided that the following conditions 50 * are met: 51 * 1. Redistributions of source code must retain the above copyright 52 * notice, this list of conditions and the following disclaimer. 53 * 2. Redistributions in binary form must reproduce the above copyright 54 * notice, this list of conditions and the following disclaimer in the 55 * documentation and/or other materials provided with the distribution. 56 * 3. All advertising materials mentioning features or use of this software 57 * must display the following acknowledgement: 58 * This product includes software developed by the University of 59 * California, Berkeley and its contributors. 60 * 4. Neither the name of the University nor the names of its contributors 61 * may be used to endorse or promote products derived from this software 62 * without specific prior written permission. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 * 76 * @(#)fd.c 7.4 (Berkeley) 5/25/91 77 */ 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/callout.h> 82 #include <sys/device.h> 83 84 #include <machine/autoconf.h> 85 #include <machine/bus.h> 86 87 #include <arc/jazz/jazzdmatlbreg.h> 88 #include <arc/jazz/fdreg.h> 89 #include <arc/jazz/fdcvar.h> 90 #include <arc/jazz/jazziovar.h> 91 #include <arc/jazz/dma.h> 92 93 /* controller driver configuration */ 94 int fdc_jazzio_probe(struct device *, struct cfdata *, void *); 95 void fdc_jazzio_attach(struct device *, struct device *, void *); 96 97 /* MD DMA hook functions */ 98 void fdc_jazzio_dma_start(struct fdc_softc *, caddr_t, size_t, int); 99 void fdc_jazzio_dma_abort(struct fdc_softc *); 100 void fdc_jazzio_dma_done(struct fdc_softc *); 101 102 /* software state, per controller */ 103 struct fdc_jazzio_softc { 104 struct fdc_softc sc_fdc; /* base fdc device */ 105 106 bus_space_handle_t sc_baseioh; /* base I/O handle */ 107 bus_space_handle_t sc_dmaioh; /* DMA I/O handle */ 108 109 bus_dma_tag_t sc_dmat; /* bus_dma tag */ 110 bus_dmamap_t sc_dmamap; /* bus_dma map */ 111 int sc_datain; /* data direction */ 112 }; 113 114 CFATTACH_DECL(fdc_jazzio, sizeof(struct fdc_jazzio_softc), 115 fdc_jazzio_probe, fdc_jazzio_attach, NULL, NULL); 116 117 #define FDC_NPORT 6 118 #define FDC_OFFSET 2 /* Should we use bus_space_subregion() or not? */ 119 120 int 121 fdc_jazzio_probe(parent, match, aux) 122 struct device *parent; 123 struct cfdata *match; 124 void *aux; 125 { 126 struct jazzio_attach_args *ja = aux; 127 bus_space_tag_t iot; 128 bus_space_handle_t base_ioh, ioh; 129 int rv; 130 131 if (strcmp(ja->ja_name, "I82077") != 0) 132 return 0; 133 134 iot = ja->ja_bust; 135 rv = 0; 136 137 /* Map the I/O space. */ 138 if (bus_space_map(iot, ja->ja_addr, 139 FDC_OFFSET + FDC_NPORT, 0, &base_ioh)) 140 return 0; 141 142 if (bus_space_subregion(iot, base_ioh, FDC_OFFSET, FDC_NPORT, &ioh)) 143 goto out; 144 145 /* reset */ 146 bus_space_write_1(iot, ioh, FDOUT, 0); 147 delay(100); 148 bus_space_write_1(iot, ioh, FDOUT, FDO_FRST); 149 150 /* see if it can handle a command */ 151 if (out_fdc(iot, ioh, NE7CMD_SPECIFY) < 0) 152 goto out; 153 out_fdc(iot, ioh, 0xdf); /* XXX */ 154 out_fdc(iot, ioh, 2); /* XXX */ 155 156 rv = 1; 157 158 out: 159 bus_space_unmap(iot, base_ioh, FDC_OFFSET + FDC_NPORT); 160 return rv; 161 } 162 163 void 164 fdc_jazzio_attach(parent, self, aux) 165 struct device *parent, *self; 166 void *aux; 167 { 168 struct fdc_jazzio_softc *jsc = (struct fdc_jazzio_softc *)self; 169 struct fdc_softc *fdc = &jsc->sc_fdc; 170 struct jazzio_attach_args *ja = aux; 171 172 fdc->sc_iot = ja->ja_bust; 173 174 fdc->sc_maxiosize = MAXPHYS; 175 fdc->sc_dma_start = fdc_jazzio_dma_start; 176 fdc->sc_dma_abort = fdc_jazzio_dma_abort; 177 fdc->sc_dma_done = fdc_jazzio_dma_done; 178 179 jsc->sc_dmat = ja->ja_dmat; 180 181 if (bus_space_map(fdc->sc_iot, ja->ja_addr, 182 FDC_OFFSET + FDC_NPORT, 0, &jsc->sc_baseioh)) { 183 printf(": unable to map I/O space\n"); 184 return; 185 } 186 187 if (bus_space_subregion(fdc->sc_iot, jsc->sc_baseioh, 188 FDC_OFFSET, FDC_NPORT, &fdc->sc_ioh)) { 189 printf(": unable to subregion I/O space\n"); 190 goto out_unmap1; 191 } 192 193 if (bus_space_map(fdc->sc_iot, jazzio_conf->jc_fdcdmareg, 194 R4030_DMA_RANGE, 0, &jsc->sc_dmaioh)) { 195 printf(": unable to map DMA I/O space\n"); 196 goto out_unmap1; 197 } 198 199 if (bus_dmamap_create(jsc->sc_dmat, MAXPHYS, 1, MAXPHYS, 0, 200 BUS_DMA_ALLOCNOW|BUS_DMA_NOWAIT, &jsc->sc_dmamap)) { 201 printf(": unable to create DMA map\n"); 202 goto out_unmap2; 203 } 204 205 printf("\n"); 206 207 jazzio_intr_establish(ja->ja_intr, fdcintr, fdc); 208 209 fdcattach(fdc); 210 return; 211 212 out_unmap2: 213 bus_space_unmap(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_RANGE); 214 out_unmap1: 215 bus_space_unmap(fdc->sc_iot, jsc->sc_baseioh, FDC_OFFSET + FDC_NPORT); 216 } 217 218 void 219 fdc_jazzio_dma_start(fdc, addr, size, datain) 220 struct fdc_softc *fdc; 221 caddr_t addr; 222 size_t size; 223 int datain; 224 { 225 struct fdc_jazzio_softc *jsc = (void *)fdc; 226 227 /* halt DMA */ 228 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_ENAB, 0); 229 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_MODE, 0); 230 231 jsc->sc_datain = datain; 232 233 bus_dmamap_load(jsc->sc_dmat, jsc->sc_dmamap, addr, size, NULL, 234 BUS_DMA_NOWAIT | BUS_DMA_STREAMING | 235 (datain ? BUS_DMA_READ : BUS_DMA_WRITE)); 236 bus_dmamap_sync(jsc->sc_dmat, jsc->sc_dmamap, 237 0, jsc->sc_dmamap->dm_mapsize, 238 datain ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE); 239 240 /* load new transfer parameters */ 241 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, 242 R4030_DMA_ADDR, jsc->sc_dmamap->dm_segs[0].ds_addr); 243 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, 244 R4030_DMA_COUNT, jsc->sc_dmamap->dm_segs[0].ds_len); 245 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, 246 R4030_DMA_MODE, R4030_DMA_MODE_160NS | R4030_DMA_MODE_8); 247 248 /* start DMA */ 249 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, 250 R4030_DMA_ENAB, R4030_DMA_ENAB_RUN | 251 (datain ? R4030_DMA_ENAB_READ : R4030_DMA_ENAB_WRITE)); 252 } 253 254 void 255 fdc_jazzio_dma_abort(fdc) 256 struct fdc_softc *fdc; 257 { 258 struct fdc_jazzio_softc *jsc = (void *)fdc; 259 260 /* halt DMA */ 261 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_ENAB, 0); 262 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_MODE, 0); 263 } 264 265 void 266 fdc_jazzio_dma_done(fdc) 267 struct fdc_softc *fdc; 268 { 269 struct fdc_jazzio_softc *jsc = (void *)fdc; 270 271 /* halt DMA */ 272 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_COUNT, 0); 273 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_ENAB, 0); 274 bus_space_write_4(fdc->sc_iot, jsc->sc_dmaioh, R4030_DMA_MODE, 0); 275 276 bus_dmamap_sync(jsc->sc_dmat, jsc->sc_dmamap, 277 0, jsc->sc_dmamap->dm_mapsize, 278 jsc->sc_datain ? BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE); 279 bus_dmamap_unload(jsc->sc_dmat, jsc->sc_dmamap); 280 } 281
Indexes created Thu Oct 02 10:09:58 GMT 2025