jazzio.c revision 1.2 1 1.2 tsutsui /* $NetBSD: jazzio.c,v 1.2 2001/02/17 04:27:55 tsutsui Exp $ */
2 1.1 ur /* $OpenBSD: picabus.c,v 1.11 1999/01/11 05:11:10 millert Exp $ */
3 1.1 ur /* NetBSD: tc.c,v 1.2 1995/03/08 00:39:05 cgd Exp */
4 1.1 ur
5 1.1 ur /*
6 1.1 ur * Copyright (c) 1994, 1995 Carnegie-Mellon University.
7 1.1 ur * All rights reserved.
8 1.1 ur *
9 1.1 ur * Author: Chris G. Demetriou
10 1.1 ur * Author: Per Fogelstrom. (Mips R4x00)
11 1.1 ur *
12 1.1 ur * Permission to use, copy, modify and distribute this software and
13 1.1 ur * its documentation is hereby granted, provided that both the copyright
14 1.1 ur * notice and this permission notice appear in all copies of the
15 1.1 ur * software, derivative works or modified versions, and any portions
16 1.1 ur * thereof, and that both notices appear in supporting documentation.
17 1.1 ur *
18 1.1 ur * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
19 1.1 ur * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
20 1.1 ur * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
21 1.1 ur *
22 1.1 ur * Carnegie Mellon requests users of this software to return to
23 1.1 ur *
24 1.1 ur * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
25 1.1 ur * School of Computer Science
26 1.1 ur * Carnegie Mellon University
27 1.1 ur * Pittsburgh PA 15213-3890
28 1.1 ur *
29 1.1 ur * any improvements or extensions that they make and grant Carnegie the
30 1.1 ur * rights to redistribute these changes.
31 1.1 ur */
32 1.1 ur
33 1.1 ur #include <sys/param.h>
34 1.1 ur #include <sys/systm.h>
35 1.1 ur #include <sys/proc.h>
36 1.1 ur #include <sys/user.h>
37 1.1 ur #include <sys/device.h>
38 1.1 ur
39 1.1 ur #include <uvm/uvm_extern.h>
40 1.1 ur
41 1.1 ur #include <machine/bus.h>
42 1.1 ur #include <machine/intr.h>
43 1.1 ur #include <machine/cpu.h>
44 1.1 ur #include <machine/pio.h>
45 1.1 ur #include <machine/autoconf.h>
46 1.1 ur
47 1.1 ur #include <arc/jazz/jazziovar.h>
48 1.1 ur #include <arc/jazz/pica.h>
49 1.1 ur #include <arc/jazz/rd94.h>
50 1.1 ur #include <arc/arc/arctype.h>
51 1.1 ur #include <arc/jazz/jazzdmatlbreg.h>
52 1.1 ur #include <arc/jazz/dma.h>
53 1.1 ur
54 1.1 ur struct jazzio_softc {
55 1.1 ur struct device sc_dv;
56 1.1 ur struct abus sc_bus;
57 1.1 ur struct arc_bus_dma_tag sc_dmat;
58 1.1 ur struct pica_dev *sc_devs;
59 1.1 ur };
60 1.1 ur
61 1.1 ur /* Definition of the driver for autoconfig. */
62 1.1 ur int jazziomatch(struct device *, struct cfdata *, void *);
63 1.1 ur void jazzioattach(struct device *, struct device *, void *);
64 1.1 ur int jazzioprint(void *, const char *);
65 1.1 ur
66 1.1 ur struct cfattach jazzio_ca = {
67 1.1 ur sizeof(struct jazzio_softc), jazziomatch, jazzioattach
68 1.1 ur };
69 1.1 ur extern struct cfdriver jazzio_cd;
70 1.1 ur
71 1.1 ur void jazzio_intr_establish(int, int (*)(void *), void *);
72 1.1 ur void jazzio_intr_disestablish(int);
73 1.1 ur int pica_iointr(unsigned int, struct clockframe *);
74 1.1 ur int pica_clkintr(unsigned int, struct clockframe *);
75 1.1 ur int rd94_iointr(unsigned int, struct clockframe *);
76 1.1 ur int rd94_clkintr(unsigned int, struct clockframe *);
77 1.1 ur
78 1.1 ur intr_handler_t pica_clock_handler;
79 1.1 ur
80 1.1 ur /*
81 1.1 ur * Interrupt dispatch table.
82 1.1 ur */
83 1.1 ur struct pica_int_desc int_table[] = {
84 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 0 */
85 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 1 */
86 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 2 */
87 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 3 */
88 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 4 */
89 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 5 */
90 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 6 */
91 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 7 */
92 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 8 */
93 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 9 */
94 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 10 */
95 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 11 */
96 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 12 */
97 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 13 */
98 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 14 */
99 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 15 */
100 1.1 ur };
101 1.1 ur
102 1.1 ur struct pica_dev {
103 1.1 ur struct confargs ps_ca;
104 1.1 ur u_int ps_mask;
105 1.1 ur intr_handler_t ps_handler;
106 1.1 ur caddr_t ps_base;
107 1.1 ur };
108 1.1 ur
109 1.1 ur struct pica_dev acer_pica_61_cpu[] = {
110 1.1 ur {{ "dallas_rtc",0, 0, },
111 1.1 ur 0, pica_intrnull, (void *)PICA_SYS_CLOCK, },
112 1.1 ur {{ "lpt", 1, 0, },
113 1.1 ur PICA_SYS_LB_IE_PAR1, pica_intrnull, (void *)PICA_SYS_PAR1, },
114 1.1 ur {{ "fdc", 2, 0, },
115 1.1 ur PICA_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)PICA_SYS_FLOPPY, },
116 1.1 ur {{ NULL, 3, NULL, },
117 1.1 ur 0, pica_intrnull, (void *)NULL, },
118 1.1 ur {{ "vga", 4, NULL, },
119 1.1 ur 0, pica_intrnull, (void *)PICA_V_LOCAL_VIDEO, },
120 1.1 ur {{ "sonic", 5, 0, },
121 1.1 ur PICA_SYS_LB_IE_SONIC, pica_intrnull, (void *)PICA_SYS_SONIC, },
122 1.1 ur {{ "asc", 6, 0, },
123 1.1 ur PICA_SYS_LB_IE_SCSI, pica_intrnull, (void *)PICA_SYS_SCSI, },
124 1.1 ur {{ "pckbd", 7, 0, },
125 1.1 ur PICA_SYS_LB_IE_KBD, pica_intrnull, (void *)PICA_SYS_KBD, },
126 1.1 ur {{ "pms", 8, NULL, },
127 1.1 ur PICA_SYS_LB_IE_MOUSE, pica_intrnull, (void *)PICA_SYS_KBD, },
128 1.1 ur {{ "com", 9, 0, },
129 1.1 ur PICA_SYS_LB_IE_COM1, pica_intrnull, (void *)PICA_SYS_COM1, },
130 1.1 ur {{ "com", 10, 0, },
131 1.1 ur PICA_SYS_LB_IE_COM2, pica_intrnull, (void *)PICA_SYS_COM2, },
132 1.1 ur {{ NULL, -1, NULL, },
133 1.1 ur 0, NULL, (void *)NULL, },
134 1.1 ur };
135 1.1 ur
136 1.1 ur struct pica_dev mips_magnum_r4000_cpu[] = {
137 1.1 ur {{ "dallas_rtc",0, 0, },
138 1.1 ur 0, pica_intrnull, (void *)PICA_SYS_CLOCK, },
139 1.1 ur {{ "lpt", 1, 0, },
140 1.1 ur PICA_SYS_LB_IE_PAR1, pica_intrnull, (void *)PICA_SYS_PAR1, },
141 1.1 ur {{ "fdc", 2, 0, },
142 1.1 ur PICA_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)PICA_SYS_FLOPPY, },
143 1.1 ur {{ NULL, 3, NULL, },
144 1.1 ur 0, pica_intrnull, (void *)NULL, },
145 1.1 ur {{ "vxl", 4, 0, },
146 1.1 ur PICA_SYS_LB_IE_VIDEO, pica_intrnull, (void *)PICA_V_LOCAL_VIDEO, },
147 1.1 ur {{ "sonic", 5, 0, },
148 1.1 ur PICA_SYS_LB_IE_SONIC, pica_intrnull, (void *)PICA_SYS_SONIC, },
149 1.1 ur {{ "asc", 6, 0, },
150 1.1 ur PICA_SYS_LB_IE_SCSI, pica_intrnull, (void *)PICA_SYS_SCSI, },
151 1.1 ur {{ "pckbd", 7, 0, },
152 1.1 ur PICA_SYS_LB_IE_KBD, pica_intrnull, (void *)PICA_SYS_KBD, },
153 1.1 ur {{ "pms", 8, NULL, },
154 1.1 ur PICA_SYS_LB_IE_MOUSE, pica_intrnull, (void *)PICA_SYS_KBD, },
155 1.1 ur {{ "com", 9, 0, },
156 1.1 ur PICA_SYS_LB_IE_COM1, pica_intrnull, (void *)PICA_SYS_COM1, },
157 1.1 ur {{ "com", 10, 0, },
158 1.1 ur PICA_SYS_LB_IE_COM2, pica_intrnull, (void *)PICA_SYS_COM2, },
159 1.1 ur {{ NULL, -1, NULL, },
160 1.1 ur 0, NULL, (void *)NULL, },
161 1.1 ur };
162 1.1 ur
163 1.1 ur struct pica_dev nec_rd94_cpu[] = {
164 1.1 ur {{ "dallas_rtc",0, 0, },
165 1.1 ur 0, pica_intrnull, (void *)RD94_SYS_CLOCK, },
166 1.1 ur {{ "lpt", 1, 0, },
167 1.1 ur RD94_SYS_LB_IE_PAR1, pica_intrnull, (void *)RD94_SYS_PAR1, },
168 1.1 ur {{ "fdc", 2, 0, },
169 1.1 ur RD94_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)RD94_SYS_FLOPPY, },
170 1.1 ur {{ NULL, 3, NULL, },
171 1.1 ur 0, pica_intrnull, (void *)NULL, },
172 1.1 ur {{ "sonic", 4, 0, },
173 1.1 ur RD94_SYS_LB_IE_SONIC, pica_intrnull, (void *)RD94_SYS_SONIC, },
174 1.1 ur {{ NULL, 5, 0, },
175 1.1 ur 0, pica_intrnull, (void *)NULL, },
176 1.1 ur {{ NULL, 6, NULL, },
177 1.1 ur 0, pica_intrnull, (void *)NULL, },
178 1.1 ur {{ "pckbd", 7, 0, },
179 1.1 ur RD94_SYS_LB_IE_KBD, pica_intrnull, (void *)RD94_SYS_KBD, },
180 1.1 ur {{ "pms", 8, NULL, },
181 1.1 ur RD94_SYS_LB_IE_MOUSE, pica_intrnull, (void *)RD94_SYS_KBD, },
182 1.1 ur {{ "com", 9, 0, },
183 1.1 ur RD94_SYS_LB_IE_COM1, pica_intrnull, (void *)RD94_SYS_COM1, },
184 1.1 ur {{ "com", 10, 0, },
185 1.1 ur RD94_SYS_LB_IE_COM2, pica_intrnull, (void *)RD94_SYS_COM2, },
186 1.1 ur {{ NULL, -1, NULL, },
187 1.1 ur 0, NULL, (void *)NULL, },
188 1.1 ur };
189 1.1 ur
190 1.1 ur struct pica_dev *pica_cpu_devs[] = {
191 1.1 ur NULL, /* Unused */
192 1.1 ur acer_pica_61_cpu, /* Acer PICA */
193 1.1 ur mips_magnum_r4000_cpu, /* Mips MAGNUM R4000 */
194 1.1 ur nec_rd94_cpu, /* NEC-R94 */
195 1.1 ur nec_rd94_cpu, /* NEC-RA'94 */
196 1.1 ur nec_rd94_cpu, /* NEC-RD94 */
197 1.1 ur nec_rd94_cpu, /* NEC-R96 */
198 1.2 tsutsui NULL,
199 1.2 tsutsui NULL,
200 1.2 tsutsui NULL,
201 1.2 tsutsui NULL,
202 1.2 tsutsui nec_rd94_cpu, /* NEC-JC94 */
203 1.1 ur };
204 1.1 ur int npica_cpu_devs = sizeof pica_cpu_devs / sizeof pica_cpu_devs[0];
205 1.1 ur
206 1.1 ur int jazzio_found = 0;
207 1.1 ur int local_int_mask = 0; /* Local interrupt enable mask */
208 1.1 ur
209 1.1 ur extern struct arc_bus_space pica_bus;
210 1.1 ur
211 1.1 ur int
212 1.1 ur jazziomatch(parent, match, aux)
213 1.1 ur struct device *parent;
214 1.1 ur struct cfdata *match;
215 1.1 ur void *aux;
216 1.1 ur {
217 1.1 ur struct confargs *ca = aux;
218 1.1 ur
219 1.1 ur /* Make sure that we're looking for a PICA. */
220 1.1 ur if (strcmp(ca->ca_name, jazzio_cd.cd_name) != 0)
221 1.1 ur return (0);
222 1.1 ur
223 1.1 ur /* Make sure that unit exists. */
224 1.1 ur if (jazzio_found ||
225 1.1 ur cputype > npica_cpu_devs || pica_cpu_devs[cputype] == NULL)
226 1.1 ur return (0);
227 1.1 ur
228 1.1 ur return (1);
229 1.1 ur }
230 1.1 ur
231 1.1 ur void
232 1.1 ur jazzioattach(parent, self, aux)
233 1.1 ur struct device *parent;
234 1.1 ur struct device *self;
235 1.1 ur void *aux;
236 1.1 ur {
237 1.1 ur struct jazzio_softc *sc = (struct jazzio_softc *)self;
238 1.1 ur struct jazzio_attach_args ja;
239 1.1 ur int i;
240 1.1 ur
241 1.1 ur printf("\n");
242 1.1 ur
243 1.1 ur jazzio_found = 1;
244 1.1 ur
245 1.1 ur /* keep our CPU device description handy */
246 1.1 ur sc->sc_devs = pica_cpu_devs[cputype];
247 1.1 ur
248 1.1 ur /* set up interrupt handlers */
249 1.1 ur switch (cputype) {
250 1.1 ur case ACER_PICA_61:
251 1.1 ur case MAGNUM:
252 1.1 ur set_intr(MIPS_INT_MASK_1, pica_iointr, 2);
253 1.1 ur break;
254 1.1 ur case NEC_R94:
255 1.1 ur case NEC_RAx94:
256 1.1 ur case NEC_RD94:
257 1.1 ur case NEC_R96:
258 1.2 tsutsui case NEC_JC94:
259 1.1 ur set_intr(MIPS_INT_MASK_1, rd94_iointr, 2);
260 1.1 ur break;
261 1.1 ur }
262 1.1 ur
263 1.1 ur sc->sc_bus.ab_dv = (struct device *)sc;
264 1.1 ur
265 1.1 ur /* Initialize PICA Dma */
266 1.1 ur picaDmaInit();
267 1.1 ur
268 1.1 ur /* Create bus_dma_tag */
269 1.1 ur jazz_bus_dma_tag_init(&sc->sc_dmat);
270 1.1 ur
271 1.1 ur /* Try to configure each PICA attached device */
272 1.1 ur for (i = 0; sc->sc_devs[i].ps_ca.ca_slot >= 0; i++) {
273 1.1 ur
274 1.1 ur if(sc->sc_devs[i].ps_ca.ca_name == NULL)
275 1.1 ur continue; /* Empty slot */
276 1.1 ur
277 1.1 ur ja.ja_name = sc->sc_devs[i].ps_ca.ca_name;
278 1.1 ur ja.ja_bus = &sc->sc_bus;
279 1.1 ur ja.ja_bust = &pica_bus;
280 1.1 ur ja.ja_dmat = &sc->sc_dmat;
281 1.1 ur ja.ja_addr = (bus_addr_t)sc->sc_devs[i].ps_base;
282 1.1 ur ja.ja_intr = sc->sc_devs[i].ps_ca.ca_slot;
283 1.1 ur ja.ja_dma = 0;
284 1.1 ur
285 1.1 ur /* Tell the autoconfig machinery we've found the hardware. */
286 1.1 ur config_found(self, &ja, jazzioprint);
287 1.1 ur }
288 1.1 ur }
289 1.1 ur
290 1.1 ur int
291 1.1 ur jazzioprint(aux, pnp)
292 1.1 ur void *aux;
293 1.1 ur const char *pnp;
294 1.1 ur {
295 1.1 ur struct jazzio_attach_args *ja = aux;
296 1.1 ur
297 1.1 ur if (pnp)
298 1.1 ur printf("%s at %s", ja->ja_name, pnp);
299 1.1 ur printf(" addr 0x%lx intr %d", ja->ja_addr, ja->ja_intr);
300 1.1 ur return (UNCONF);
301 1.1 ur }
302 1.1 ur
303 1.1 ur void
304 1.1 ur jazzio_intr_establish(slot, handler, val)
305 1.1 ur int slot;
306 1.1 ur intr_handler_t handler;
307 1.1 ur void *val;
308 1.1 ur {
309 1.1 ur struct jazzio_softc *sc = jazzio_cd.cd_devs[0];
310 1.1 ur
311 1.1 ur if(slot == 0) { /* Slot 0 is special, clock */
312 1.1 ur pica_clock_handler = handler;
313 1.1 ur switch (cputype) {
314 1.1 ur case ACER_PICA_61:
315 1.1 ur case MAGNUM:
316 1.1 ur set_intr(MIPS_INT_MASK_4, pica_clkintr, 1);
317 1.1 ur break;
318 1.1 ur case NEC_R94:
319 1.1 ur case NEC_RAx94:
320 1.1 ur case NEC_RD94:
321 1.1 ur case NEC_R96:
322 1.2 tsutsui case NEC_JC94:
323 1.1 ur set_intr(MIPS_INT_MASK_3, rd94_clkintr, 1);
324 1.1 ur break;
325 1.1 ur }
326 1.1 ur }
327 1.1 ur
328 1.1 ur if(int_table[slot].int_mask != 0) {
329 1.1 ur panic("pica intr already set");
330 1.1 ur }
331 1.1 ur else {
332 1.1 ur int_table[slot].int_mask = sc->sc_devs[slot].ps_mask;;
333 1.1 ur local_int_mask |= int_table[slot].int_mask;
334 1.1 ur int_table[slot].int_hand = handler;
335 1.1 ur int_table[slot].param = val;
336 1.1 ur }
337 1.1 ur
338 1.1 ur switch (cputype) {
339 1.1 ur case ACER_PICA_61:
340 1.1 ur case MAGNUM:
341 1.1 ur out16(PICA_SYS_LB_IE, local_int_mask);
342 1.1 ur break;
343 1.1 ur
344 1.1 ur case NEC_R94:
345 1.1 ur case NEC_RAx94:
346 1.1 ur case NEC_RD94:
347 1.1 ur case NEC_R96:
348 1.2 tsutsui case NEC_JC94:
349 1.1 ur /* XXX: I don't know why, but firmware does. */
350 1.1 ur if (in32(0xe0000560) != 0)
351 1.1 ur out16(RD94_SYS_LB_IE+2, local_int_mask);
352 1.1 ur else
353 1.1 ur out16(RD94_SYS_LB_IE, local_int_mask);
354 1.1 ur break;
355 1.1 ur }
356 1.1 ur }
357 1.1 ur
358 1.1 ur void
359 1.1 ur jazzio_intr_disestablish(slot)
360 1.1 ur int slot;
361 1.1 ur {
362 1.1 ur if(slot != 0) { /* Slot 0 is special, clock */
363 1.1 ur local_int_mask &= ~int_table[slot].int_mask;
364 1.1 ur int_table[slot].int_mask = 0;
365 1.1 ur int_table[slot].int_hand = pica_intrnull;
366 1.1 ur int_table[slot].param = (void *)NULL;
367 1.1 ur }
368 1.1 ur }
369 1.1 ur
370 1.1 ur int
371 1.1 ur pica_intrnull(val)
372 1.1 ur void *val;
373 1.1 ur {
374 1.1 ur panic("uncaught PICA intr for slot %p", val);
375 1.1 ur }
376 1.1 ur
377 1.1 ur /*
378 1.1 ur * Handle pica i/o interrupt.
379 1.1 ur */
380 1.1 ur int
381 1.1 ur pica_iointr(mask, cf)
382 1.1 ur unsigned mask;
383 1.1 ur struct clockframe *cf;
384 1.1 ur {
385 1.1 ur int vector;
386 1.1 ur
387 1.1 ur while((vector = inb(PVIS) >> 2) != 0) {
388 1.1 ur (*int_table[vector].int_hand)(int_table[vector].param);
389 1.1 ur }
390 1.1 ur return(~0); /* Dont reenable */
391 1.1 ur }
392 1.1 ur
393 1.1 ur /*
394 1.1 ur * Handle pica interval clock interrupt.
395 1.1 ur */
396 1.1 ur int
397 1.1 ur pica_clkintr(mask, cf)
398 1.1 ur unsigned mask;
399 1.1 ur struct clockframe *cf;
400 1.1 ur {
401 1.1 ur int temp;
402 1.1 ur
403 1.1 ur temp = inw(R4030_SYS_IT_STAT);
404 1.1 ur (*pica_clock_handler)(cf);
405 1.1 ur
406 1.1 ur /* Re-enable clock interrupts */
407 1.1 ur splx(MIPS_INT_MASK_4 | MIPS_SR_INT_IE);
408 1.1 ur
409 1.1 ur return(~MIPS_INT_MASK_4); /* Keep clock interrupts enabled */
410 1.1 ur }
411 1.1 ur
412 1.1 ur /*
413 1.1 ur * Handle NEC-RD94 i/o interrupt.
414 1.1 ur */
415 1.1 ur int
416 1.1 ur rd94_iointr(mask, cf)
417 1.1 ur unsigned mask;
418 1.1 ur struct clockframe *cf;
419 1.1 ur {
420 1.1 ur int vector;
421 1.1 ur
422 1.1 ur while((vector = inb(RD94_SYS_INTSTAT1) >> 2) != 0) {
423 1.1 ur (*int_table[vector].int_hand)(int_table[vector].param);
424 1.1 ur }
425 1.1 ur return(~0); /* Dont reenable */
426 1.1 ur }
427 1.1 ur
428 1.1 ur /*
429 1.1 ur * Handle NEC-RD94 interval clock interrupt.
430 1.1 ur */
431 1.1 ur int
432 1.1 ur rd94_clkintr(mask, cf)
433 1.1 ur unsigned mask;
434 1.1 ur struct clockframe *cf;
435 1.1 ur {
436 1.1 ur int temp;
437 1.1 ur
438 1.1 ur temp = in32(RD94_SYS_INTSTAT3);
439 1.1 ur (*pica_clock_handler)(cf);
440 1.1 ur
441 1.1 ur /* Re-enable clock interrupts */
442 1.1 ur splx(MIPS_INT_MASK_3 | MIPS_SR_INT_IE);
443 1.1 ur
444 1.1 ur return(~MIPS_INT_MASK_3); /* Keep clock interrupts enabled */
445 1.1 ur }
446