jazzio.c revision 1.4 1 1.4 tsutsui /* $NetBSD: jazzio.c,v 1.4 2001/04/30 04:52:53 tsutsui Exp $ */
2 1.1 ur /* $OpenBSD: picabus.c,v 1.11 1999/01/11 05:11:10 millert Exp $ */
3 1.1 ur /* NetBSD: tc.c,v 1.2 1995/03/08 00:39:05 cgd Exp */
4 1.1 ur
5 1.1 ur /*
6 1.1 ur * Copyright (c) 1994, 1995 Carnegie-Mellon University.
7 1.1 ur * All rights reserved.
8 1.1 ur *
9 1.1 ur * Author: Chris G. Demetriou
10 1.1 ur * Author: Per Fogelstrom. (Mips R4x00)
11 1.1 ur *
12 1.1 ur * Permission to use, copy, modify and distribute this software and
13 1.1 ur * its documentation is hereby granted, provided that both the copyright
14 1.1 ur * notice and this permission notice appear in all copies of the
15 1.1 ur * software, derivative works or modified versions, and any portions
16 1.1 ur * thereof, and that both notices appear in supporting documentation.
17 1.1 ur *
18 1.1 ur * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
19 1.1 ur * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
20 1.1 ur * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
21 1.1 ur *
22 1.1 ur * Carnegie Mellon requests users of this software to return to
23 1.1 ur *
24 1.1 ur * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU
25 1.1 ur * School of Computer Science
26 1.1 ur * Carnegie Mellon University
27 1.1 ur * Pittsburgh PA 15213-3890
28 1.1 ur *
29 1.1 ur * any improvements or extensions that they make and grant Carnegie the
30 1.1 ur * rights to redistribute these changes.
31 1.1 ur */
32 1.1 ur
33 1.1 ur #include <sys/param.h>
34 1.1 ur #include <sys/systm.h>
35 1.1 ur #include <sys/proc.h>
36 1.1 ur #include <sys/user.h>
37 1.1 ur #include <sys/device.h>
38 1.1 ur
39 1.1 ur #include <uvm/uvm_extern.h>
40 1.1 ur
41 1.1 ur #include <machine/bus.h>
42 1.1 ur #include <machine/intr.h>
43 1.1 ur #include <machine/cpu.h>
44 1.1 ur #include <machine/pio.h>
45 1.1 ur #include <machine/autoconf.h>
46 1.1 ur
47 1.1 ur #include <arc/jazz/jazziovar.h>
48 1.1 ur #include <arc/jazz/pica.h>
49 1.1 ur #include <arc/jazz/rd94.h>
50 1.1 ur #include <arc/arc/arctype.h>
51 1.1 ur #include <arc/jazz/jazzdmatlbreg.h>
52 1.1 ur #include <arc/jazz/dma.h>
53 1.1 ur
54 1.1 ur struct jazzio_softc {
55 1.1 ur struct device sc_dv;
56 1.1 ur struct abus sc_bus;
57 1.1 ur struct arc_bus_dma_tag sc_dmat;
58 1.1 ur struct pica_dev *sc_devs;
59 1.1 ur };
60 1.1 ur
61 1.1 ur /* Definition of the driver for autoconfig. */
62 1.1 ur int jazziomatch(struct device *, struct cfdata *, void *);
63 1.1 ur void jazzioattach(struct device *, struct device *, void *);
64 1.1 ur int jazzioprint(void *, const char *);
65 1.1 ur
66 1.1 ur struct cfattach jazzio_ca = {
67 1.1 ur sizeof(struct jazzio_softc), jazziomatch, jazzioattach
68 1.1 ur };
69 1.1 ur extern struct cfdriver jazzio_cd;
70 1.1 ur
71 1.1 ur void jazzio_intr_establish(int, int (*)(void *), void *);
72 1.1 ur void jazzio_intr_disestablish(int);
73 1.1 ur int pica_iointr(unsigned int, struct clockframe *);
74 1.1 ur int pica_clkintr(unsigned int, struct clockframe *);
75 1.1 ur int rd94_iointr(unsigned int, struct clockframe *);
76 1.1 ur int rd94_clkintr(unsigned int, struct clockframe *);
77 1.1 ur
78 1.1 ur intr_handler_t pica_clock_handler;
79 1.1 ur
80 1.1 ur /*
81 1.1 ur * Interrupt dispatch table.
82 1.1 ur */
83 1.1 ur struct pica_int_desc int_table[] = {
84 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 0 */
85 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 1 */
86 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 2 */
87 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 3 */
88 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 4 */
89 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 5 */
90 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 6 */
91 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 7 */
92 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 8 */
93 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 9 */
94 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 10 */
95 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 11 */
96 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 12 */
97 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 13 */
98 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 14 */
99 1.1 ur {0, pica_intrnull, (void *)NULL, 0 }, /* 15 */
100 1.1 ur };
101 1.1 ur
102 1.1 ur struct pica_dev {
103 1.1 ur struct confargs ps_ca;
104 1.1 ur u_int ps_mask;
105 1.1 ur intr_handler_t ps_handler;
106 1.1 ur caddr_t ps_base;
107 1.1 ur };
108 1.1 ur
109 1.1 ur struct pica_dev acer_pica_61_cpu[] = {
110 1.1 ur {{ "dallas_rtc",0, 0, },
111 1.1 ur 0, pica_intrnull, (void *)PICA_SYS_CLOCK, },
112 1.1 ur {{ "lpt", 1, 0, },
113 1.1 ur PICA_SYS_LB_IE_PAR1, pica_intrnull, (void *)PICA_SYS_PAR1, },
114 1.1 ur {{ "fdc", 2, 0, },
115 1.1 ur PICA_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)PICA_SYS_FLOPPY, },
116 1.1 ur {{ NULL, 3, NULL, },
117 1.1 ur 0, pica_intrnull, (void *)NULL, },
118 1.1 ur {{ "vga", 4, NULL, },
119 1.1 ur 0, pica_intrnull, (void *)PICA_V_LOCAL_VIDEO, },
120 1.1 ur {{ "sonic", 5, 0, },
121 1.1 ur PICA_SYS_LB_IE_SONIC, pica_intrnull, (void *)PICA_SYS_SONIC, },
122 1.1 ur {{ "asc", 6, 0, },
123 1.1 ur PICA_SYS_LB_IE_SCSI, pica_intrnull, (void *)PICA_SYS_SCSI, },
124 1.1 ur {{ "pckbd", 7, 0, },
125 1.1 ur PICA_SYS_LB_IE_KBD, pica_intrnull, (void *)PICA_SYS_KBD, },
126 1.1 ur {{ "pms", 8, NULL, },
127 1.1 ur PICA_SYS_LB_IE_MOUSE, pica_intrnull, (void *)PICA_SYS_KBD, },
128 1.1 ur {{ "com", 9, 0, },
129 1.1 ur PICA_SYS_LB_IE_COM1, pica_intrnull, (void *)PICA_SYS_COM1, },
130 1.1 ur {{ "com", 10, 0, },
131 1.1 ur PICA_SYS_LB_IE_COM2, pica_intrnull, (void *)PICA_SYS_COM2, },
132 1.1 ur {{ NULL, -1, NULL, },
133 1.1 ur 0, NULL, (void *)NULL, },
134 1.1 ur };
135 1.1 ur
136 1.1 ur struct pica_dev mips_magnum_r4000_cpu[] = {
137 1.1 ur {{ "dallas_rtc",0, 0, },
138 1.1 ur 0, pica_intrnull, (void *)PICA_SYS_CLOCK, },
139 1.1 ur {{ "lpt", 1, 0, },
140 1.1 ur PICA_SYS_LB_IE_PAR1, pica_intrnull, (void *)PICA_SYS_PAR1, },
141 1.1 ur {{ "fdc", 2, 0, },
142 1.1 ur PICA_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)PICA_SYS_FLOPPY, },
143 1.1 ur {{ NULL, 3, NULL, },
144 1.1 ur 0, pica_intrnull, (void *)NULL, },
145 1.1 ur {{ "vxl", 4, 0, },
146 1.1 ur PICA_SYS_LB_IE_VIDEO, pica_intrnull, (void *)PICA_V_LOCAL_VIDEO, },
147 1.1 ur {{ "sonic", 5, 0, },
148 1.1 ur PICA_SYS_LB_IE_SONIC, pica_intrnull, (void *)PICA_SYS_SONIC, },
149 1.1 ur {{ "asc", 6, 0, },
150 1.1 ur PICA_SYS_LB_IE_SCSI, pica_intrnull, (void *)PICA_SYS_SCSI, },
151 1.1 ur {{ "pckbd", 7, 0, },
152 1.1 ur PICA_SYS_LB_IE_KBD, pica_intrnull, (void *)PICA_SYS_KBD, },
153 1.1 ur {{ "pms", 8, NULL, },
154 1.1 ur PICA_SYS_LB_IE_MOUSE, pica_intrnull, (void *)PICA_SYS_KBD, },
155 1.1 ur {{ "com", 9, 0, },
156 1.1 ur PICA_SYS_LB_IE_COM1, pica_intrnull, (void *)PICA_SYS_COM1, },
157 1.1 ur {{ "com", 10, 0, },
158 1.1 ur PICA_SYS_LB_IE_COM2, pica_intrnull, (void *)PICA_SYS_COM2, },
159 1.1 ur {{ NULL, -1, NULL, },
160 1.1 ur 0, NULL, (void *)NULL, },
161 1.1 ur };
162 1.1 ur
163 1.1 ur struct pica_dev nec_rd94_cpu[] = {
164 1.1 ur {{ "dallas_rtc",0, 0, },
165 1.1 ur 0, pica_intrnull, (void *)RD94_SYS_CLOCK, },
166 1.1 ur {{ "lpt", 1, 0, },
167 1.1 ur RD94_SYS_LB_IE_PAR1, pica_intrnull, (void *)RD94_SYS_PAR1, },
168 1.1 ur {{ "fdc", 2, 0, },
169 1.1 ur RD94_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)RD94_SYS_FLOPPY, },
170 1.1 ur {{ NULL, 3, NULL, },
171 1.1 ur 0, pica_intrnull, (void *)NULL, },
172 1.1 ur {{ "sonic", 4, 0, },
173 1.1 ur RD94_SYS_LB_IE_SONIC, pica_intrnull, (void *)RD94_SYS_SONIC, },
174 1.4 tsutsui {{ NULL, 5, NULL, },
175 1.1 ur 0, pica_intrnull, (void *)NULL, },
176 1.1 ur {{ NULL, 6, NULL, },
177 1.1 ur 0, pica_intrnull, (void *)NULL, },
178 1.1 ur {{ "pckbd", 7, 0, },
179 1.1 ur RD94_SYS_LB_IE_KBD, pica_intrnull, (void *)RD94_SYS_KBD, },
180 1.1 ur {{ "pms", 8, NULL, },
181 1.1 ur RD94_SYS_LB_IE_MOUSE, pica_intrnull, (void *)RD94_SYS_KBD, },
182 1.1 ur {{ "com", 9, 0, },
183 1.1 ur RD94_SYS_LB_IE_COM1, pica_intrnull, (void *)RD94_SYS_COM1, },
184 1.1 ur {{ "com", 10, 0, },
185 1.1 ur RD94_SYS_LB_IE_COM2, pica_intrnull, (void *)RD94_SYS_COM2, },
186 1.1 ur {{ NULL, -1, NULL, },
187 1.1 ur 0, NULL, (void *)NULL, },
188 1.1 ur };
189 1.1 ur
190 1.4 tsutsui struct pica_dev nec_jc94_cpu[] = {
191 1.4 tsutsui {{ "dallas_rtc",0, 0, },
192 1.4 tsutsui 0, pica_intrnull, (void *)RD94_SYS_CLOCK, },
193 1.4 tsutsui {{ "lpt", 1, 0, },
194 1.4 tsutsui RD94_SYS_LB_IE_PAR1, pica_intrnull, (void *)RD94_SYS_PAR1, },
195 1.4 tsutsui {{ "fdc", 2, 0, },
196 1.4 tsutsui RD94_SYS_LB_IE_FLOPPY,pica_intrnull, (void *)RD94_SYS_FLOPPY, },
197 1.4 tsutsui {{ NULL, 3, NULL, },
198 1.4 tsutsui 0, pica_intrnull, (void *)NULL, },
199 1.4 tsutsui {{ "sonic", 4, 0, },
200 1.4 tsutsui RD94_SYS_LB_IE_SONIC, pica_intrnull, (void *)RD94_SYS_SONIC, },
201 1.4 tsutsui {{ "osiop", 5, 0, },
202 1.4 tsutsui RD94_SYS_LB_IE_SCSI0, pica_intrnull, (void *)RD94_SYS_SCSI0, },
203 1.4 tsutsui {{ "osiop", 6, 0, },
204 1.4 tsutsui RD94_SYS_LB_IE_SCSI1, pica_intrnull, (void *)RD94_SYS_SCSI1, },
205 1.4 tsutsui {{ "pckbd", 7, 0, },
206 1.4 tsutsui RD94_SYS_LB_IE_KBD, pica_intrnull, (void *)RD94_SYS_KBD, },
207 1.4 tsutsui {{ "pms", 8, NULL, },
208 1.4 tsutsui RD94_SYS_LB_IE_MOUSE, pica_intrnull, (void *)RD94_SYS_KBD, },
209 1.4 tsutsui {{ "com", 9, 0, },
210 1.4 tsutsui RD94_SYS_LB_IE_COM1, pica_intrnull, (void *)RD94_SYS_COM1, },
211 1.4 tsutsui {{ "com", 10, 0, },
212 1.4 tsutsui RD94_SYS_LB_IE_COM2, pica_intrnull, (void *)RD94_SYS_COM2, },
213 1.4 tsutsui {{ NULL, -1, NULL, },
214 1.4 tsutsui 0, NULL, (void *)NULL, },
215 1.4 tsutsui };
216 1.4 tsutsui
217 1.1 ur struct pica_dev *pica_cpu_devs[] = {
218 1.1 ur NULL, /* Unused */
219 1.1 ur acer_pica_61_cpu, /* Acer PICA */
220 1.1 ur mips_magnum_r4000_cpu, /* Mips MAGNUM R4000 */
221 1.1 ur nec_rd94_cpu, /* NEC-R94 */
222 1.1 ur nec_rd94_cpu, /* NEC-RA'94 */
223 1.1 ur nec_rd94_cpu, /* NEC-RD94 */
224 1.1 ur nec_rd94_cpu, /* NEC-R96 */
225 1.2 tsutsui NULL,
226 1.2 tsutsui NULL,
227 1.2 tsutsui NULL,
228 1.2 tsutsui NULL,
229 1.4 tsutsui nec_jc94_cpu, /* NEC-JC94 */
230 1.1 ur };
231 1.1 ur int npica_cpu_devs = sizeof pica_cpu_devs / sizeof pica_cpu_devs[0];
232 1.1 ur
233 1.1 ur int jazzio_found = 0;
234 1.1 ur int local_int_mask = 0; /* Local interrupt enable mask */
235 1.1 ur
236 1.1 ur extern struct arc_bus_space pica_bus;
237 1.1 ur
238 1.1 ur int
239 1.1 ur jazziomatch(parent, match, aux)
240 1.1 ur struct device *parent;
241 1.1 ur struct cfdata *match;
242 1.1 ur void *aux;
243 1.1 ur {
244 1.1 ur struct confargs *ca = aux;
245 1.1 ur
246 1.1 ur /* Make sure that we're looking for a PICA. */
247 1.1 ur if (strcmp(ca->ca_name, jazzio_cd.cd_name) != 0)
248 1.1 ur return (0);
249 1.1 ur
250 1.1 ur /* Make sure that unit exists. */
251 1.1 ur if (jazzio_found ||
252 1.1 ur cputype > npica_cpu_devs || pica_cpu_devs[cputype] == NULL)
253 1.1 ur return (0);
254 1.1 ur
255 1.1 ur return (1);
256 1.1 ur }
257 1.1 ur
258 1.1 ur void
259 1.1 ur jazzioattach(parent, self, aux)
260 1.1 ur struct device *parent;
261 1.1 ur struct device *self;
262 1.1 ur void *aux;
263 1.1 ur {
264 1.1 ur struct jazzio_softc *sc = (struct jazzio_softc *)self;
265 1.1 ur struct jazzio_attach_args ja;
266 1.1 ur int i;
267 1.1 ur
268 1.1 ur printf("\n");
269 1.1 ur
270 1.1 ur jazzio_found = 1;
271 1.1 ur
272 1.1 ur /* keep our CPU device description handy */
273 1.1 ur sc->sc_devs = pica_cpu_devs[cputype];
274 1.1 ur
275 1.1 ur /* set up interrupt handlers */
276 1.1 ur switch (cputype) {
277 1.1 ur case ACER_PICA_61:
278 1.1 ur case MAGNUM:
279 1.1 ur set_intr(MIPS_INT_MASK_1, pica_iointr, 2);
280 1.1 ur break;
281 1.1 ur case NEC_R94:
282 1.1 ur case NEC_RAx94:
283 1.1 ur case NEC_RD94:
284 1.1 ur case NEC_R96:
285 1.2 tsutsui case NEC_JC94:
286 1.1 ur set_intr(MIPS_INT_MASK_1, rd94_iointr, 2);
287 1.1 ur break;
288 1.1 ur }
289 1.1 ur
290 1.1 ur sc->sc_bus.ab_dv = (struct device *)sc;
291 1.1 ur
292 1.1 ur /* Initialize PICA Dma */
293 1.1 ur picaDmaInit();
294 1.1 ur
295 1.1 ur /* Create bus_dma_tag */
296 1.1 ur jazz_bus_dma_tag_init(&sc->sc_dmat);
297 1.1 ur
298 1.1 ur /* Try to configure each PICA attached device */
299 1.1 ur for (i = 0; sc->sc_devs[i].ps_ca.ca_slot >= 0; i++) {
300 1.1 ur
301 1.4 tsutsui if (sc->sc_devs[i].ps_ca.ca_name == NULL)
302 1.1 ur continue; /* Empty slot */
303 1.1 ur
304 1.1 ur ja.ja_name = sc->sc_devs[i].ps_ca.ca_name;
305 1.1 ur ja.ja_bus = &sc->sc_bus;
306 1.1 ur ja.ja_bust = &pica_bus;
307 1.1 ur ja.ja_dmat = &sc->sc_dmat;
308 1.1 ur ja.ja_addr = (bus_addr_t)sc->sc_devs[i].ps_base;
309 1.1 ur ja.ja_intr = sc->sc_devs[i].ps_ca.ca_slot;
310 1.1 ur ja.ja_dma = 0;
311 1.1 ur
312 1.1 ur /* Tell the autoconfig machinery we've found the hardware. */
313 1.1 ur config_found(self, &ja, jazzioprint);
314 1.1 ur }
315 1.1 ur }
316 1.1 ur
317 1.1 ur int
318 1.1 ur jazzioprint(aux, pnp)
319 1.1 ur void *aux;
320 1.1 ur const char *pnp;
321 1.1 ur {
322 1.1 ur struct jazzio_attach_args *ja = aux;
323 1.1 ur
324 1.1 ur if (pnp)
325 1.1 ur printf("%s at %s", ja->ja_name, pnp);
326 1.1 ur printf(" addr 0x%lx intr %d", ja->ja_addr, ja->ja_intr);
327 1.1 ur return (UNCONF);
328 1.1 ur }
329 1.1 ur
330 1.1 ur void
331 1.1 ur jazzio_intr_establish(slot, handler, val)
332 1.1 ur int slot;
333 1.1 ur intr_handler_t handler;
334 1.1 ur void *val;
335 1.1 ur {
336 1.1 ur struct jazzio_softc *sc = jazzio_cd.cd_devs[0];
337 1.1 ur
338 1.4 tsutsui if (slot == 0) { /* Slot 0 is special, clock */
339 1.1 ur pica_clock_handler = handler;
340 1.1 ur switch (cputype) {
341 1.1 ur case ACER_PICA_61:
342 1.1 ur case MAGNUM:
343 1.1 ur set_intr(MIPS_INT_MASK_4, pica_clkintr, 1);
344 1.1 ur break;
345 1.1 ur case NEC_R94:
346 1.1 ur case NEC_RAx94:
347 1.1 ur case NEC_RD94:
348 1.1 ur case NEC_R96:
349 1.2 tsutsui case NEC_JC94:
350 1.1 ur set_intr(MIPS_INT_MASK_3, rd94_clkintr, 1);
351 1.1 ur break;
352 1.1 ur }
353 1.1 ur }
354 1.1 ur
355 1.4 tsutsui if (int_table[slot].int_mask != 0) {
356 1.1 ur panic("pica intr already set");
357 1.4 tsutsui } else {
358 1.4 tsutsui int_table[slot].int_mask = sc->sc_devs[slot].ps_mask;
359 1.1 ur local_int_mask |= int_table[slot].int_mask;
360 1.1 ur int_table[slot].int_hand = handler;
361 1.1 ur int_table[slot].param = val;
362 1.1 ur }
363 1.1 ur
364 1.1 ur switch (cputype) {
365 1.1 ur case ACER_PICA_61:
366 1.1 ur case MAGNUM:
367 1.1 ur out16(PICA_SYS_LB_IE, local_int_mask);
368 1.1 ur break;
369 1.1 ur
370 1.1 ur case NEC_R94:
371 1.3 ur case NEC_R96:
372 1.3 ur out16(RD94_SYS_LB_IE2, local_int_mask);
373 1.3 ur break;
374 1.3 ur
375 1.1 ur case NEC_RAx94:
376 1.1 ur case NEC_RD94:
377 1.2 tsutsui case NEC_JC94:
378 1.1 ur /* XXX: I don't know why, but firmware does. */
379 1.1 ur if (in32(0xe0000560) != 0)
380 1.3 ur out16(RD94_SYS_LB_IE2, local_int_mask);
381 1.1 ur else
382 1.3 ur out16(RD94_SYS_LB_IE1, local_int_mask);
383 1.1 ur break;
384 1.1 ur }
385 1.1 ur }
386 1.1 ur
387 1.1 ur void
388 1.1 ur jazzio_intr_disestablish(slot)
389 1.1 ur int slot;
390 1.1 ur {
391 1.4 tsutsui if (slot != 0) { /* Slot 0 is special, clock */
392 1.1 ur local_int_mask &= ~int_table[slot].int_mask;
393 1.1 ur int_table[slot].int_mask = 0;
394 1.1 ur int_table[slot].int_hand = pica_intrnull;
395 1.1 ur int_table[slot].param = (void *)NULL;
396 1.1 ur }
397 1.1 ur }
398 1.1 ur
399 1.1 ur int
400 1.1 ur pica_intrnull(val)
401 1.1 ur void *val;
402 1.1 ur {
403 1.1 ur panic("uncaught PICA intr for slot %p", val);
404 1.1 ur }
405 1.1 ur
406 1.1 ur /*
407 1.1 ur * Handle pica i/o interrupt.
408 1.1 ur */
409 1.1 ur int
410 1.1 ur pica_iointr(mask, cf)
411 1.1 ur unsigned mask;
412 1.1 ur struct clockframe *cf;
413 1.1 ur {
414 1.1 ur int vector;
415 1.1 ur
416 1.4 tsutsui while ((vector = inb(PVIS) >> 2) != 0) {
417 1.1 ur (*int_table[vector].int_hand)(int_table[vector].param);
418 1.1 ur }
419 1.4 tsutsui return (~0); /* Dont reenable */
420 1.1 ur }
421 1.1 ur
422 1.1 ur /*
423 1.1 ur * Handle pica interval clock interrupt.
424 1.1 ur */
425 1.1 ur int
426 1.1 ur pica_clkintr(mask, cf)
427 1.1 ur unsigned mask;
428 1.1 ur struct clockframe *cf;
429 1.1 ur {
430 1.1 ur int temp;
431 1.1 ur
432 1.1 ur temp = inw(R4030_SYS_IT_STAT);
433 1.1 ur (*pica_clock_handler)(cf);
434 1.1 ur
435 1.1 ur /* Re-enable clock interrupts */
436 1.1 ur splx(MIPS_INT_MASK_4 | MIPS_SR_INT_IE);
437 1.1 ur
438 1.4 tsutsui return (~MIPS_INT_MASK_4); /* Keep clock interrupts enabled */
439 1.1 ur }
440 1.1 ur
441 1.1 ur /*
442 1.1 ur * Handle NEC-RD94 i/o interrupt.
443 1.1 ur */
444 1.1 ur int
445 1.1 ur rd94_iointr(mask, cf)
446 1.1 ur unsigned mask;
447 1.1 ur struct clockframe *cf;
448 1.1 ur {
449 1.1 ur int vector;
450 1.1 ur
451 1.4 tsutsui while ((vector = inb(RD94_SYS_INTSTAT1) >> 2) != 0) {
452 1.1 ur (*int_table[vector].int_hand)(int_table[vector].param);
453 1.1 ur }
454 1.4 tsutsui return (~0); /* Dont reenable */
455 1.1 ur }
456 1.1 ur
457 1.1 ur /*
458 1.1 ur * Handle NEC-RD94 interval clock interrupt.
459 1.1 ur */
460 1.1 ur int
461 1.1 ur rd94_clkintr(mask, cf)
462 1.1 ur unsigned mask;
463 1.1 ur struct clockframe *cf;
464 1.1 ur {
465 1.1 ur int temp;
466 1.1 ur
467 1.1 ur temp = in32(RD94_SYS_INTSTAT3);
468 1.1 ur (*pica_clock_handler)(cf);
469 1.1 ur
470 1.1 ur /* Re-enable clock interrupts */
471 1.1 ur splx(MIPS_INT_MASK_3 | MIPS_SR_INT_IE);
472 1.1 ur
473 1.4 tsutsui return (~MIPS_INT_MASK_3); /* Keep clock interrupts enabled */
474 1.1 ur }
475