necpb.c revision 1.15
1 /* $NetBSD: necpb.c,v 1.15 2003/06/15 23:08:56 fvdl Exp $ */ 2 3 /*- 4 * Copyright (c) 1997, 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Christopher G. Demetriou. All rights reserved. 42 * Copyright (c) 1994 Charles M. Hannum. All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Charles M. Hannum. 55 * 4. The name of the author may not be used to endorse or promote products 56 * derived from this software without specific prior written permission. 57 * 58 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 59 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 60 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 61 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 63 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 64 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 65 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 66 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 67 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 68 */ 69 70 #include <sys/types.h> 71 #include <sys/param.h> 72 #include <sys/time.h> 73 #include <sys/systm.h> 74 #include <sys/errno.h> 75 #include <sys/device.h> 76 #include <sys/malloc.h> 77 #include <sys/extent.h> 78 79 #include <uvm/uvm_extern.h> 80 81 #define _ARC_BUS_DMA_PRIVATE 82 #include <machine/bus.h> 83 84 #include <machine/pio.h> 85 86 #include <machine/autoconf.h> 87 #include <machine/cpu.h> 88 #include <machine/platform.h> 89 90 #include <dev/pci/pcivar.h> 91 #include <dev/pci/pcireg.h> 92 93 #include <arc/jazz/rd94.h> 94 #include <arc/pci/necpbvar.h> 95 96 int necpbmatch __P((struct device *, struct cfdata *, void *)); 97 void necpbattach __P((struct device *, struct device *, void *)); 98 99 static int necpbprint __P((void *, const char *)); 100 101 void necpb_attach_hook __P((struct device *, struct device *, 102 struct pcibus_attach_args *)); 103 int necpb_bus_maxdevs __P((pci_chipset_tag_t, int)); 104 pcitag_t necpb_make_tag __P((pci_chipset_tag_t, int, int, int)); 105 void necpb_decompose_tag __P((pci_chipset_tag_t, pcitag_t, int *, 106 int *, int *)); 107 pcireg_t necpb_conf_read __P((pci_chipset_tag_t, pcitag_t, int)); 108 void necpb_conf_write __P((pci_chipset_tag_t, pcitag_t, int, 109 pcireg_t)); 110 int necpb_intr_map __P((struct pci_attach_args *, 111 pci_intr_handle_t *)); 112 const char * necpb_intr_string __P((pci_chipset_tag_t, pci_intr_handle_t)); 113 void * necpb_intr_establish __P((pci_chipset_tag_t, pci_intr_handle_t, 114 int, int (*func)(void *), void *)); 115 void necpb_intr_disestablish __P((pci_chipset_tag_t, void *)); 116 117 int necpb_intr(unsigned, struct clockframe *); 118 119 120 CFATTACH_DECL(necpb, sizeof(struct necpb_softc), 121 necpbmatch, necpbattach, NULL, NULL); 122 123 extern struct cfdriver necpb_cd; 124 125 static struct necpb_intrhand *necpb_inttbl[4]; 126 127 /* There can be only one. */ 128 int necpbfound; 129 struct necpb_context necpb_main_context; 130 static long necpb_mem_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 131 static long necpb_io_ex_storage[EXTENT_FIXED_STORAGE_SIZE(10) / sizeof(long)]; 132 133 int 134 necpbmatch(parent, match, aux) 135 struct device *parent; 136 struct cfdata *match; 137 void *aux; 138 { 139 struct confargs *ca = aux; 140 141 if (strcmp(ca->ca_name, necpb_cd.cd_name) != 0) 142 return (0); 143 144 if (necpbfound) 145 return (0); 146 147 return (1); 148 } 149 150 /* 151 * Set up the chipset's function pointers. 152 */ 153 void 154 necpb_init(ncp) 155 struct necpb_context *ncp; 156 { 157 pcitag_t tag; 158 pcireg_t csr; 159 160 if (ncp->nc_initialized) 161 return; 162 163 arc_large_bus_space_init(&ncp->nc_memt, "necpcimem", 164 RD94_P_PCI_MEM, 0, RD94_S_PCI_MEM); 165 arc_bus_space_init_extent(&ncp->nc_memt, (caddr_t)necpb_mem_ex_storage, 166 sizeof(necpb_mem_ex_storage)); 167 168 arc_bus_space_init(&ncp->nc_iot, "necpciio", 169 RD94_P_PCI_IO, RD94_V_PCI_IO, 0, RD94_S_PCI_IO); 170 arc_bus_space_init_extent(&ncp->nc_iot, (caddr_t)necpb_io_ex_storage, 171 sizeof(necpb_io_ex_storage)); 172 173 jazz_bus_dma_tag_init(&ncp->nc_dmat); 174 175 ncp->nc_pc.pc_attach_hook = necpb_attach_hook; 176 ncp->nc_pc.pc_bus_maxdevs = necpb_bus_maxdevs; 177 ncp->nc_pc.pc_make_tag = necpb_make_tag; 178 ncp->nc_pc.pc_decompose_tag = necpb_decompose_tag; 179 ncp->nc_pc.pc_conf_read = necpb_conf_read; 180 ncp->nc_pc.pc_conf_write = necpb_conf_write; 181 ncp->nc_pc.pc_intr_map = necpb_intr_map; 182 ncp->nc_pc.pc_intr_string = necpb_intr_string; 183 ncp->nc_pc.pc_intr_establish = necpb_intr_establish; 184 ncp->nc_pc.pc_intr_disestablish = necpb_intr_disestablish; 185 186 /* 187 * XXX: 188 * NEC's firmware does not configure PCI devices completely. 189 * We need to disable expansion ROM and enable mem/io/busmaster 190 * bits here. 191 */ 192 tag = necpb_make_tag(&ncp->nc_pc, 0, 3, 0); 193 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 194 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 195 PCI_COMMAND_MASTER_ENABLE; 196 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 197 necpb_conf_write(&ncp->nc_pc, tag, PCI_MAPREG_ROM, 0); 198 199 tag = necpb_make_tag(&ncp->nc_pc, 0, 4, 0); 200 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 201 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 202 PCI_COMMAND_MASTER_ENABLE; 203 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 204 necpb_conf_write(&ncp->nc_pc, tag, PCI_MAPREG_ROM, 0); 205 206 tag = necpb_make_tag(&ncp->nc_pc, 0, 5, 0); 207 csr = necpb_conf_read(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG); 208 csr |= PCI_COMMAND_IO_ENABLE | PCI_COMMAND_MEM_ENABLE | 209 PCI_COMMAND_MASTER_ENABLE; 210 necpb_conf_write(&ncp->nc_pc, tag, PCI_COMMAND_STATUS_REG, csr); 211 necpb_conf_write(&ncp->nc_pc, tag, PCI_MAPREG_ROM, 0); 212 213 ncp->nc_initialized = 1; 214 } 215 216 void 217 necpbattach(parent, self, aux) 218 struct device *parent, *self; 219 void *aux; 220 { 221 struct necpb_softc *sc = (struct necpb_softc *)self; 222 struct pcibus_attach_args pba; 223 int i; 224 225 necpbfound = 1; 226 227 printf("\n"); 228 229 sc->sc_ncp = &necpb_main_context; 230 necpb_init(sc->sc_ncp); 231 232 out32(RD94_SYS_PCI_INTMASK, 0xf); 233 234 for (i = 0; i < 4; i++) 235 necpb_inttbl[i] = NULL; 236 237 (*platform->set_intr)(MIPS_INT_MASK_2, necpb_intr, 3); 238 239 pba.pba_busname = "pci"; 240 pba.pba_iot = &sc->sc_ncp->nc_iot; 241 pba.pba_memt = &sc->sc_ncp->nc_memt; 242 pba.pba_dmat = &sc->sc_ncp->nc_dmat; 243 pba.pba_dmat64 = NULL; 244 pba.pba_pc = &sc->sc_ncp->nc_pc; 245 pba.pba_flags = PCI_FLAGS_IO_ENABLED | PCI_FLAGS_MEM_ENABLED; 246 pba.pba_bus = 0; 247 pba.pba_bridgetag = NULL; 248 249 config_found(self, &pba, necpbprint); 250 } 251 252 static int 253 necpbprint(aux, pnp) 254 void *aux; 255 const char *pnp; 256 { 257 struct pcibus_attach_args *pba = aux; 258 259 if (pnp) 260 aprint_normal("%s at %s", pba->pba_busname, pnp); 261 aprint_normal(" bus %d", pba->pba_bus); 262 return (UNCONF); 263 } 264 265 void 266 necpb_attach_hook(parent, self, pba) 267 struct device *parent, *self; 268 struct pcibus_attach_args *pba; 269 { 270 } 271 272 int 273 necpb_bus_maxdevs(pc, busno) 274 pci_chipset_tag_t pc; 275 int busno; 276 { 277 return (32); 278 } 279 280 pcitag_t 281 necpb_make_tag(pc, bus, device, function) 282 pci_chipset_tag_t pc; 283 int bus, device, function; 284 { 285 pcitag_t tag; 286 287 if (bus >= 256 || device >= 32 || function >= 8) 288 panic("necpb_make_tag: bad request"); 289 290 tag = 0x80000000 | (bus << 16) | (device << 11) | (function << 8); 291 return (tag); 292 } 293 294 void 295 necpb_decompose_tag(pc, tag, bp, dp, fp) 296 pci_chipset_tag_t pc; 297 pcitag_t tag; 298 int *bp, *dp, *fp; 299 { 300 if (bp != NULL) 301 *bp = (tag >> 16) & 0xff; 302 if (dp != NULL) 303 *dp = (tag >> 11) & 0x1f; 304 if (fp != NULL) 305 *fp = (tag >> 8) & 0x07; 306 } 307 308 pcireg_t 309 necpb_conf_read(pc, tag, reg) 310 pci_chipset_tag_t pc; 311 pcitag_t tag; 312 int reg; 313 { 314 pcireg_t data; 315 int s; 316 317 s = splhigh(); 318 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 319 data = in32(RD94_SYS_PCI_CONFDATA); 320 out32(RD94_SYS_PCI_CONFADDR, 0); 321 splx(s); 322 323 return (data); 324 } 325 326 void 327 necpb_conf_write(pc, tag, reg, data) 328 pci_chipset_tag_t pc; 329 pcitag_t tag; 330 int reg; 331 pcireg_t data; 332 { 333 int s; 334 335 s = splhigh(); 336 out32(RD94_SYS_PCI_CONFADDR, tag | reg); 337 out32(RD94_SYS_PCI_CONFDATA, data); 338 out32(RD94_SYS_PCI_CONFADDR, 0); 339 splx(s); 340 } 341 342 int 343 necpb_intr_map(pa, ihp) 344 struct pci_attach_args *pa; 345 pci_intr_handle_t *ihp; 346 { 347 pci_chipset_tag_t pc = pa->pa_pc; 348 pcitag_t intrtag = pa->pa_intrtag; 349 int pin = pa->pa_intrpin; 350 int bus, dev; 351 352 if (pin == 0) { 353 /* No IRQ used. */ 354 *ihp = -1; 355 return (1); 356 } 357 358 if (pin > 4) { 359 printf("necpb_intr_map: bad interrupt pin %d\n", pin); 360 *ihp = -1; 361 return (1); 362 } 363 364 necpb_decompose_tag(pc, intrtag, &bus, &dev, NULL); 365 if (bus != 0) { 366 *ihp = -1; 367 return (1); 368 } 369 370 switch (dev) { 371 case 3: 372 *ihp = (pin+2) % 4; 373 break; 374 case 4: 375 *ihp = (pin+1) % 4; 376 break; 377 case 5: 378 *ihp = (pin) % 4; 379 break; 380 default: 381 *ihp = -1; 382 return (1); 383 } 384 385 return (0); 386 } 387 388 const char * 389 necpb_intr_string(pc, ih) 390 pci_chipset_tag_t pc; 391 pci_intr_handle_t ih; 392 { 393 static char str[8]; 394 395 if (ih >= 4) 396 panic("necpb_intr_string: bogus handle %ld", ih); 397 sprintf(str, "int %c", 'A' + (int)ih); 398 return (str); 399 } 400 401 void * 402 necpb_intr_establish(pc, ih, level, func, arg) 403 pci_chipset_tag_t pc; 404 pci_intr_handle_t ih; 405 int level, (*func) __P((void *)); 406 void *arg; 407 { 408 struct necpb_intrhand *n, *p; 409 u_int32_t mask; 410 411 if (ih >= 4) 412 panic("necpb_intr_establish: bogus handle"); 413 414 n = malloc(sizeof(struct necpb_intrhand), M_DEVBUF, M_NOWAIT); 415 if (n == NULL) 416 panic("necpb_intr_establish: can't malloc interrupt handle"); 417 418 n->ih_func = func; 419 n->ih_arg = arg; 420 n->ih_next = NULL; 421 n->ih_intn = ih; 422 423 if (necpb_inttbl[ih] == NULL) { 424 necpb_inttbl[ih] = n; 425 mask = in32(RD94_SYS_PCI_INTMASK); 426 mask |= 1 << ih; 427 out32(RD94_SYS_PCI_INTMASK, mask); 428 } else { 429 p = necpb_inttbl[ih]; 430 while (p->ih_next != NULL) 431 p = p->ih_next; 432 p->ih_next = n; 433 } 434 435 return n; 436 } 437 438 void 439 necpb_intr_disestablish(pc, cookie) 440 pci_chipset_tag_t pc; 441 void *cookie; 442 { 443 struct necpb_intrhand *n, *p, *q; 444 u_int32_t mask; 445 446 n = cookie; 447 448 q = NULL; 449 p = necpb_inttbl[n->ih_intn]; 450 while (p != n) { 451 if (p == NULL) 452 panic("necpb_intr_disestablish: broken intr table"); 453 q = p; 454 p = p->ih_next; 455 } 456 457 if (q == NULL) { 458 necpb_inttbl[n->ih_intn] = n->ih_next; 459 if (n->ih_next == NULL) { 460 mask = in32(RD94_SYS_PCI_INTMASK); 461 mask &= ~(1 << n->ih_intn); 462 out32(RD94_SYS_PCI_INTMASK, mask); 463 } 464 } else 465 q->ih_next = n->ih_next; 466 467 free(n, M_DEVBUF); 468 } 469 470 /* 471 * Handle PCI/EISA interrupt. 472 */ 473 int 474 necpb_intr(mask, cf) 475 unsigned mask; 476 struct clockframe *cf; 477 { 478 u_int32_t vector, stat; 479 struct necpb_intrhand *p; 480 int a; 481 482 vector = in32(RD94_SYS_INTSTAT2) & 0xffff; 483 484 if (vector == 0x4000) { 485 stat = in32(RD94_SYS_PCI_INTSTAT); 486 stat &= in32(RD94_SYS_PCI_INTMASK); 487 for (a=0; a<4; a++) { 488 if (stat & (1 << a)) { 489 #if 0 490 printf("pint %d\n", a); 491 #endif 492 p = necpb_inttbl[a]; 493 while (p != NULL) { 494 (*p->ih_func)(p->ih_arg); 495 p = p->ih_next; 496 } 497 } 498 } 499 } else if (vector == 0x8000) { 500 printf("eisa_nmi\n"); 501 } else { 502 printf("eint %d\n", vector & 0xff); 503 #if 0 504 eisa_intr(vector & 0xff); 505 #endif 506 } 507 508 return (~0); 509 } 510
Indexes created Thu Oct 23 22:10:10 GMT 2025